JPH04320346A - Manufacture of thin film semiconductor device - Google Patents

Abstract

PURPOSE:To inhibit a reduction in an ON current by eliminating an exposed portion of a gate oxide film with a gate electrode and a source/drain region as a mask, using the gate electrode and the source/drain region as a mask, adding impurity elements to an exposed portion of a non-single crystal semiconductor thin film and forming an offset region. CONSTITUTION:A gate electrode 1-11, a source contact region 1-12, a drain contact region 1-13 are used as a mask. An exposed portion of a gate oxide d film is removed by etching so that a non-single crystal semiconductor thin film may be partially exposed. Then, low concentration impurity elements are added thereto, thereby forming an offset region 1-14. More specifically, the gate electrode 1-13, the source contact region 1-12 and the drain contact region 1-13 are used as a mask so as to form the offset region 1-14 in a self-alignment fashion.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film semiconductor device on an insulating amorphous material such as a quartz substrate or a glass substrate, which has extremely low off-state current and high drain breakdown voltage.

0002

[Prior Art] A method for forming a thin polycrystalline silicon film or a single crystal silicon thin film with large crystal grains with uniform crystal orientation on an amorphous insulating substrate or an amorphous insulating film is as follows.
SOI (Silicon On Insulator)
r) known as technology. {SOI structure formation technology,
Industrial books}. Broadly classified, there are recrystallization methods, epitaxial methods, insulating layer embedding methods, and bonding methods. Recrystallization methods include a method in which silicon is melted and recrystallized by laser annealing or electron beam annealing, and a solid phase growth method in which silicon is grown in a solid phase without raising the temperature to a melting temperature. It is classified into two types. The solid phase growth method is superior in that it can be recrystallized at a relatively low temperature. 550
It has also been reported that crystal grains in silicon thin films grew despite low-temperature heat treatment at ℃. {IEEE
Electron Device Letters
, vol. EDL-8, No. 8, p361, Augu
st1987}.

0003

[Problems to be Solved by the Invention] However, a thin film transistor fabricated using a silicon thin film with excellent crystallinity has a low drain breakdown voltage. One of the reasons is thought to be that the depletion layer expands more easily even under low applied voltage due to the reduction in defects.

[0004] In order to prevent such a decrease in drain breakdown voltage, LDD (Lightly Doped Dra
in) There is a method of forming the structure. This process will be briefly explained with reference to FIG. In FIG. 3, steps from forming a gate electrode to forming an interlayer insulating film will be explained. In FIG. 3(a), 3-1 is an insulating amorphous material, 3-2 is a silicon thin film, 3-3 is a gate insulating film, and 3-4 is a gate electrode.

Next, low concentration ion implantation is performed to form offset regions 3-5. Dose amount is 1×1011c
Nc
If it is h, a donor type impurity such as phosphorus is ion-implanted, and if it is Pch, an acceptor type impurity such as boron is ion-implanted. Arrows 3-6 indicate ion beams.

[0006] Next, a step of forming side walls is started. First, a SiO2 film 3-7 is formed. Thereafter, when the SiO2 film 3-7 is etched by anisotropic etching, a side wall as shown in FIG. 3(d) 3-8 is formed. Next, as shown in FIG. 3E, ions are implanted using the gate electrode 3-4 and side walls 3-8 as masks to form a source region 3-9 and a drain region 3-10. The dose of the source and drain regions is 1×1014 to 1×
The offset area 3-5 is approximately 1016 cm-2.
The dose should be higher than that of

As shown in FIG. 3(f), the interlayer insulating film 3
-12 is formed into a film and activation annealing is performed. After that, a step of forming contact electrodes is started.

In the conventional methods described above, in order to perform anisotropic etching, microwave plasma etching method,
ECR etching method or low pressure magnetron RIE
There are methods such as (Reactive Ion Etching) method. However, these methods, for example 30c
When applied to the processing of large m-square substrates, variations within the substrate become a problem. Side wall 3- as shown in FIG. 3(d)
This problem is serious because the delicate shape of 8 must be controlled. Furthermore, variations in the thickness of the SiO2 film 3-7 also have an effect. Furthermore, there is a problem in that the on-current is reduced due to the structural properties of the LDD structure.

The present invention solves the problems of the conventional process as described above, forms an excellent LDD type thin film transistor without using anisotropic etching technology that has problems with process stability, and has a low off-state current. The purpose of the present invention is to provide a method for creating an excellent thin film transistor with minimal reduction in on-current.

0010

[Means for Solving the Problems] The method for manufacturing a thin film semiconductor device of the present invention provides the following steps in a thin film semiconductor device formed on an insulating amorphous material: [a] On the insulating amorphous material, Step of forming a non-single crystal semiconductor thin film and patterning it into an island shape, [b] Forming a gate insulating film on the non-single crystal semiconductor thin film patterned into an island shape, and applying a resist mask. forming and patterning the gate insulating film to expose at least a part of the surface of the non-single crystal semiconductor thin film; [c] using the resist mask and gate oxide film as a mask, forming a high concentration film; a step of performing ion implantation to form a contact region, [d] After peeling off the resist mask, forming a low resistance impurity-doped semiconductor thin film, and patterning the impurity-doped semiconductor thin film to form the gate. A gate electrode is formed on the insulating film, and a semiconductor layer is formed on the exposed non-single crystal semiconductor thin film.
forming the gate electrode and the source and drain regions; [e] removing the exposed portion of the gate oxide film using the gate electrode and the source and drain regions as masks; [f] forming the gate electrode and the drain region; The method is characterized in that it includes at least a step of adding an impurity element to the exposed portion of the non-single crystal semiconductor thin film using the source and drain regions as a mask to form an offset region.

[0011] Furthermore, the gate electrode and the source,
The drain regions are each separated and insulated.

Furthermore, the impurity concentration of the offset region is lower than the impurity concentration of the contact region and the source and drain regions.

[0013]

Embodiments (Embodiment 1) Embodiment 1 of the present invention will be explained along the steps of manufacturing a thin film transistor having an LDD structure.

A non-single crystal semiconductor thin film is formed on an insulating amorphous material. As the insulating amorphous material, a quartz substrate, a glass substrate, a nitride film, a SiO2 film, or the like is used. When using a quartz substrate, the process temperature is 1200℃.
It is permissible up to about ℃, but when using a glass substrate,
Limited to low temperature processes below 600°C. To form the non-single crystal semiconductor thin film, LPCVD method, plasma CVD method, sputtering method, vapor deposition method, laser annealing method,
There are methods such as solid phase growth method. In the following, a case will be described as an example in which a quartz substrate is used and a solid phase grown Si thin film is used as the non-single crystal semiconductor thin film. In addition to solid phase growth Si thin films, polycrystalline Si thin films and SOI (Silicon
The present invention can also be applied to (on Insulator).

As shown in FIG. 1(a), plasma CVD
Using a device, mix gas of SiH4 and H2 at 13.56M
Amorphous Si is decomposed by high-frequency glow discharge at Hz.
A film 1-2 is deposited on a quartz substrate 1-1. The SiH4 partial pressure of the mixed gas is 10 to 20%, and the internal pressure in the deposit is 0.
It is about 5 to 1.5 torr. The substrate temperature is suitably 250°C or less, about 180°C. The amount of bound hydrogen was determined by infrared absorption measurement and was approximately 8 atomic%. When the chamber is cleaned with Freon before depositing the amorphous Si film 1-2, the subsequently deposited amorphous Si film 2
Contains x1018 cm-3 of fluorine. If such impurity fluorine is contained, solid phase growth will not proceed sufficiently. Therefore, in the present invention, after the Freon cleaning, dummy deposition is performed for about one hour, and then actual deposition is performed. Alternatively, Freon cleaning may be abolished and the chamber may be cleaned using another method such as bead treatment.

[0016] Subsequently, the amorphous Si film was heated at 400°C to 5°C.
Heat treatment is performed at 00°C to release hydrogen. This step aims to prevent explosive desorption of hydrogen.

Next, the amorphous thin film 1-2 is grown in a solid phase. As a solid phase growth method, furnace annealing using a quartz tube is convenient. As the annealing atmosphere, nitrogen gas, hydrogen gas, argon gas, helium gas, etc. are used. 1×10
Annealing may be performed in a high vacuum atmosphere of −6 to 1×10 −10 Torr. Solid phase growth annealing temperature is 500℃
~700°C. In such low-temperature annealing, only crystal grains having crystal orientations with low activation energy for crystal growth grow selectively, and moreover, they grow slowly and to a large size. In the inventor's experiments, the annealing temperature was 600°C.
A silicon thin film with a large grain size of 2 μm or more was obtained by solid-phase growth for 16 hours.

Instead of the solid phase growth method, LPCVD method, plasma CVD method, sputtering method, vapor deposition method, MBE (Mole
The non-single-crystal silicon thin film may be formed by a curar beam epitaxy method, a laser annealing method, or the like.

Next, the solid-phase grown silicon thin film is patterned into an island shape as shown in FIG. 1(b) 1-3 by photolithography.

Next, as shown in FIG. 1(c), a gate oxide film 1-4 is formed. The gate oxide film can be formed by LPCVD, photo-excited CVD, plasma CVD, ECR plasma CVD, high vacuum evaporation, plasma oxidation, or high pressure oxidation at 500°C. There are the following low temperature methods. The gate oxide film formed by the low-temperature method becomes an excellent film that is denser and has fewer interface states by heat treatment. When using a quartz substrate as the amorphous insulating substrate 1-1, a thermal oxidation method can be used. The thermal oxidation method includes d
There are ry oxidation method and wet oxidation method, but the oxidation temperature is 10
The dry oxidation method is more suitable because the film quality is excellent, although the temperature is higher than 00°C.

After forming the oxide film, boron ions may be implanted into the channel. This is because the threshold voltage of the Nch thin film transistor shifts to the negative side and P
The purpose of this is to prevent the threshold voltage of the channel thin film transistor from shifting to the positive side. The deposited thickness of the amorphous silicon film 1-2 is 500 to 1500.
In the case of approximately Å, the boron dose is 1×1012~5
Approximately 1012 cm-2 is suitable. When the thickness of the amorphous silicon film is as thin as 500 Å or less, boron
As a guideline, reduce the amount of noise to 1 x 1012 cm-2 or less. In addition, if the film thickness is 1500 Å or more, increase the amount of boron, and as a guide, 5 x 1012 cm-2
Do more than that.

Next, a resist mask 1-6 is formed, and the gate oxide film in the portion where the source and drain regions are to be formed is peeled off to form an island-shaped gate oxide film as shown in FIG. 1(d). Membrane 1-5
form.

Next, as shown in FIG. 1E, a source region 1-7 and a drain region 1-8 are formed by ion implantation of an impurity element. The ion dose Nh of the source and drain regions is 1×1019 to 1×10
Approximately 21cm-3 is suitable.

The source region 1-7 and drain region 1-8 can be formed not only by ion implantation but also by other methods. For example, a plasma doping method can be used. Parallel plate plasma CVD
Using a device, phosphorus or boron is deposited on the substrate by glow discharge decomposition of phosphine gas or diborane gas, and the source and drain regions are formed by selectively adding impurities to the silicon thin film 1-3. It is something that forms. Other effective methods include ion shower doping and laser doping.

Subsequently, the resist mask 1-6 is peeled off as shown in FIG. 1(f).

Impurity-doped silicon thin film 1-1 constituting gate electrode material and source and drain contact regions
0 is deposited. In the case of an Nch thin film transistor, a donor type impurity such as phosphorus is added, and in the case of a Pch thin film transistor, an acceptor type impurity is added. After forming a doped amorphous silicon thin film using a plasma CVD method using a mixed gas of phosphine gas (PH3) and silane gas (SiH4) or a mixed gas of diborane gas (B2H6) and silane gas, a solid phase How to grow or LPC
A method of forming a doped amorphous silicon or polycrystalline silicon thin film by VD method and annealing as necessary;
Alternatively, there is a method in which an undoped silicon thin film is formed and then impurities are added by diffusion such as pre-deposition. Impurity concentration is 1 x 1019 cm-3 or more, preferably 1 x 1020
cm-3 or more is desirable.

Subsequently, a gate electrode and source and drain regions are simultaneously formed by the next photo process. Figure 1
In (h), 1-11 is a gate electrode, 1-12 is a source contact region, and 1-13 is a drain contact region. The distance between the gate electrode 1-11 and the source contact region and the distance between the gate electrode and the drain contact region are important parameters that determine the length of the offset region of the LDD structure thin film transistor. be. The value is preferably 1 μm or less.

Next, the gate electrode 1-11 and the source
Using the drain contact region 1-12 and the drain contact region 1-13 as a mask, the exposed portion of the gate oxide film is removed by etching to expose a part of the non-single crystal semiconductor thin film as shown in FIG. 1(i). . Hydrofluoric acid (HF) is used for etching.
) is commonly used.

Next, a low concentration impurity element is added to form an offset region 1-14 as shown in FIG. 1(j). Gate electrode 1-11 and source contact region 1-1
Offset regions 1-14 are formed in a self-aligned manner using 2 and drain contact regions 1-13 as masks. Similarly to the source and drain regions, a donor type impurity is added in the case of an Nch thin film transistor, and an acceptor type impurity is added in the case of a Pch thin film transistor. The impurity concentration of the offset region is made lower than the impurity concentration of the source and drain regions. When using the ion implantation method, the ion implantation dose is 1 x 1012 to 1 x 101.
It should be about 4 cm-2. Impurity concentration is 1×1017~
It becomes about 1×1019 cm−3. In addition to the ion implantation method, as mentioned earlier, the method of adding impurities is laser.
There are methods such as a laser doping method or a plasma doping method. Since the surface of the silicon thin film is exposed, the addition efficiency is excellent.

After forming the offset region, FIG. 1(k)
As shown in FIG. 1, interlayer insulating films 1-15 are stacked. As the interlayer insulating film material, an oxide film, a nitride film, or the like is used. As long as the insulation is good, the film thickness can be any thickness.
The thickness is usually from several thousand Å to several μm. Methods for forming the oxide film include LPCVD, APCVD, and plasma CVD.
There are methods such as a method, an ECR plasma CVD method, and a sputtering method. A simple method for forming the nitride film is the LPCVD method or the plasma CVD method. For the reaction, a mixed gas of ammonia gas (NH3), silane gas, and nitrogen gas, or a mixed gas of silane gas and nitrogen gas, etc. is used.

Subsequently, activation annealing is performed for the purpose of densifying the interlayer insulating film 1-15, activating the source, drain and offset regions, and restoring crystallinity. Examples of the annealing method include a one-step activation annealing method and a two-step activation annealing method. The two-step activation annealing method will be explained. First, it is heated at a temperature of about 600 to 800°C for about 1 to 20 hours in a N2 gas atmosphere.
Stepwise annealing is performed to restore the crystallinity of the ion-implanted offset region. Annealing is performed for 10 to 20 hours at a low temperature of about 600°C. Further, at a relatively high temperature of 800° C., short-time annealing of 1 to 10 hours is performed. After performing such one-step annealing, 1000
A two-step annealing is performed for less than one hour at a temperature of .degree. C. or higher to activate impurity ions. The two-step activation annealing described above restores and activates the crystallinity of the source and drain regions. The annealing atmosphere may be not only nitrogen but also hydrogen gas, argon gas, helium gas, or vacuum.

[0032] Next, hydrogenation treatment may be performed. When hydrogen ions are introduced by a hydrogen plasma method, a hydrogen ion implantation method, or a hydrogen diffusion method from a plasma nitride film, dangling bonds existing at grain boundaries and gate oxide film interfaces are introduced. Defects present at the junction between the source and drain portions and the channel portion are inactivated. Such a hydrogenation step is performed on the interlayer insulating film 1-1.
This may be done before laminating the layer 5. Alternatively, the hydrogenation step may be performed after forming a source electrode and a drain electrode, which will be described later.

Next, as shown in FIG. 1(l), contact holes are formed in the interlayer insulating film 1-15, contact electrodes are formed, and source electrodes 1-16 and drain electrodes 1-17 are formed. shall be. The source electrode and drain electrode are formed of a metal material such as aluminum or chromium. In this way, a thin film transistor is formed.

(Example 2) When it is necessary to flatten the surface shape of the interlayer insulating film, BPSG (b
orophosphosilicate glass
) A very flat interlayer insulating film can be obtained by forming a film and subjecting it to low-temperature reflow. The BPSG film can be produced using methods such as APCVD, LPCVD, plasma CVD, and spin-on glass. Reflow can be performed even at a low temperature of about 750°C. A thin film transistor manufactured using reflow technology will be described with reference to FIG. Insulating amorphous material 2-1, silicon thin film 2-2, gate oxide film 2-3, source region 2-4, drain region 2-5,
After forming the gate electrode 2-6, offset region 2-7, source contact region 2-8, and drain contact region 2-9, a BPSG film 2-10 is formed by the method described above. Thereafter, the BPSG film is reflowed by heat treatment at about 750 to 900°C, and is
Form a flat interlayer insulating film as shown in .

[0035]

As explained above, since the LDD structure can be realized in a self-aligned manner through simple steps, an extremely large effect on reducing off-state current is expected. Furthermore, it is possible to suppress the jump of the OFF leakage current peculiar to the OFF region of the thin film transistor. Since the LDD structure can be realized through a simple process, the drain breakdown voltage can be reduced to 100V.
It becomes possible to increase the voltage resistance to a certain extent. Further, the drain breakdown voltage value and the off-state current value can also be controlled by the ion implantation dose in the offset region.

Excellent LD without increasing the number of photo steps
It becomes possible to create a D structure.

Contact resistance was reduced because source and drain contact regions were provided between the source and drain regions and the source and drain electrodes, respectively. Therefore, it has become possible to obtain a sufficiently large on-current. In other words, the problem that the on-state current of the conventional thin film transistor having an LDD structure decreases has been solved.

Conventionally, in order to form an offset region,
Side walls had to be formed on the gate electrode. However, in order to form this sidewall, it was necessary to accurately control the thickness of the insulating film and the anisotropy of etching. According to the invention there is no need to form side walls. In other words, L does not require the use of anisotropic etching technology that is difficult to control.
It becomes possible to create a thin film transistor with a DD structure. Therefore, there is a great effect on simplification of the process and improvement of yield.

Since the gate oxide film is etched away in a self-aligned manner to expose the surface of the silicon thin film, impurities can be efficiently added not only by ion implantation but also by other simple methods. Therefore, it is possible to form the offset region in a self-aligned manner without using ion implantation. As a result, an LD with excellent uniformity characteristics
It becomes possible to create a D-structure TFT.

Furthermore, since the source region and drain region are formed in a self-aligned manner, it is effective for shortening the channel, and there is little variation in characteristics. The thickness of the channel region is 1
Since the film thickness of the source and drain regions forming the contact can be as thick as 1000 Å or more, the contact resistance is reduced. As a result, the rise of the subthreshold region of the thin film transistor becomes very steep, and a large on-current that is not limited by contact resistance can be obtained.

Since a flat interlayer insulating film can be obtained by applying the reflow technique, the occurrence of disconnections in the wiring formed thereon is extremely reduced, further improving the yield. Therefore, the effects of the present invention can be maximized. Since it is possible to fabricate thin film transistors with excellent characteristics on an amorphous insulating substrate, sufficiently high-speed operation can be achieved even when applied to an active matrix substrate in which driver circuits are integrated on the same substrate. Furthermore, it has great effects on reducing power supply voltage, reducing current consumption, and improving reliability. Further, since it is possible to manufacture the device by a low-temperature process at 600° C. or lower, it is highly effective in reducing the cost and increasing the area of the active matrix substrate.

When the present invention is applied to a contact image sensor in which a photoelectric conversion element and its scanning circuit are integrated on the same chip, it is possible to increase the reading speed, increase the resolution, and further increase the gradation. produces a very large effect. Once high resolution is achieved, close-contact images for color reading will become available.
Application to digital sensors is also facilitated. Of course, this has great effects in reducing power supply voltage, reducing current consumption, and improving reliability. Furthermore, since it can be manufactured by a low-temperature process, it is possible to make the contact type image sensor chip long, and a reading device for a large facsimile such as A4 or A3 size can be realized with a single chip. Therefore, the complicated and unreliable technique of splicing two sensor chips can be avoided, and the mounting yield can also be improved.

[0043] Not only quartz substrates and glass substrates, but also sapphire substrates (Al2O3) or MgO/Al2O3
, BP, CaF2, or the like can also be used.

Although the explanation has been given above using thin film transistors as an example, devices using thin films such as bipolar transistors and heterojunction bipolar transistors can also be explained.
The present invention can be applied. Further, the present invention can also be applied to elements using SOI technology, such as three-dimensional devices.

[Brief explanation of the drawing]

FIGS. 1A to 1L are process diagrams showing a method for manufacturing a thin film semiconductor device according to the present invention.

FIGS. 2(a) to 2(b) are process diagrams showing a method for manufacturing a thin film semiconductor device according to the present invention when reflow technology is applied.

FIGS. 3(a) to 3(f) are process diagrams showing a method of manufacturing a conventional LDD structure thin film transistor.

[Explanation of symbols]

1-7 Source contact area 1-8
Drain contact region 1-11 Gate electrode 1-12 Source region 1-13 Drain region 1-14 Offset region 1-16 Interlayer insulating film 2-10 BPSG film

Claims (3)

[Claims] Claim 1: In a thin film semiconductor device formed on an insulating amorphous material, [a] A non-single crystal semiconductor thin film is formed on the insulating amorphous material and patterned into an island shape. Step [b] Forming a gate insulating film on the non-single crystal semiconductor thin film patterned into an island shape, forming a resist mask, and patterning the gate insulating film. a step of exposing at least a part of the surface of the non-single crystal semiconductor thin film; [c] a step of performing high-concentration ion implantation using the resist mask and gate oxide film as a mask to form a contact region; [d] After peeling off the resist mask, a low resistance impurity-doped semiconductor thin film is formed, and the impurity-doped semiconductor thin film is patterned to form a gate electrode on the gate insulating film and the exposed area. Saw on non-single crystal semiconductor thin film
forming the gate electrode and the source and drain regions; [e] removing the exposed portion of the gate oxide film using the gate electrode and the source and drain regions as masks; [f] forming the gate electrode and the drain region; A method for manufacturing a thin film semiconductor device, comprising at least the step of adding an impurity element to an exposed portion of the non-single crystal semiconductor thin film using the source and drain regions as a mask to form an offset region. 2. The method of manufacturing a thin film semiconductor device according to claim 1, wherein the gate electrode, source and drain regions are each separated and insulated. 3. The impurity concentration of the offset region is:
2. The method of manufacturing a thin film semiconductor device according to claim 1, wherein the impurity concentration is lower than that of the contact region and the source and drain regions.