JPH0613407A - Thin film semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce off-leakage currents by forming a main gate electrode onto a gate insulating film and forming a sub-gate electrode electrically conducted with the main gate electrode while holding a second insulating film having a contact hole onto the main gate electrode. CONSTITUTION:A main gate electrode 1-1 is formed onto a gate insulating film 1-3. A second insulating film 1-4 is film-formed onto the main gate electrode 1-1. A gate contact hole is shaped to the second insulating film 1-4, and the main gate electrode 1-1 is exposed. A sub-gate electrode 1-2 completely overlapping the main gate electrode 1-1 is formed. The sub-gate electrode 1-2 is masked, and ions are implanted, thus shaping a source region 1-5, a drain region 1-6 and an offset region to the sub-gate electrode 1-2 in a self-alignment manner. Accordingly, the jumping-up of off leakage currents is inhibited, and a three- terminal thin-film transistor having excellent on-currents can be realized.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a planar type thin film semiconductor device formed on an insulating amorphous material such as a quartz substrate or a glass substrate, which has a large on-current.
The present invention relates to a structure of a thin film semiconductor device having extremely small off-leakage current and a manufacturing method thereof.

[0002]

2. Description of the Related Art In order to increase the on-current and mobility of a thin film transistor, it is necessary to form a semiconductor thin film having excellent crystallinity on an insulating substrate, and a solid phase growth method or a laser annealing method is used. Known {SOI structure formation technology, industrial books}.

Further, the leak current in the off region of a normal thin film transistor strongly depends on the electric field strength in the vicinity of the drain region, and when the gate voltage is increased to the off side, the off leak current greatly increases. In order to reduce the off-leakage current, LDD (Lightly d
It is known that it is effective to form an open drain structure or an offset gate structure.

In the conventional LDD structure or offset gate structure, complicated steps such as providing a gate electrode side wall by utilizing anisotropic etching are required. Further, since the offset region of the channel portion has high resistance, there is a problem that the on-current is reduced.

In order to suppress a decrease in on-current due to the offset gate structure, in addition to the first gate electrode, an electrically insulated second gate electrode is provided and an offset region is provided independently of the first gate electrode. There is a method of controlling the conduction state of. {Extended Abstracts
of the 22nd Conferenceon
Solid State Devices and
Materials, Sendai, 1990, pp.
1011-1014}. This is shown in FIG. 1
6-1 is a source region, 16-2 is a drain region, 16-
3 is a polycrystalline silicon film, 16-4 is a gate insulating film, 16-5 is a first gate electrode, 16-6 is a second gate electrode, and 16-7 is an offset region. However, since there are two gate electrodes, this results in a four-terminal thin film transistor.

[0006]

According to the conventional method as described above, the difficult step of forming the side wall of the gate electrode is required. Further, there is a problem that the on-current decreases due to the existence of the offset region. Further, there is a method of providing the second gate electrode in order to suppress the reduction of the on-current, but this has a problem that it becomes a four-terminal thin film transistor.

The present invention solves the problems as described above, and the offset gate structure or the LDD is manufactured by a simple process.
An object of the present invention is to realize an excellent three-terminal thin film transistor having a very low off-leakage current, suppressing a jump of the off-leakage current in the off-region, and having a large on-current by incorporating the structure.

[0008]

The present invention provides a source region,
In a planar thin film semiconductor device having a drain region, a gate insulating film and a gate electrode, a second insulating film having a main gate electrode on the gate insulating film and a contact hole on the main gate electrode is sandwiched. And a sub-gate electrode electrically connected to the main gate electrode, and a source region and a drain region are formed in a self-aligned manner by using the sub-gate electrode as a mask.

Furthermore, if the sub-gate electrode length is L _s and the main gate electrode length is L _m , then at least L _s > L
It is characterized by satisfying the condition of _m .

Further, the sub-gate electrode is characterized by completely overlapping the main gate electrode.

Further, in the method of manufacturing the thin film semiconductor device, the step of: (a) forming a first semiconductor layer on the insulating amorphous material and forming a gate insulating film on the semiconductor layer;
(B) a step of forming a main gate electrode on the gate insulating film, (c) a step of forming a second insulating film on the main gate electrode, (d) a gate contact to the second insulating film Forming a hole to expose a part of the main gate electrode, (e) forming a sub-gate electrode that completely overlaps the main gate electrode, (f) phosphorus using the sub-gate electrode as a mask, A step of forming a source region, a drain region and an offset region in a self-aligned manner with respect to the sub-gate electrode by ion-implanting an impurity such as arsenic or boron, (g) a step of laminating an interlayer insulating film,
(H) In order to form a contact with the first semiconductor layer, at least a step of forming a contact hole in the interlayer insulating film and forming an electrode by a photo step is included.

As a second invention, the present invention provides a source region,
A planar type thin film semiconductor device having a drain region, a gate insulating film and a gate electrode, wherein a tapered main gate electrode is provided on the gate insulating film, the main gate electrode is oxidized, and a second main electrode is provided on the main gate electrode. An insulating film is formed, a contact hole is formed in the second insulating film to have a sub-gate electrode electrically connected to the main gate electrode, and the sub-gate electrode is used as a mask to self-align with the source region and It is characterized in that a drain region is formed.

Further, _assuming that the sub-gate electrode length is L _s and the main gate electrode length is L _m , at least L _s > L
It is characterized by satisfying the condition of _m .

Furthermore, the sub-gate electrode completely overlaps the main gate electrode.

In the method of manufacturing the thin film semiconductor device,
(A) a step of forming a first semiconductor layer on an insulating amorphous material and forming a gate insulating film on the semiconductor layer;
(B) forming a tapered main gate electrode on the gate insulating film by taper etching,
(C) The main gate electrode is directly oxidized to form a second
Forming an insulating film, the step of: (d) forming a gate contact hole in the second insulating film to expose a part of the main gate electrode, and (e) completely overlapping the main gate electrode. And (f) by ion-implanting an impurity such as phosphorus, arsenic, or boron with the sub-gate electrode as a mask, the source region and the drain region are self-aligned with the sub-gate electrode. And a step of forming an offset region, (g) a step of laminating an interlayer insulating film, (h) a contact hole is formed in the interlayer insulating film by a photo step in order to form a contact with the first semiconductor layer. However, the method has at least a step of forming an electrode.

A third aspect of the present invention is a source region,
A planar thin-film semiconductor device having a drain region, a gate insulating film, and a gate electrode has a main gate electrode on the gate insulating film, and the main gate electrode is used as a mask to ion-implant a low-concentration impurity and LDD (L
a lightly doped drain region is formed, and a sub-gate electrode electrically connected to the main gate electrode is sandwiched between the main gate electrode and a second insulating film having a contact hole. A thin film semiconductor device, wherein a source region and a drain region are formed in a self-aligned manner by ion-implanting a high concentration of impurities as a mask.

Further, when the sub-gate electrode length is L _s and the main gate electrode length is L _m , at least L _s > L
It is characterized by satisfying the condition of _m .

Furthermore, the sub-gate electrode completely overlaps the main gate electrode.

Further, in the method of manufacturing a thin film semiconductor device, the step of: (a) forming a first semiconductor layer on an insulating amorphous material and forming a gate insulating film on the semiconductor layer;
(B) forming a main gate electrode on the gate insulating film, (c) forming a second insulating film on the main gate electrode, (d) using the main gate electrode as a mask, 1 × 10 ¹⁹ cm ^-3 or lower concentrations of phosphorus, by the impurity of arsenic or boron, or the like is ion-implanted to form a LDD region, a gate contact hole (e) of the second insulating film, Exposing part of the main gate electrode, (f) forming a sub-gate electrode that completely overlaps the main gate electrode, (g) 1 × 10 ¹⁹ cm ^{−3 with the} sub-gate electrode as a mask By ion-implanting the above high-concentration impurities such as phosphorus, arsenic, or boron, in a self-aligned manner with respect to the sub-gate electrode,
A step of forming a source region, a drain region and an offset region, (h) a step of laminating an interlayer insulating film, (i)
In order to form a contact with the first semiconductor layer, at least a step of forming a contact hole in the interlayer insulating film and forming an electrode by a photo process is included.

Finally, in a planar type thin film semiconductor device having a source region, a drain region, a gate insulating film and a gate electrode, a tapered main gate electrode is provided on the gate insulating film, and the main gate electrode is used as a mask. LDD (Lig
an area of the Htly Doped Drain) is formed,
The main gate electrode is oxidized to form a second insulating film on the main gate electrode, and a contact hole is formed in the second insulating film to form a sub-gate electrode electrically connected to the main gate electrode. A source region and a drain region are formed in a self-aligned manner by ion-implanting a high-concentration impurity with the sub-gate electrode as a mask.

Further, if the sub-gate electrode length is L _s and the main gate electrode length is L _m , at least L _s > L
It is characterized by satisfying the condition of _m .

Furthermore, the sub-gate electrode completely overlaps the main gate electrode.

Further, in the method of manufacturing a thin film semiconductor device, the step of: (a) forming a first semiconductor layer on an insulating amorphous material and forming a gate insulating film on the semiconductor layer;
(B) forming a tapered main gate electrode on the gate insulating film by taper etching,
(C) 1 × 1 using the main gate electrode as a mask
A step of forming an LDD region by ion-implanting a low-concentration impurity such as phosphorus, arsenic, or boron of 0 ¹⁹ cm ⁻³ or less, (d) directly oxidizing the main gate electrode to form a second insulating film (E) forming a gate contact hole in the second insulating film to expose a part of the main gate electrode, and (f) completely overlapping the main gate electrode. A step of forming a sub-gate electrode, (g) self-implanting the sub-gate electrode by ion-implanting a high-concentration impurity such as phosphorus, arsenic, or boron of 1 × 10 ¹⁹ cm ⁻³ or more with the sub-gate electrode as a mask. Consistently,
A step of forming a source region, a drain region and an offset region, (h) a step of laminating an interlayer insulating film, (i)
In order to form a contact with the first semiconductor layer, at least a step of forming a contact hole in the interlayer insulating film and forming an electrode by a photo process is included.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The cross-sectional structure of the thin film transistor of the present invention is shown in FIG.
Shown in. 4 shows four structures proposed by the present invention. Since the details will be described along with the manufacturing method, a brief description will be given first. 1A and 1B show an offset gate structure, FIG.
(C) and (d) show the LDD structure. 1-1 is a main gate electrode, 1-2 is a sub-gate electrode, 1-3 is a gate insulating film, 1-4 is a second insulating film, 1-5 is a source region, 1-6 is a drain region, 1-7. Indicates a tapered main gate electrode, and 1-8 indicates an LDD region. Hereinafter, the manufacturing methods of FIGS. 1A to 1D will be described as Examples 1 to 4, respectively.

Example 1 A thin film transistor having an offset gate structure of the present invention shown in FIG. 1A will be described along with a manufacturing process.

A non-single crystal semiconductor thin film is formed on the insulating amorphous material. As the insulating amorphous material, a quartz substrate, a glass substrate, a nitride film, a SiO ₂ film or the like is used. When using a quartz substrate, the process temperature is 1200
It is allowed up to about ℃, but when using a glass substrate,
Limited to low temperature processes below 600 ° C. Below,
An example will be described in which a quartz substrate is used and a solid phase growth Si thin film is used as the non-single crystal semiconductor thin film. Of course, not only the solid-phase-grown Si thin film, but also a polycrystalline Si thin film or SOI (Silicon on Ins) formed by a low pressure CVD method, a plasma CVD method, a sputtering method, or the like.
The present invention can be realized by using an ululator).

Using a plasma CVD apparatus, a mixed gas of SiH ₄ and H ₂ is decomposed by a high frequency glow discharge of 13.56 MHz on a quartz substrate 2-1 as shown in FIG. The Si film 2-2 is deposited. The SiH ₄ partial pressure of the mixed gas is 10 to 20%, and the internal pressure in the depot is 0.5.
It is about 1.5 torr. The substrate temperature is preferably 250 ° C. or lower, about 180 ° C. When the amount of bound hydrogen was determined by infrared absorption measurement, it was about 8 atomic%. The chamber before the deposition of the amorphous Si film 2-2 was subjected to Freon cleaning, and the amorphous Si film deposited subsequently was 2 × 10.
Contains ¹⁸ cm ^-3 of fluorine. Therefore, in the present invention, after the Freon cleaning, the dummy is deposited,
Perform the actual deposition. Or abolish Freon cleaning,
Clean the chamber by another method such as bead treatment.

Then, the amorphous Si film is formed at 400 ° C. to 5 ° C.
Heat treatment is performed at 00 ° C. to release hydrogen. This process is intended to prevent the explosive desorption of hydrogen.

Next, the amorphous thin film 2-2 is solid-phase grown. As a solid phase growth method, furnace annealing with a quartz tube is convenient. Nitrogen gas, hydrogen gas, argon gas, helium gas or the like is used as the annealing atmosphere. 1 x 1
The annealing may be performed in a high vacuum atmosphere of 0 ⁻⁶ to 1 × 10 ⁻¹⁰ Torr. Solid phase growth annealing temperature is 500 ° C ~
The temperature is 700 ° C. In such low temperature annealing, selectively,
Only crystal grains having a crystal orientation with a small activation energy for crystal growth grow, and slowly grow large.
In an experiment by the inventor, a large grain size silicon thin film of 2 μm or more was obtained by solid phase growth at an annealing temperature of 600 ° C. and an annealing time of 16 hours. In FIG. 2B, 2-3 indicates a solid phase growth silicon thin film.

The method for producing a silicon thin film by the solid phase growth method has been described above.
The silicon thin film may be formed by a method such as a sputtering method or a vapor deposition method.

Next, the solid phase growth silicon thin film is patterned into an island shape by a photolithography method as shown in FIG.

Next, as shown in FIG. 2D, a gate oxide film 2-4 is formed. As the method for forming the gate oxide film, LPCVD method, photo-excited CVD method, plasma CVD method, ECR plasma CVD method, high vacuum vapor deposition method, plasma oxidation method, high pressure oxidation method, etc. There is a low temperature method. The gate oxide film formed by the low temperature method is heat-treated to be a denser and excellent film having less interface states. When a quartz substrate is used as the amorphous insulating substrate 2-1, a thermal oxidation method can be used. D for the thermal oxidation method
There are a ry oxidation method and a wet oxidation method. An oxide film is formed at about 800 ° C. or higher. To use a quartz substrate, for example, 1
It is suitable to carry out dry oxidation at a temperature as high as possible of 000 ° C. or higher. Gate oxide film thickness is from 500Å to 1
About 500Å is suitable.

After forming the gate oxide film, boron may be channel-implanted and channel-doped if necessary.
This is intended to prevent the threshold voltage of the Nch thin film transistor from shifting to the negative side. The amorphous silicon film has a deposition thickness of 500 to 1
In case of about 500Å, the dose of boron is 1 × 10 ^12.
About 5 × 10 ¹² cm ^-2 is suitable. When the thickness of the amorphous silicon film is as thin as 500 Å or less, the boron dose amount is reduced, and as a guideline, it is set to 1 × 10 ¹² cm ^-2 or less. When the film thickness is 1500 Å or more, the boron dose is increased, and as a guide, it is 5 × 10 ¹² cm.
^-Set to ² or more.

Instead of channel ion implantation, boron may be added at the time of depositing the silicon film 2-2. This can be obtained by flowing diborane gas (B ₂ H ₆ ) together with silane gas into the chamber during the deposition of the silicon film to cause a reaction.

Next, as shown in FIG. 2E, a main gate electrode 2-5 is formed. The main gate electrode material is a polycrystalline silicon thin film, a silicide film such as molybdenum silicide, tungsten silicide or titanium silicide, a metal film such as aluminum or chromium, or a transparency such as ITO or SnO ₂ . A conductive film or the like can be used. As a film forming method, a CVD method, a sputtering method, a vacuum deposition method,
Although there is a method such as a plasma CVD method, detailed description thereof is omitted here.

Next, as shown in FIG. 3 (a), the second
The insulating film 2-6 is formed. An oxide film, a nitride film, or the like is used as the second insulating film material. LPCVD or plasma CVD is a simple method for forming the nitride film. Ammonia gas (N
A mixed gas of H ₃ ), silane gas and nitrogen gas, a mixed gas of silane gas and nitrogen gas, or the like is used. If the film thickness is too thick, the on-current decreases significantly, and conversely if it is too thin, the effect of reducing the off-leakage current disappears. Therefore, it is necessary to find an optimum value for the film thickness of the second insulating film from the relationship between the on-current and the off-leakage current.
Å to 3000 Å is suitable.

Subsequently, as shown in FIG. 3B, a gate contact hole 2-7 is formed in the second insulating film 2-6 by photolithography to expose a part of the main gate electrode.

Subsequently, as shown in FIG. 3C, a sub-gate electrode 2-8 is formed. The material of the sub-gate electrode is basically the same as the material of the main gate electrode, and a description thereof will be omitted. The sub-gate electrode 2-8 completely overlaps the main gate electrode 2-5. The distance L from the end of the main gate electrode pattern to the end of the sub gate electrode pattern represents an offset region, and is indicated by 2-9 in the figure. The offset length L has to be optimized depending on the value of the lateral diffusion length Y _j of the ion-implanted impurities, but about 1.5 μm to 4 μm is suitable for a thin film transistor. In the figure, L is shown to be equal on both sides of the gate electrode, but this does not necessarily have to be equal.

Next, as shown in FIG. 3D, an acceptor type or donor type impurity is ion-implanted into the first semiconductor layer by an ion implantation method to form a source region and a drain region in a self-aligned manner. To do. In FIG. 2D, 2-10 is a source region in which high concentration ion implantation is performed,
Reference numerals 2-11 denote drain regions.

Boron (B) or the like is used as the acceptor type impurity. As the donor type impurity, phosphorus (P), arsenic (As) or the like is used. As an impurity addition method, there are methods such as a laser doping method and a plasma doping method other than the ion implantation method. The arrow indicated by 2-11 represents the ion beam of impurities. When a quartz substrate is used as the insulating amorphous material 2-1, a thermal diffusion method can be used. The impurity dose amount is about 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ^-2 . Converted to the impurity concentration, in the source 2-10 and the drain region 2-11, about 1 × 10 ¹⁹ to 1 × 10 ²²
It is about cm ^-3 .

Next, as shown in FIG. 4A, an interlayer insulating film 2-13 is laminated. An oxide film, a nitride film, or the like is used as the material for the interlayer insulating film. The insulating layer may have any thickness as long as it has a good insulating property, but it is usually several thousand Å to several μm. LPCVD or plasma CVD is a simple method for forming the nitride film. For the reaction, a mixed gas of ammonia gas (NH ₃ ) and silane gas and nitrogen gas, a mixed gas of silane gas and nitrogen gas, or the like is used. Then, activation annealing is performed for the purpose of densification of the interlayer insulating film, activation of the source region and drain region, and recovery of crystallinity. As the conditions of activation annealing, the temperature is lowered to about 800 to 1000 ° C. in an N ₂ gas atmosphere, and the annealing time is set to about 20 minutes to 1 hour. At 900 to 1000 ° C., the impurities are considerably activated by annealing for about 20 minutes. 20 at 800-900 ° C
Anneal for 1 hour to 1 minute. On the other hand, first 500
A two-step activation annealing method in which the crystallinity is sufficiently recovered by annealing at ˜800 ° C. for about 1 to 20 hours and then activation is performed at a high temperature of 900 to 1000 ° C. is also effective. In addition, RT using infrared lamp or halogen lamp
A (Rapid Thermal Annealin
The g) method is also effective. Furthermore, it is also effective to use a laser activation method using a laser beam or the like.

Next, when hydrogen ions are introduced by a method such as a hydrogen plasma method, a hydrogen ion implantation method, or a hydrogen diffusion method from a plasma nitride film, dangling bonds existing at crystal grain boundaries or a gate oxide film. Defects existing at the interface and the like, and defects existing at the junction between the source / drain portion and the channel portion are inactivated. Such a hydrogenation step may be performed before stacking the interlayer insulating films 2-13. Alternatively, the hydrogenation step may be performed after forming a source electrode and a drain electrode, which will be described later.

Next, as shown in FIG. 4B, a contact hole is formed in the interlayer insulating film 2-13 by photoetching. Then, as shown in FIG.
And a drain electrode 2-15 are formed. The source electrode and the drain electrode are formed of a metal material such as aluminum or chromium. In this way, a thin film transistor is formed.

(Embodiment 2) The second invention shown in FIG. 1 (b) will be described. The steps from the formation of the silicon thin film to the formation of the gate oxide film are shown in FIGS. 5 (a) to 5 (d). Since these steps are the same as those described in the section of the first embodiment, detailed description thereof is omitted here. An example will be described in which a quartz substrate is used and a solid phase growth Si thin film is used as the non-single crystal semiconductor thin film.
Of course, not only solid phase growth Si thin film but also low pressure CVD
Method, plasma CVD method, sputtering method, or other polycrystalline Si thin film or SOI (Silicon on I)
The present invention can also be realized by using a nsulator.

Next, the gate electrode forming step will be described. The tapered gate electrode is manufactured by mixing oxygen gas (O ₂ ) as an etching gas and performing plasma etching. Normally, Freon gas (C
The polycrystalline silicon, the silicide film, the polycide film, or the like is plasma-etched with F ₄ ). At this time, when O ₂ gas is mixed, the gate electrode is processed while the resist serving as the mask is also removed by etching. Therefore, the tapered gate electrode 5-5 as shown in FIG. 5E is formed. When the gas partial pressure of O ₂ gas is increased, the taper shape becomes gentler. In this way, the taper shape can be controlled by the voltage division ratio.

Next, as shown in FIG. 6A, a second insulating film 5-6 is formed by directly oxidizing the main gate electrode. The method for forming the second insulating film was briefly described in the description of the method for forming the gate oxide film. A method such as a thermal oxidation method, a plasma oxidation method or a high pressure oxidation method can be considered. The thermal oxidation method has been described above and will not be described. The plasma oxidation method directly oxidizes a silicon film in oxygen plasma, and has a feature that an oxide film can be formed even at a low temperature of 600 ° C. or lower. The high-pressure oxidation method directly oxidizes silicon in a high-pressure oxygen atmosphere. An oxide film can be formed at a low temperature of 600 ° C. in a high pressure oxygen atmosphere of about 10,000 Torr to 370000 Torr. Since the gate oxide film is formed, it is desirable to form the second insulating film at a temperature as low as possible. The film thickness is
If it is too thick, the on-current will be significantly reduced, and if it is too thin, the off-leakage current reduction effect will be lost. Therefore,
An optimum value for the film thickness of the second insulating film needs to be obtained from the relationship between the on-current and the off-leakage current, but about 500Å to 3000Å is suitable.

Subsequently, as shown in FIG. 6B, a gate contact hole 5-7 is formed in the second insulating film 5-6 by photolithography to expose a part of the main gate electrode.

Subsequently, as shown in FIG. 6C, a sub-gate electrode 5-8 is formed. The material of the sub-gate electrode is basically the same as the material of the main gate electrode, and a description thereof will be omitted. The sub-gate electrode 5-8 completely overlaps the main gate electrode 5-5. A distance L from the end of the main gate electrode pattern to the end of the sub gate electrode pattern represents an offset region, which is indicated by 5-9 in the figure. The offset length L has to be optimized depending on the value of the lateral diffusion length Y _j of the ion-implanted impurities, but about 1.5 μm to 4 μm is suitable for a thin film transistor. In the figure, L is shown to be equal on both sides of the gate electrode, but this does not necessarily have to be equal.

Next, as shown in FIG. 6D, an acceptor type or donor type impurity is ion-implanted into the first semiconductor layer by an ion implantation method to form a source region and a drain region in a self-aligned manner. To do. In FIG. 6D, 5-10 is a source region in which high concentration ion implantation is performed,
Reference numerals 5-11 denote drain regions.

Boron (B) or the like is used as the acceptor type impurity. As the donor type impurity, phosphorus (P), arsenic (As) or the like is used. As an impurity addition method, there are methods such as a laser doping method and a plasma doping method other than the ion implantation method. The arrow indicated by 5-12 represents the ion beam of impurities. When a quartz substrate is used as the insulating amorphous material 5-1, a thermal diffusion method can be used. The impurity dose amount is about 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ^-2 . Converted to the impurity concentration, the source 5-10 and the drain region 5-11 have about 1 × 10 ¹⁹ to 1 × 10 ^22.
It is about cm ^-3 .

Next, as shown in FIG. 7A, an interlayer insulating film 5-13 is laminated. An oxide film, a nitride film, or the like is used as the material for the interlayer insulating film. The insulating layer may have any thickness as long as it has a good insulating property, but it is usually several thousand Å to several μm. LPCVD or plasma CVD is a simple method for forming the nitride film. For the reaction, a mixed gas of ammonia gas (NH ₃ ) and silane gas and nitrogen gas, a mixed gas of silane gas and nitrogen gas, or the like is used. Then, activation annealing is performed for the purpose of densification of the interlayer insulating film, activation of the source region and drain region, and recovery of crystallinity. As the conditions of activation annealing, the temperature is lowered to about 800 to 1000 ° C. in an N ₂ gas atmosphere, and the annealing time is set to about 20 minutes to 1 hour. At 900 to 1000 ° C., the impurities are considerably activated by annealing for about 20 minutes. 20 at 800-900 ° C
Anneal for 1 hour to 1 minute. On the other hand, first 500
A two-step activation annealing method in which the crystallinity is sufficiently recovered by annealing at ˜800 ° C. for about 1 to 20 hours and then activation is performed at a high temperature of 900 to 1000 ° C. is also effective. In addition, RT using infrared lamp or halogen lamp
A (Rapid Thermal Annealin
The g) method is also effective. Furthermore, it is also effective to use a laser activation method using a laser beam or the like.

Next, when hydrogen ions are introduced by a method such as a hydrogen plasma method, a hydrogen ion implantation method, or a hydrogen diffusion method from a plasma nitride film, a dangling bond existing at a grain boundary or a gate oxide film is formed. Defects existing at the interface and the like, and defects existing at the junction between the source / drain portion and the channel portion are inactivated. Such a hydrogenation step may be performed before stacking the interlayer insulating film 5-13. Alternatively, the hydrogenation step may be performed after forming a source electrode and a drain electrode, which will be described later.

Next, as shown in FIG. 7B, a contact hole is formed in the interlayer insulating film 5-13 by photoetching. Then, as shown in FIG.
And the drain electrode 5-15 is formed. The source electrode and the drain electrode are formed of a metal material such as aluminum or chromium. In this way, a thin film transistor is formed.

(Embodiment 3) Next, an embodiment of the third invention of the present invention shown in FIG. 1C will be described.
A non-single crystal semiconductor thin film is formed on the insulating amorphous material. As the insulating amorphous material, a quartz substrate, a glass substrate, a nitride film, a SiO ₂ film or the like is used. When using a quartz substrate, the process temperature is allowed up to about 1200 ° C., but when using a glass substrate, it is limited to a low temperature process of 600 ° C. or lower. Hereinafter, a case where a quartz substrate is used and a solid phase growth Si thin film is used as the non-single crystal semiconductor thin film will be described as an example. The steps from the silicon thin film formation to the gate oxide film formation are shown in FIGS. 8 (a) to 8 (d). Since these steps have been described in the sections of the first and second embodiments, detailed description thereof will be omitted here.

Next, the gate electrode forming step will be described. As shown in FIG. 8E, the main gate electrode 8
-5 is formed. The main gate electrode material is a polycrystalline silicon thin film, a silicide film such as molybdenum silicide, tungsten silicide or titanium silicide, a metal film such as aluminum or chromium, or a transparency such as ITO or SnO ₂ . A conductive film or the like can be used. As a film forming method, a CVD method, a sputtering method, a vacuum evaporation method, a plasma CV
Although there is a method such as the D method, the detailed description is omitted here.

Next, a low concentration impurity element is added to form an LDD region 8-6 as shown in FIG. 9 (a). LD with self-alignment using the main gate electrode 8-5 as a mask
The D region 8-6 is formed. 8-7 represents an ion beam of impurities. Like the source and drain regions,
In the case of an Nch thin film transistor, a donor type impurity is added,
In the case of a Pch thin film transistor, an acceptor type impurity is added. The impurity concentration of the LDD region is made lower than that of the source and drain regions. When using the ion implantation method, the ion implantation dose is
It is about 1 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² . The impurity concentration is about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ . As the impurity addition method, in addition to the ion implantation method, there are methods such as the laser doping method and the plasma doping method as described above.

Next, as shown in FIG. 9B, the second
The insulating film 8-8 is formed. An oxide film, a nitride film, or the like is used as the second insulating film material. LPCVD or plasma CVD is a simple method for forming the nitride film. Ammonia gas (N
A mixed gas of H ₃ ), silane gas and nitrogen gas, a mixed gas of silane gas and nitrogen gas, or the like is used. If the film thickness is too thick, the on-current decreases significantly, and conversely if it is too thin, the effect of reducing the off-leakage current disappears. Therefore, it is necessary to find an optimum value for the film thickness of the second insulating film from the relationship between the on-current and the off-leakage current.
Å to 3000 Å is suitable.

Subsequently, as shown in FIG. 9C, a gate contact hole 8-9 is formed in the second insulating film 8-8 by photolithography to expose a part of the main gate electrode.

Subsequently, as shown in FIG. 9D, a sub-gate electrode 8-10 is formed. The material of the sub-gate electrode is basically the same as the material of the main gate electrode, and a description thereof will be omitted. The sub-gate electrode 8-10 completely overlaps the main gate electrode 8-5. The distance L from the end of the main gate electrode pattern to the end of the sub-gate electrode pattern represents the LDD length, which is represented by 8-11 in the figure. The offset length L has to be optimized depending on the value of the lateral diffusion length Y _j of the ion-implanted impurities, but about 1.5 μm to 4 μm is suitable for a thin film transistor. In the figure, L is shown to be equal on both sides of the gate electrode,
This does not necessarily have to be equal.

Next, as shown in FIG. 10A, an acceptor type or a donor type impurity is ion-implanted into the first semiconductor layer by an ion implantation method to form a source region and a drain region in a self-aligned manner. To do. In FIG. 10A, 8-12 indicates a source region which is ion-implanted at a high concentration, and 8-13 indicates a drain region.

Boron (B) or the like is used as the acceptor type impurity. As the donor type impurity, phosphorus (P), arsenic (As) or the like is used. As an impurity addition method, there are methods such as a laser doping method and a plasma doping method other than the ion implantation method. The arrow indicated by 8-11 represents the ion beam of impurities. When a quartz substrate is used as the insulating amorphous material 8-1, a thermal diffusion method can be used. The impurity dose amount is about 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ^-2 . Converted into impurity concentration, the source 8-12 and the drain region 8-13 have about 1 × 10 ¹⁹ to 1 × 10 ^22.
It is about cm ^-3 .

Next, as shown in FIG. 10B, an interlayer insulating film 8-15 is laminated. An oxide film, a nitride film, or the like is used as the material for the interlayer insulating film. The insulating layer may have any thickness as long as it has a good insulating property, but it is usually several thousand Å to several μm. LPCVD or plasma CVD is a simple method for forming the nitride film. For the reaction, a mixed gas of ammonia gas (NH ₃ ) and silane gas and nitrogen gas, a mixed gas of silane gas and nitrogen gas, or the like is used. Then, activation annealing is performed for the purpose of densification of the interlayer insulating film, activation of the source region and drain region, and recovery of crystallinity. As the conditions of activation annealing, the temperature is lowered to about 800 to 1000 ° C. in an N ₂ gas atmosphere, and the annealing time is set to about 20 minutes to 1 hour. At 900 to 1000 ° C., the impurities are considerably activated by annealing for about 20 minutes. 20 at 800-900 ° C
Anneal for 1 hour to 1 minute. On the other hand, first 500
A two-step activation annealing method in which the crystallinity is sufficiently recovered by annealing at ˜800 ° C. for about 1 to 20 hours and then activation is performed at a high temperature of 900 to 1000 ° C. is also effective. In addition, RT using infrared lamp or halogen lamp
A (Rapid Thermal Annealin
The g) method is also effective. Furthermore, it is also effective to use a laser activation method using a laser beam or the like.

Next, when hydrogen ions are introduced by a method such as a hydrogen plasma method, a hydrogen ion implantation method, or a method of diffusing hydrogen from a plasma nitride film, dangling bonds existing at crystal grain boundaries or a gate oxide film. Defects existing at the interface and the like, and defects existing at the junction between the source / drain portion and the channel portion are inactivated. Such a hydrogenation process may be performed before stacking the interlayer insulating films 8-15. Alternatively, the hydrogenation step may be performed after forming a source electrode and a drain electrode, which will be described later.

Next, as shown in FIG. 10C, a contact hole is formed in the interlayer insulating film 8-15 by photoetching. Then, as shown in FIG.
6 and the drain electrode 8-17 are formed. The source electrode and the drain electrode are formed of a metal material such as aluminum or chromium. In this way, a thin film transistor is formed.

Example 4 Finally, a method of manufacturing an LDD structure thin film transistor to which the tapered main gate electrode shown in FIG. 1D is applied will be described. The process from the silicon thin film formation to the gate oxide film formation is shown in FIG.
It is shown from (a) to FIG. 11 (d). These steps have been described in the paragraphs 1 to 3 of the embodiment, so detailed description thereof will be omitted here.

Next, the gate electrode forming step will be described.

As shown in FIG. 11E, a tapered main gate electrode 11-5 is formed. As the material of the main gate electrode, a polycrystalline silicon thin film, a silicide film such as molybdenum silicide, tungsten silicide or titanium silicide, a polycide film in which a silicide film is laminated on a polycrystalline silicon film, or aluminum or chromium is used. A metal film or a transparent conductive film such as ITO or SnO ₂ can be used. As a film forming method, CV
There are methods such as the D method, the sputtering method, the vacuum deposition method, and the plasma CVD method, but the detailed description thereof is omitted here.

The tapered gate electrode is formed by mixing oxygen gas (O ₂ ) as an etching gas and performing plasma etching. Usually, the polycrystalline silicon, the silicide film, the polycide film, or the like is plasma-etched by using Freon gas (CF ₄ ).
At this time, when O ₂ gas is mixed, the gate electrode is processed while the resist serving as the mask is also removed by etching. Therefore, the tapered gate electrode 11-5 as shown in FIG. 11E is formed. O ₂
When the gas partial pressure of the gas is increased, the taper shape becomes gentler. In this way, the taper shape can be controlled by the voltage division ratio.

Next, a low concentration impurity element is added to form an LDD region 11-6 as shown in FIG. LDD regions 11-6 are formed in a self-aligned manner using the main gate electrode 11-5 as a mask. 11-7 represents an ion beam of impurities. Similar to the source and drain regions, a donor type impurity is added in the case of an Nch thin film transistor, and an acceptor type impurity is added in the case of a Pch thin film transistor. The impurity concentration of the LDD region is made lower than that of the source and drain regions. When the ion implantation method is used, the ion implantation dose amount is about 1 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² . The impurity concentration is about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ . As the impurity addition method, in addition to the ion implantation method, there are methods such as the laser doping method and the plasma doping method as described above.

Next, as shown in FIG.
By directly oxidizing the main gate electrode, the second
The insulating film 11-8 is formed. The method for forming the second insulating film was briefly described in the description of the method for forming the gate oxide film. A method such as a thermal oxidation method, a plasma oxidation method or a high pressure oxidation method can be considered. The thermal oxidation method has been described above and will not be described. The plasma oxidation method directly oxidizes a silicon film in oxygen plasma, and has a feature that an oxide film can be formed even at a low temperature of 600 ° C. or lower. The high-pressure oxidation method directly oxidizes silicon in a high-pressure oxygen atmosphere.
An oxide film can be formed at a low temperature of 600 ° C. in a high pressure oxygen atmosphere of about 10,000 Torr to 370000 Torr. Since the gate oxide film is formed, it is desirable to form the second insulating film at a temperature as low as possible. If the film thickness is too thick, the on-current decreases significantly, and conversely if it is too thin, the effect of reducing the off-leakage current disappears. Therefore, it is necessary to find an optimum value for the film thickness of the second insulating film from the relationship between the on-current and the off-leakage current.
Å to 3000 Å is suitable.

Subsequently, as shown in FIG. 12C, a gate contact hole 11-9 is formed in the second insulating film 11-8 by photolithography to expose a part of the main gate electrode.

Subsequently, as shown in FIG. 12D, a sub-gate electrode 11-10 is formed. The material of the sub-gate electrode is basically the same as the material of the main gate electrode, and a description thereof will be omitted. Sub-gate electrode 11-10
Completely overlaps the main gate electrode 11-5. The distance L from the end of the main gate electrode pattern to the end of the sub gate electrode pattern represents the LDD length, which is represented by 11-11 in the figure. The offset length L has to be optimized depending on the value of the lateral diffusion length Y _j of the ion-implanted impurities, but about 1.5 μm to 4 μm is suitable for a thin film transistor. In the figure, L is shown to be equal on both sides of the gate electrode, but this does not necessarily have to be equal.

Next, as shown in FIG. 13A, an acceptor type or donor type impurity is ion-implanted into the first semiconductor layer by an ion implantation method to form a source region and a drain region in a self-aligned manner. To do. In FIG. 13A, 11-12 indicates a source region which is ion-implanted at a high concentration, and 11-13 indicates a drain region.

Boron (B) or the like is used as the acceptor type impurity. As the donor type impurity, phosphorus (P), arsenic (As) or the like is used. As an impurity addition method, there are methods such as a laser doping method and a plasma doping method other than the ion implantation method. The arrows indicated by 11-14 represent ion beams of impurities. When a quartz substrate is used as the insulating amorphous material 11-1, a thermal diffusion method can be used. Impurity dose amount is 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm
^-2 . When converted to impurity concentration, the source 11-
12 and the drain region 11-13 have a size of about 1 × 10 ¹⁹ to 1 × 10 ²² cm ⁻³ .

Next, as shown in FIG. 13B, an interlayer insulating film 11-15 is laminated. As the material for the interlayer insulating film,
An oxide film or a nitride film is used. The insulating layer may have any thickness as long as it has a good insulating property, but it is usually several thousand Å to several μm. LPCVD or plasma CVD is a simple method for forming the nitride film. The reaction is
A mixed gas of ammonia gas (NH ₃ ) and silane gas and nitrogen gas, a mixed gas of silane gas and nitrogen gas, or the like is used. Then, activation annealing is performed for the purpose of densification of the interlayer insulating film, activation of the source region and drain region, and recovery of crystallinity. The activation annealing conditions are 800 to 1000 ° C. in a N ₂ gas atmosphere.
The temperature is lowered to about 10 minutes, and the annealing time is set to about 20 minutes to 1 hour. At 900 to 1000 ° C., the impurities are considerably activated by annealing for about 20 minutes. 2 at 800-900 ° C
Anneal for 0 minutes to 1 hour. On the other hand, first 50
A two-step activation annealing method in which the crystallinity is sufficiently recovered by annealing at 0 to 800 ° C. for about 1 to 20 hours and then activated at a high temperature of 900 to 1000 ° C. is also effective. In addition, RT using infrared lamp or halogen lamp
A (Rapid Thermal Annealin
The g) method is also effective. Furthermore, it is also effective to use a laser activation method using a laser beam or the like.

Next, when hydrogen ions are introduced by a method such as a hydrogen plasma method, a hydrogen ion implantation method, or a hydrogen diffusion method from a plasma nitride film, dangling bonds existing at crystal grain boundaries and a gate oxide film are formed. Defects existing at the interface and the like, and defects existing at the junction between the source / drain portion and the channel portion are inactivated. Such a hydrogenation step may be performed before stacking the interlayer insulating films 11-15. Alternatively, the hydrogenation step may be performed after forming a source electrode and a drain electrode, which will be described later.

Next, as shown in FIG. 13C, a contact hole is formed in the interlayer insulating film 11-15 by photoetching. Then, as shown in FIG.
-16 and the drain electrode 11-17 are formed. The source electrode and the drain electrode are formed of a metal material such as aluminum or chromium. In this way, a thin film transistor is formed.

[0078]

As described above, with the offset gate structure according to the present invention described in the first and second embodiments, a thin film transistor having an extremely low off-leakage current can be realized. Furthermore, by providing the sub-gate electrode, it becomes possible to form a channel in the offset region when the thin film transistor is turned on. Therefore, the conventional offset gate structure thin film transistor has a problem that the on-current decreases, but the present invention makes it possible to prevent the on-current from decreasing. As described in the first embodiment, since the second insulating film is formed on the main gate electrode and the sub-gate electrode is provided thereon, the thickness of the gate oxide film on the offset is It is thicker than the thickness of the gate oxide film by the thickness of the second insulating film. This can be seen by referring to the sectional view of FIG. Therefore, the electric field strength in the offset region becomes very small, and as a result, the off leak current is reduced. Further, the gate voltage dependence of the off-leakage current is suppressed, and the current jump in the off-region can be eliminated. Further, since the main gate electrode and the sub-gate electrode are electrically connected to each other, the main gate electrode does not have four terminals, and is a thin film transistor having three terminals as usual.

As described in the second embodiment, the tapered gate electrode is formed and the gate electrode is directly oxidized, whereby the second insulating film can be formed without film deposition. it can. Since the main gate electrode has a tapered shape, when the main gate electrode is oxidized, the entire end portion of the film becomes an oxide film. Therefore, as shown in FIG. 1B, the film thickness of the gate oxide film on the offset becomes much thicker than the film thickness of the gate oxide film in the channel portion, so that the electric field strength in the offset region is very large. Get smaller. Therefore, the off leak current is reduced. Further, the gate voltage dependence of the off-leakage current is suppressed, and the current jump in the off-region can be eliminated. Moreover, the thin film transistor does not have four terminals but has three terminals as usual. According to the present invention, such a great effect can be obtained.

In the offset gate structure, the resistance in the offset region is high, which may cause a problem that the on-current is lowered. Therefore, it is the third and fourth embodiments that describe the method of manufacturing the LDD structure by applying the invention described in the first and second embodiments. LDD as in the present invention
With the structure, a thin film transistor with extremely low off-leakage current can be realized. As described in the section of Example 3, the provision of the sub-gate electrode makes it possible to form a channel in the LDD region when the thin film transistor is turned on. Therefore, the conventional LDD structure thin film transistor and the offset gate structure thin film transistor have a problem that the on-current decreases.
The present invention makes it possible to prevent a decrease in on-current. Further, as shown in FIG. 1C, the thickness of the gate oxide film on the LDD region is much thicker than the thickness of the gate oxide film on the channel portion, so that the electric field strength in the LDD region is very small. Become. Therefore, the off-leakage current is reduced. Further, the gate voltage dependence of the off-leakage current is suppressed, and the current jump in the off-region can be eliminated. Moreover, the thin film transistor does not have four terminals but has three terminals as usual.

As described in the section of Embodiment 4, by forming a tapered main gate electrode and directly oxidizing it, the entire film at the end portion becomes an oxide film. Therefore, as shown in FIG. 1D, the film thickness of the gate oxide film on the LDD region is much thicker than the film thickness of the gate oxide film on the channel portion, so that the electric field strength of the LDD region is very large. Get smaller. As a result, the off leak current is reduced.
Further, the gate voltage dependence of the off-leakage current is suppressed, and the current jump in the off-region can be eliminated. Moreover, the thin film transistor does not have four terminals but has three terminals as usual. According to the present invention, such a great effect can be obtained.

Further, in order to manufacture a conventional thin film transistor having an offset gate structure, the LDD region is formed by providing the gate electrode side wall by anisotropic etching, but according to the present invention, such a complicated process is performed. It has become possible to omit it.

As described above, according to the present invention, it is possible to manufacture a thin film transistor in which the on-current is extremely reduced and the off-leakage current is extremely small in a very simple process with the three terminals. The present invention brings a great effect.

FIG. 14 illustrates the effect of the present invention on the transistor characteristics. FIG. 14 is a diagram showing the characteristics of the Nch thin film transistor. The horizontal axis is the gate voltage,
The vertical axis represents the drain current. 14-1 is a transistor curve of a conventional non-offset gate structure thin film transistor. Although a large on-current can be obtained, the off-leakage current is large, and the off-leakage current depending on the gate voltage in the off-region has a very large jump. 14-
Reference numeral 2 is a transistor curve of a conventional offset gate structure thin film transistor. The off-leakage current is reduced and the jump is suppressed, but the on-current is reduced. This is because the offset region is connected to the channel region in series as a high resistance region. On the other hand, the transistor curve of the thin film transistor manufactured according to the present invention is shown by the curve 14-3. According to the present invention, the reduction of the off-leakage current is realized while keeping the on-current as high as that of the non-offset gate structure thin film transistor.

FIG. 15 is a diagram for explaining the effect of the distance from the edge of the main gate electrode pattern to the edge of the sub-gate electrode pattern, that is, the offset length L in the present invention.
As a result of the experiments so far, it is known that when impurity atoms are ion-implanted into a polycrystalline silicon film and activation annealing is performed at about 1000 ° C., the implanted impurity atoms diffuse laterally by about 1 μm. This result is reflected in this figure. In the figure, 15-1 shows a transistor curve when L = 1 μm, and 15-2 shows a transistor curve when L = 1.5 μm. Since the lateral diffusion length of impurities is about 1 μm, when L = 1 μm, the source,
The drain region extends under the gate electrode. Therefore, as shown by the curve 15-1, the drain current when the gate voltage is negative, that is, the leak current, greatly jumps depending on the gate voltage. On the other hand, in the present invention, since L ≧ 1.5 μm, even if impurities are diffused in the lateral direction, the source / drain regions do not reach under the gate electrode. When L = 1.5 μm, an offset region of about 0.5 μm is formed on one side. Therefore, as shown by the curve 15-2, the jump of the leak current depending on the gate voltage is completely eliminated. However, due to the influence of the offset region, the channel resistance increases and the on-current decreases. Therefore, if L is made too large, the on-current becomes extremely small. A curve when L = 4.5 μm is shown in 8-3.
The offset region is about 3.5 μm on one side, and the channel resistance is too large, resulting in an extremely low on-current.
Therefore, in the present invention, L ≦ 4 μm is defined. In the thin film transistor of the present invention, when it is turned on, an electric field is applied to the offset region as well, so that a decrease in on current can be almost suppressed.

By using the solid phase growth method, it becomes possible to form a silicon thin film having excellent crystallinity on an amorphous insulating substrate, which greatly contributes to the development of SOI technology.

The thin film transistor manufactured by the present invention has excellent characteristics. The off-leakage current of the thin film transistor is smaller than that of the conventional one. Also, the threshold voltage is reduced and the transistor characteristics are greatly improved. There is no decrease in on-current due to the offset gate structure.

Since it becomes possible to manufacture a thin film transistor having excellent characteristics on an amorphous insulating substrate, a sufficiently high speed operation can be realized even when applied to an active matrix substrate in which a driver circuit is integrated on the same substrate. It Since the off-leakage current is very small, the pixel retention characteristic is also improved. Further, it has a great effect on reduction of power supply voltage, reduction of current consumption, and improvement of reliability. Also, 600 ℃
Since it can be manufactured by the following low-temperature process, its effect is great even when the cost and the area of the active matrix substrate are reduced.

When the present invention is applied to a contact-type image sensor in which a photoelectric conversion element and its scanning circuit are integrated in the same chip, it is extremely useful in increasing the reading speed, increasing the resolution, and obtaining gradation. Produce a great effect on. When higher resolution is achieved, it can be easily applied to a contact image sensor for color reading. Of course, the effect is great also for the reduction of power supply voltage, the reduction of current consumption, and the improvement of reliability. Further, since it can be manufactured by a low temperature process, the contact type image sensor chip can be lengthened, and a single chip can realize a reading device for a large facsimile such as A4 size or A3 size. Therefore, it is possible to avoid a technique such as double joining of the sensor chips and which is unreliable, and the mounting yield is improved.

Not only a quartz substrate or a glass substrate, but also a sapphire substrate or MgO.Al ₂ O ₃ , BP, CaF ₂
A crystalline insulating substrate such as the above can also be used.

Although the thin film transistor has been described above as an example, an element using a thin film, such as a bipolar transistor or a heterojunction bipolar transistor,
The present invention can be applied. Further, the present invention can be applied to an element using SOI technology such as a three-dimensional device.

Although the present invention has been described by taking the solid phase growth method as an example, the present invention is not limited to the solid phase growth method, and may be LPC.
The present invention can also be applied to the case where a thin film semiconductor device is formed by using a poly-Si thin film formed by the VD method or another method, for example, the EB vapor deposition method, the sputtering method or the MBE method. It can also be applied to a general MOS type semiconductor device.

[Brief description of drawings]

1A to 1D are structural cross-sectional views of a thin film transistor of the present invention.

2A to 2E are process cross-sectional views of a thin film transistor showing an embodiment of the present invention.

3A to 3D are process cross-sectional views of a thin film transistor showing an embodiment of the present invention. However,
(A) continues from FIG. 2 (e).

4A to 4B are process cross-sectional views of a thin film transistor showing an embodiment of the present invention. However,
(A) continues from FIG. 3 (d).

5A to 5E are process cross-sectional views of a thin film transistor showing an embodiment of the present invention.

6A to 6D are process cross-sectional views of a thin film transistor showing an embodiment of the present invention. However, FIG.
(A) continues from FIG. 5 (e).

7A to 7B are process cross-sectional views of a thin film transistor showing an embodiment of the present invention. However,
(A) continues from FIG. 6 (d).

8A to 8E are process cross-sectional views of a thin film transistor showing an embodiment of the present invention.

9A to 9D are process cross-sectional views of a thin film transistor showing an embodiment of the present invention. However, in FIG.
(A) continues from FIG. 8 (e).

10A to 10C are process cross-sectional views of a thin film transistor showing an embodiment of the present invention. However,
0 (a) continues from FIG. 9 (d).

11A to 11E are process cross-sectional views of a thin film transistor showing an embodiment of the present invention.

12A to 12D are process cross-sectional views of a thin film transistor showing an embodiment of the present invention. However,
2 (a) continues from FIG. 11 (e).

13A to 13C are process cross-sectional views of a thin film transistor showing an embodiment of the present invention. However,
3 (a) continues from FIG. 12 (d).

FIG. 14 is a characteristic diagram of an Nch thin film transistor showing the effect of the present invention.

FIG. 15 is a characteristic diagram of an Nch thin film transistor showing the effect of the offset length L in the present invention.

FIG. 16 is a structural cross-sectional view illustrating a conventional offset gate structure thin film transistor.

[Explanation of symbols]

1-1 Main gate electrode 1-2 Sub-gate electrode 1-3 Gate insulating film 1-4 Fourth insulating film 1-7 Tapered main gate electrode 1-8 LDD region 2-4 Gate insulating film 2-5 Main gate Electrode 2-6 Second insulating film 2-7 Gate contact hole 2-8 Sub-gate electrode 2-9 Offset region 2-10 Source region 2-11 Drain region 5-4 Gate insulating film 5-5 Tapered main gate electrode 5-6 Second insulating film formed by oxidation of main gate electrode 5-7 Gate contact hole 5-8 Sub-gate electrode 5-9 Offset region 5-10 Source region 5-11 Drain region 8-4 Gate insulating film 8 -5 Main gate electrode 8-6 LDD region 8-8 Second insulating film 8-9 Gate contact hole 8 10 sub-gate electrode 8-11 LDD region 8-12 source region 8-13 drain region 11-4 gate insulating film 11-5 tapered main gate electrode 11-6 LDD region 11-8 formed by oxidizing main gate electrode Second
Insulating film 11-9 Gate contact hole 11-10 Sub-gate electrode 11-11 LDD region 11-12 Source region 11-13 Drain region 14-1 Characteristics of non-offset gate structure Nch thin film transistor manufactured by conventional method 14-2 Conventional method 14-3 Characteristics of Nch Thin-Film Transistor Produced by Offset Gate Structure 14-3 Characteristics of Nch Thin-Film Transistor Fabricated According to the Present Invention 15-1 Characteristics of Nch Thin-Film Transistor when L = 1 μm 15-2 Characteristics of Nch Thin-Film Transistor when L = 1.5 μm Characteristics of Nch thin film transistor when 15−3 L = 4.5 μm

Claims (16)

[Claims] 1. A planar type thin film semiconductor device having a source region, a drain region, a gate insulating film and a gate electrode, wherein a main gate electrode is provided on the gate insulating film, and a contact hole is provided on the main gate electrode. It has a sub-gate electrode electrically connected to the main gate electrode with a second insulating film interposed therebetween, and a source region and a drain region are formed in a self-aligned manner by using the sub-gate electrode as a mask. Thin film semiconductor device. 2. When the sub-gate electrode length of claim 1 is L _s and the main gate electrode length is L _m , at least L _s > L
A thin film semiconductor device characterized by satisfying the condition of _m . 3. The thin film semiconductor device according to claim 1, wherein the sub-gate electrode completely overlaps the main gate electrode. 4. The method of manufacturing a thin film semiconductor device according to claim 1, wherein (a) a first semiconductor layer is formed on the insulating amorphous material, and a gate insulating film is formed on the semiconductor layer. (B) forming a main gate electrode on the gate insulating film, (c) forming a second insulating film on the main gate electrode, (d) the second insulating film Forming a gate contact hole in the substrate to expose a part of the main gate electrode, (e) forming a sub-gate electrode that completely overlaps the main gate electrode, (f) masking the sub-gate electrode Forming a source region, a drain region, and an offset region in a self-aligned manner with respect to the sub-gate electrode by ion-implanting impurities such as phosphorus, arsenic, or boron. Stacking an interlayer insulating film, (h) at least including a step of forming a contact hole in the interlayer insulating film and forming an electrode by a photo process in order to form a contact with the first semiconductor layer A method for manufacturing a thin film semiconductor device, comprising: 5. A planar type thin film semiconductor device having a source region, a drain region, a gate insulating film and a gate electrode, wherein a tapered main gate electrode is provided on the gate insulating film and the main gate electrode is oxidized. A second insulating film is formed on the main gate electrode, a contact hole is formed in the second insulating film to have a sub-gate electrode electrically connected to the main gate electrode, and the sub-gate electrode is masked. And a source region and a drain region are formed in a self-aligned manner as a thin film semiconductor device. 6. The sub-gate electrode length of claim 5 is L _s , and the main gate electrode length is L _m , at least L _s > L
A thin film semiconductor device characterized by satisfying the condition of _m . 7. The thin film semiconductor device according to claim 5, wherein the sub-gate electrode completely overlaps the main gate electrode. 8. The method of manufacturing a thin film semiconductor device according to claim 5, wherein (a) a first semiconductor layer is formed on the insulating amorphous material, and a gate insulating film is formed on the semiconductor layer. And (b) forming a tapered main gate electrode on the gate insulating film by taper etching, (c) directly oxidizing the main gate electrode, and
And (d) forming a gate contact hole in the second insulating film to expose a part of the main gate electrode, (e) completely overlapping the main gate electrode And (f) by ion-implanting impurities such as phosphorus, arsenic, or boron with the sub-gate electrode as a mask, the source region and the drain region are self-aligned with the sub-gate electrode. And a step of forming an offset region, (g) a step of laminating an interlayer insulating film, (h) a contact hole is formed in the interlayer insulating film by a photo step in order to form a contact with the first semiconductor layer. And a method of manufacturing a thin film semiconductor device, comprising at least a step of forming an electrode. 9. A planar type thin film semiconductor device having a source region, a drain region, a gate insulating film and a gate electrode, wherein a main gate electrode is provided on the gate insulating film, and the main gate electrode is used as a mask for low-concentration impurities. LDD (Lightly Doped)
A drain region is formed, and a sub-gate electrode electrically connected to the main gate electrode is sandwiched between the main gate electrode and a second insulating film having a contact hole, and the sub-gate electrode is used as a mask. A thin film semiconductor device, wherein a source region and a drain region are formed in a self-aligned manner by ion-implanting a high concentration of impurities. 10. The sub-gate electrode length of claim 9 is L _s ,
If the length of the main gate electrode is L _m , at least L _s >
A thin film semiconductor device characterized by satisfying the condition of L _m . 11. The thin film semiconductor device according to claim 9, wherein the sub-gate electrode completely overlaps the main gate electrode. 12. The method for manufacturing a thin film semiconductor device according to claim 9, wherein (a) a first semiconductor layer is formed on the insulating amorphous material, and a gate insulating film is formed on the semiconductor layer. (B) forming a main gate electrode on the gate insulating film, (c) forming a second insulating film on the main gate electrode, (d) masking the main gate electrode As 1 × 1
Forming an LDD region by ion-implanting an impurity such as phosphorus, arsenic, or boron at a low concentration of 0 ¹⁹ cm ^-3 or less; (e) forming a gate contact hole in the second insulating film; Exposing a part of the main gate electrode, (f) forming a sub-gate electrode so as to completely overlap the main gate electrode, (g) 1 × 10 ^{19 using the} sub-gate electrode as a mask
a step of forming a source region, a drain region and an offset region in a self-aligned manner with respect to the sub-gate electrode by ion-implanting a high-concentration impurity such as phosphorus, arsenic or boron of cm ⁻³ or more; Laminating an interlayer insulating film, (i) at least including a step of forming a contact hole in the interlayer insulating film and forming an electrode by a photo process in order to form a contact with the first semiconductor layer. A method for manufacturing a thin film semiconductor device, comprising: 13. A planar type thin film semiconductor device having a source region, a drain region, a gate insulating film and a gate electrode, wherein a tapered main gate electrode is provided on the gate insulating film, and the main gate electrode is used as a mask to reduce the thickness. LDD (Light
and a second insulating film is formed on the main gate electrode by oxidizing the main gate electrode, and a contact hole is formed in the second insulating film to form the main gate electrode. A thin film semiconductor device having a sub-gate electrode that is electrically connected, wherein a high concentration impurity is ion-implanted using the sub-gate electrode as a mask to form a source region and a drain region in a self-aligned manner. 14. The sub-gate electrode length of claim 13 is L
_s and the length of the main gate electrode are L _m , the thin film semiconductor device is characterized in that at least the condition of L _s > L _m is satisfied. 15. The thin film semiconductor device according to claim 13, wherein the sub-gate electrode completely overlaps the main gate electrode. 16. The method of manufacturing a thin film semiconductor device according to claim 13, wherein (a) a first semiconductor layer is formed on the insulating amorphous material, and a gate insulating film is formed on the semiconductor layer. (B) forming a tapered main gate electrode on the gate insulating film by taper etching, (c) 1 × 1 using the main gate electrode as a mask
A step of forming an LDD region by ion-implanting an impurity such as phosphorus, arsenic, or boron at a low concentration of 0 ¹⁹ cm ^-3 or less, (d) directly oxidizing the main gate electrode, and
And (e) forming a gate contact hole in the second insulating film to expose a part of the main gate electrode, (f) completely overlapping the main gate electrode Forming a sub-gate electrode as described above, (g) 1 × 10 ^{19 using the} sub-gate electrode as a mask
a step of forming a source region, a drain region and an offset region in a self-aligned manner with respect to the sub-gate electrode by ion-implanting a high-concentration impurity such as phosphorus, arsenic or boron of cm ⁻³ or more, (h) Laminating an interlayer insulating film, (i) at least including a step of forming a contact hole in the interlayer insulating film and forming an electrode by a photo process in order to form a contact with the first semiconductor layer. A method for manufacturing a thin film semiconductor device, comprising: