JP3163822B2 - Transistor and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor such as an active matrix type liquid crystal display having a transistor for switching each pixel, and a method of manufacturing the transistor.

[0002]

2. Description of the Related Art Thin film transistors are used in an active matrix type liquid crystal display device (hereinafter, referred to as a liquid crystal display) as a pixel switching element, a driver circuit, a contact type image sensor, and an SRAM.
(Static Random Access Memo
ries). However, in the conventional liquid crystal display, the scanning line and the gate electrode of the thin film transistor are formed only by one layer of the doped polysilicon film by the same process. Even if the impurity-doped polycrystalline silicon film is deposited, for example, at 3500 °, its sheet resistance is reduced only to about 20Ω / □. ｛IEICE Technical Report, SDM91
-164, The Institute of Electronics, Information and Communication Engineers, 1991. The problems when the conventional scanning lines and gate electrodes are applied to a liquid crystal display will be described below.

The first problem is that the disconnection of the scanning line causes a line defect, which lowers the quality of the liquid crystal display and lowers the yield. As a driving method of the liquid crystal display, it is usual to input a gate signal to the scanning line from both left and right sides. For example, even if a scanning line is broken at one point, a gate signal comes from both sides to the scanning line. However, when the resistance of the scanning line is high, the delay of the gate signal cannot be ignored and the response delay of the pixel near the disconnection becomes noticeable. Also, if there is a short circuit between the scanning line and the source line, we would like to cut the scanning lines on both sides of this short-circuit point to eliminate the effect of the short circuit. Would. If the scanning line can be reduced in resistance,
The delay of the gate signal coming from both sides is reduced to a level that does not cause a problem, and the display screen of the liquid crystal display is not affected at all.

[0004] The second problem is that flicker (screen flicker) and display unevenness cannot be suppressed. When a rectangular pulse is input to the scanning line, the time constant τ of the scanning line is
If R × C (R is the scanning line resistance and C is the scanning line capacitance) is large, the waveform of the rectangular pulse is distorted at the center of the screen, and the rising characteristics of the pixel transistors vary, resulting in flicker. Appears. If the scanning line resistance is high, the time constant τ increases, so that flicker cannot be suppressed. When applied to a large-screen or high-vision liquid crystal display, the above problem becomes more remarkable.

A third problem is that when an impurity-doped polycrystalline silicon film is used as in the past, the thickness of the polycrystalline silicon film is reduced to 5,000.
Even so, the sheet resistance is reduced only to about 15Ω / □. In order to further reduce the resistance, the film thickness needs to be 5000 ° or more. However, in this case, unevenness on the surface of the element becomes large, and the step coverage of a film or wiring formed thereon becomes a problem, which is a major factor in lowering the yield.

A fourth problem is that when silicide is used to reduce the resistance, the stress of the silicide on the quartz substrate is large. Comparing the values of the coefficient of linear expansion, the quartz substrate is 5.5 × 10 ⁻⁷ / deg.
i ₂ is 8.25 × 10 ^{−6 /} deg., WSi ₂ is 6.25 × 1
It is about 0 ^-6 / deg., Which is larger than the quartz substrate by one digit or more.
{Semiconductor Research 24, Industrial Research Committee, 1986} Accordingly, it is considered that the silicide film on the quartz substrate is subjected to stress and cracks and the like are easily formed in the film. This also causes a reduction in yield.

On the other hand, when the off-leak current of the thin film transistor is large, the retention characteristics of the pixels are deteriorated. Therefore, it is necessary to reduce the off-leak current in order to realize an excellent liquid crystal display. The leakage current in the off region of a normal thin film transistor strongly depends on the electric field intensity near the drain region, and the off-leakage current jumps up as the gate voltage increases toward the off side. In order to reduce the off-leak current, an LDD (Light
It is known that it is effective to form a tly-doped drain structure or an offset gate structure.

In the conventional LDD structure or offset gate structure, a complicated process such as providing a gate electrode side wall using anisotropic etching was required.

[0009]

In order to solve the above-mentioned problems of the conventional method, it is necessary to lower the value of the sheet resistance of the scanning line to about one-third of the conventional one, ie, about 5 to 8 Ω / □. There is. As one of the methods, a three-layer structure having a lowermost polycrystalline silicon film, a silicide film as an intermediate layer, and a polycrystalline silicon film as an uppermost layer is patterned by a single photoetching to form a gate electrode and a scanning line of the thin film transistor. There is a way to form it ｛Proceedings of T
he 12th International Dis
playResearch Conference
(Japan Display 1992) p45
1｝. Although there is no problem with the normal gate electrode structure, if the etching is further performed excessively to form the offset gate structure, the etching rate of the silicide film is the highest, and as shown in FIG. And become an overhang shape. Therefore, the film property on the step of the interlayer insulating film 5-9 deteriorates, and the disconnection rate of the wiring formed thereon increases. FIG. 5 is a cross-sectional view of a thin film transistor when a three-layer film of polycrystalline silicon / silicide / polycrystalline silicon is used as a gate electrode by one photoetching. 5-1
Is an insulating substrate, 5-2 is a semiconductor thin film, 5-3 is a source region, 5-4 is a drain region, 5-5 is a gate insulating film, 5
-6 is a lowermost polycrystalline silicon film, 5-7 is a silicide film, 5-8 is an uppermost polycrystalline silicon film,
5-6, 5-7, and 5-8 form a three-layer gate electrode. 5-9 is an interlayer insulating film, 5-10 is a source electrode, 5
-11 is a drain electrode.

It is an object of the present invention to reduce the resistance of a scanning line and the gate electrode of a thin film transistor, and to manufacture a thin film transistor having a low off-leakage current by an offset gate structure by a method which is not difficult even compared with the conventional process, so that pixel unevenness and pixel unevenness are reduced. An object of the present invention is to provide a method for easily realizing a liquid crystal display with less flicker and excellent pixel holding characteristics with a high yield.

[0011]

According to the present invention, there is provided a transistor having a two-layered gate electrode on a source / drain active region via a gate insulating film. Under the same etching conditions, a thin film in which the lower layer has an etching rate higher than that of the upper layer is stacked, and the upper gate electrode protrudes from the lower gate electrode. The method of manufacturing a transistor according to the present invention includes the steps of: forming a gate insulating film on an active region serving as a source / drain; forming a first thin film serving as a first gate electrode on the gate insulating film; Forming a second thin film to be a second gate electrode on one thin film, and forming the first gate electrode and the second gate electrode by simultaneously etching the first thin film and the second thin film. Wherein the etching rate of the first thin film is higher than the etching rate of the second thin film.

[0012]

[0013]

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, FIG. 1 shows a structure of a liquid crystal display having a thin film transistor having an offset gate structure using a two-layer scanning line and a two-layer gate electrode according to the present invention. FIG. 1A shows a structural plan view of one pixel, and FIG.
FIG. 1B is a structural cross-sectional view taken along a line AB in FIG. First, in FIG.
Reference numeral 3 denotes a scanning line, 1-7 denotes a source line, 1-5 denotes a semiconductor thin film constituting an active region of a thin film transistor, 1-6 denotes a contact hole, and 1-8 denotes a pixel electrode. The scanning line 1-13 has a two-layer structure of a thin film 1-3 having a high etching rate in a lower layer and a thin film 1-2 having a low etching rate in an upper layer. When the upper film 1-2 is formed of a low-resistance polycrystalline silicon film, the lower film 1-3 uses a silicide film or the like. As the silicide film, cobalt silicide (CoSi ₂ ) or nickel silicide (N
iSi), titanium silicide (TiSi ₂ ), molybdenum silicide (MoSi ₂ ), tungsten silicide (WSi ₂ ), or the like is used. The gate electrode of the thin film transistor is also integrally formed of the two-layer structure film. FIG. 1 is a cross-sectional view taken along a line AB.
(B). Under the same etching conditions, the etching rate of the silicide film is higher than the etching rate of the low-resistance polycrystalline silicon film. Accordingly, the pattern width of the lower film 1-3 is smaller than the pattern width of the upper film 1-2. The difference 1-15 in the pattern width is defined as the offset length L. Source region 1-10 of thin film transistor
The drain region 1-11 and the upper layer 1-2 are formed in a self-aligned manner. Therefore, the offset length L1
The area indicated by -15 is the offset area. 1-1
2 is an interlayer insulating film, and 1-14 is an insulating film having good step coverage.

Hereinafter, a method of manufacturing an active matrix substrate to which an offset gate thin film transistor having a two-layer scanning line and a two-layer gate electrode according to the present invention is applied will be described.

First, the present invention will be described with reference to a cross-sectional view taken along a line AB in FIG. As shown in FIG. 2, a non-single-crystal semiconductor thin film 2-2 is formed on the insulating amorphous material 2-1. As the insulating amorphous material, a quartz substrate, a glass substrate, a nitride film, a SiO ₂ film, or the like is used. When a quartz substrate is used, the process temperature is allowed up to about 1200 ° C., but when a glass substrate is used, the process is limited to a low temperature process of 600 ° C. or less.
Hereinafter, an example in which a quartz substrate is used and a solid-phase grown Si thin film is used as the non-single-crystal semiconductor thin film will be described. Of course, not only a solid-phase grown Si thin film, but also a polycrystalline Si thin film formed by a low pressure CVD method, a plasma CVD method, a sputtering method or the like, and an SOI (silicon silicon).
n Insulator) can be used to implement the present invention.

As shown in FIG. 2A, a mixed gas of SiH ₄ and H ₂ is decomposed by a 13.56 MHz high-frequency glow discharge using a plasma CVD apparatus to form an amorphous phase on a quartz substrate 2-1. The porous Si film 2-2 is deposited. The SiH ₄ partial pressure of the mixed gas is 10 to 20%, and the internal pressure in the deposit is 0.5.
About 1.5 torr. A substrate temperature of 250 ° C. or less and about 180 ° C. is suitable. The amount of bonded hydrogen determined by infrared absorption measurement was about 8 atomic%. The chamber before the deposition of the amorphous Si film 2-2 is subjected to Freon cleaning, and the deposited amorphous Si film is 2 × 10
Contains ¹⁸ cm ^-3 of fluorine. Therefore, in the present invention, after the freon cleaning, dummy deposition is performed,
Perform the actual deposition. Alternatively, abolish freon cleaning,
The chamber is cleaned by another method such as beading.

Subsequently, the amorphous Si film is formed at a temperature of 400.degree.
Heat treatment at 00 ° C. to release hydrogen. This step is intended to prevent explosive desorption of hydrogen.

Next, the amorphous thin film 2-2 is grown in a solid phase. For the solid phase growth method, furnace annealing using a quartz tube is convenient. As an annealing atmosphere, nitrogen gas, hydrogen gas, argon gas, helium gas or the like is used. 1x1
Anneal in a high vacuum atmosphere of 0 ^-6 to 1 × 10 ^-10 Torr
May be performed. Solid phase growth annealing temperature is 500 ° C ~
700 ° C. In such low temperature annealing, selectively,
Only crystal grains having a crystal orientation with a small activation energy for crystal growth grow and grow slowly and slowly.
In the experiment of the inventor, the annealing temperature was 600 ° C. and the annealing temperature was 600 ° C.
By performing solid phase growth for 16 hours, a silicon thin film having a large grain diameter of 2 μm or more has been obtained. In FIG. 2B, reference numeral 2-3 denotes a solid-phase grown silicon thin film.

Although the method of forming a silicon thin film by the solid phase growth method has been described above, in addition to the above, LPCVD
The silicon thin film may be formed by a method such as a sputtering method or a vapor deposition method.

Next, the solid-phase-grown silicon thin film is patterned by photolithography in an island shape as shown in FIG.

Next, as shown in FIG. 2D, a gate oxide film 2-4 is formed. As a method of forming the gate oxide film, 500 ° C. such as an LPCVD method, a photo-excitation CVD method, a plasma CVD method, an ECR plasma CVD method, a high vacuum deposition method, a plasma oxidation method, or a high pressure oxidation method. There are the following low-temperature methods. The gate oxide film formed by the low-temperature method becomes an excellent film which is denser and has less interface states by heat treatment. When a quartz substrate is used as the amorphous insulating substrate 2-1, a thermal oxidation method can be used. The thermal oxidation method includes d
There are a ry oxidation method and a wet oxidation method. At about 800 ° C. or higher, an oxide film is formed. To use a quartz substrate, for example, 1
It is suitable to carry out dry oxidation at a temperature as high as 000 ° C. or higher. The thickness of the gate oxide film is from 500 ° to 1
About 500 ° is suitable.

After the formation of the gate oxide film, boron may be channel-implanted as necessary to perform channel doping.
This is intended to prevent the threshold voltage of the Nch thin film transistor from shifting to the negative side. The amorphous silicon film has a deposition thickness of 500 to 1;
In the case of about 500 °, the dose of boron is 1 × 10 ¹²
About 5 × 10 ¹² cm ⁻² is suitable. When the thickness of the amorphous silicon film is as thin as 500 ° or less, boron-
The amount is reduced to 1 × 10 ¹² cm ^-2 or less as a guide. When the film thickness is 1500 ° or more, the boron dose is increased, and the standard is 5 × 10 ¹² cm.
^-2 or more.

Instead of channel ion implantation, boron may be added at the time of depositing the silicon film 2-2. This is obtained by flowing a diborane gas (B ₂ H ₆ ) together with a silane gas into the chamber during the silicon film deposition to cause a reaction.

Next, the process proceeds to a process of forming a two-layer gate electrode. As shown in FIG. 2E, a lower thin film 2-5 having a high etching rate is formed. Here, a film is formed using a silicide film. As a film forming method, a co-evaporation method of simultaneously depositing metal and silicon from separate crucibles, a sputtering method, or a silane (SiH ₄ ) gas and a metal fluoride gas (for example, MoF ₆ ,
A method such as CVD method by thermal decomposition of WF _6, etc.). Among the above methods, a sputtering method using a mixed crystal target of metal and silicon is often used because of excellent controllability of the composition ratio of the silicide film.

For example, when a MoSi ₂ film is used as the silicide film, sputtering is performed using a mixed crystal target such as MoSi _3.5 having a composition ratio richer than silicon in stoichiometry. This aims at bringing the formed film close to the stoichiometric composition and relaxing the stress. As described above, since the coefficient of linear expansion of the silicide film differs from the quartz substrate by one digit or more, as described above, the thickness of the silicide film is limited to about 2500 ° at the maximum.
If the film thickness is larger than this, cracks may enter the film itself.

Next, a thin film 2-6 having a small etching rate is formed as an upper layer in FIG. Here, a case where a low-resistance polycrystalline silicon film is used will be described as an example. First, a film formation method using a diffusion method will be described. A polycrystalline silicon film is deposited by a method such as LPCVD,
P is added to the polycrystalline silicon film by a POCl ₃ diffusion method at 0 to 1000 ° C. At this time, since a thin oxide film is formed on the polycrystalline silicon film, the oxide film is removed with an aqueous solution containing hydrofluoric acid. There is also a method of adding P by an ion implantation method. In addition, there is a method of depositing a doped polycrystalline silicon film to form the upper film 2-6. This is a method of forming a film by decomposing a mixed gas of SiO ₂ gas and PH ₃ gas. An impurity-added polycrystalline silicon film is formed by thermal decomposition at 500 to 700 ° C. in the LPCVD method and glow discharge decomposition in the PECVD method. In the PECVD method, an amorphous silicon film can be formed at about 300 ° C. It is also an effective method to grow this doped amorphous silicon film into a high-quality polycrystalline silicon film by the solid phase growth method as described above.

The P-doped polycrystalline silicon film of 1 × 10 ¹⁹ cm ^-3 or more is formed by the method described above to a thickness of 500 to 2,000.
Deposit about Å.

Next, the process proceeds to a gate electrode forming process. As shown in FIG. 3B, a resist mask 2-7 is formed by photolithography.

Subsequently, as shown in FIG. 3C, a gate electrode is formed. Lower film 2 with high etching rate
-5 and the thin film 2-6 having a small etching rate are simultaneously patterned. Etching is performed using a dry etching apparatus. Usually, a polycrystalline silicon, a silicide film, a polycide film, or the like is plasma-etched by causing a plasma discharge of a freon gas (CF ₄ ). At this time, if oxygen gas (O ₂ ) is mixed, the gate electrode is processed while the resist serving as a mask is also removed by etching. Therefore, a tapered gate electrode is formed. When the gas partial pressure of the O ₂ gas is increased, a more gentle taper shape is obtained. Thus, the taper shape can be controlled by the partial pressure ratio. According to an experiment performed by the inventor using a molybdenum silicide film as a silicide film, the same etching conditions were used.
The etching rate of the molybdenum silicide film was about 1.2 times the etching rate of the polycrystalline silicon film.
Due to this difference in the etching rate, the pattern width of the lower layer film 2-5 becomes smaller on one side by L than the pattern width of the upper layer.
L is called an offset length 2-8. In order to reduce the off-leak current of the thin film transistor, L is suitably 0.5 μm or more, preferably 1 to 1.5 μm.

Next, as shown in FIG.
The resist mask 2-7 is peeled off.

Next, as shown in FIG. 3E, ion implantation for forming a source region and a drain region is performed. By ion implantation, acceptor-type or donor-type impurities are ion-implanted into the first semiconductor layer, and a source region and a drain region are formed in a self-aligned manner with respect to the upper layer film 2-6. In FIG. 3E, 2-9
Is a source region implanted at a high concentration, and 2-1.
0 indicates a drain region.

As the acceptor type impurity, boron (B) or the like is used. Phosphorus (P) or arsenic (As) is used as the donor-type impurity. Examples of the impurity doping method include a laser doping method and a plasma doping method in addition to the ion implantation method. Arrows indicated by 2-11 indicate ion beams of impurities. When a quartz substrate is used as the insulating amorphous material 2-1, a thermal diffusion method can be used. The impurity dose is about 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻² . In terms of impurity concentration, the source region 2-9 and the drain region 2-10 have a density of about 1 × 10 ¹⁹ to 1 × 10
It is about ²² cm ^-3 .

In the embodiment, the ion implantation is described after the resist mask 2-7 is peeled off. However, the resist mask may be peeled off after the ion implantation.

Subsequently, as shown in FIG. 4A, a lower insulating film 2-12 is laminated. As the material of the lower insulating film, an oxide film or a nitride film having excellent step coverage is used.
For example, SOG (Spin On Glass) is excellent. This is a method in which a solution in which SiO ₂ is dissolved is applied by a spinner, and the solvent is removed by a subsequent heat treatment to form an oxide film. Therefore, the step coverage is remarkably excellent. It is particularly suitable when an insulating film is formed on an overhang structure as in the present invention.

However, since the SOG film has a disadvantage that cracks are easily generated, the thickness of the insulating film formed by this method is about 500 °, and at most about 1000 °. Therefore, as shown in FIG. 4B, it may be necessary to form an interlayer insulating film 2-13 on the lower insulating film 2-12 formed of SOG. As an oxide film forming method, LPCVD method, APCVD method, plasma C
There are methods such as a VD method, an ECR plasma CVD method, and a light excitation CVD method. Further, an organic silicon compound TEOS (Tetra Ethyl Ortho-S) is used as a source gas.
ilicate) and ozone. TEO
When S is used, excellent step coverage is realized. Also, P
SG (Phosphosilicate glass)
By reflowing BSG (Borosilicate glass) or BSG (Borosilicate glass), more excellent step coverage can be realized. Regarding the film thickness, the thickness is usually several thousand to several μm. As a method for forming a nitride film, an LPCVD method, a plasma CVD method, or the like is simple. The reaction is
A mixed gas of ammonia gas (NH ₃ ), silane gas and nitrogen gas, or a mixed gas of silane gas and nitrogen gas is used. If the step coverage of the interlayer insulating film is good, the lower insulating film 2-12 described above becomes unnecessary.

Subsequently, activation annealing is performed for the purpose of densifying the interlayer insulating film, activating the source region and the drain region, and restoring crystallinity. The conditions for the activation annealing are as follows: the temperature is lowered to about 800 to 1000 ° C. in an N ₂ gas atmosphere, and the annealing time is about 20 minutes to 1 hour. At 900 to 1000 ° C., the impurities are considerably activated by annealing for about 20 minutes. 20 at 800-900 ° C
Anneal for a minute to an hour. On the other hand, first 500
A two-step activated annealing method is also effective, in which the crystallinity is sufficiently recovered by annealing at ~ 800 ° C for about 1 to 20 hours and then activated at a high temperature of 900 to 1000 ° C. In addition, RT using an infrared lamp or a halogen lamp
A (Rapid Thermal Annealin)
The method g) is also effective. Furthermore, it is effective to use a laser activation method using a laser beam or the like.

Next, when hydrogen ions are introduced by a hydrogen plasma method, a hydrogen ion implantation method, or a method of diffusing hydrogen from a plasma nitride film, dangling bonds existing at crystal grain boundaries, Defects existing at the oxide film interface and at the junction between the source, drain and channel are inactivated. Such a hydrogenation step may be performed before laminating the interlayer insulating film 2-13. Alternatively, the hydrogenation step may be performed after forming a source electrode and a drain electrode described later.

Next, as shown in FIG. 4C, contact holes are formed in the interlayer insulating film 2-13 and the gate oxide film 2-4 by photoetching. Then, a source electrode 2-14 and a drain electrode 2-15 are formed as shown in FIG. The source electrode and the drain electrode are formed of a metal material such as aluminum or chromium. Thus, a thin film transistor is formed.

[0040]

As described above, according to the present invention, a very great effect can be expected on the improvement of the characteristics of the liquid crystal display such that the resistance of the scanning line can be reduced and the off-leak current of the thin film transistor can be reduced. .

With the two-layer scanning line using the silicide film as in the present invention, the sheet resistance of the scanning line is reduced to about 8 Ω / □, which is one third of 25 Ω / □ of the conventional polycrystalline silicon. I can do it. Therefore, as described above, various problems of the liquid crystal display can be solved.

Since gate signals are sent to the scanning lines from both the left and right sides, even if a disconnection occurs in the scanning lines, the signal delay is small because the scanning line resistance is sufficiently small, and there is no effect on the screen display of the liquid crystal display. Absent. Therefore, even if a short circuit occurs between the source line and the scanning line, the short-circuit defect can be relieved by cutting the scanning lines on both sides of the short-circuit point. Thus, there is a great effect on the improvement of the yield.

Since the scanning line resistance is reduced, the time constant τ of the scanning line is reduced. Therefore, the rising characteristics of the pixel transistors at the center and the edge of the screen become uniform. as a result,
Flicker or display unevenness can be reduced. Moreover, since it is not necessary to reduce the line capacity of the scanning line,
The retention characteristics of the pixels do not deteriorate. As described above, according to the present invention, a liquid crystal display with extremely little flicker or display unevenness can be realized without lowering the pixel holding characteristics.

As for a high-vision TFT, a large TFT panel of about 4 inches has to be produced because a light valve or the like is required in order to constitute a projection type display. When a panel having such a long scanning line is manufactured, the effect of the present invention is further enhanced.

Since the resistance of the scanning line is reduced, it is possible to eliminate an additional pixel storage capacitor line. Therefore, the aperture ratio is improved, and as a result, a very bright liquid crystal display can be realized.

The gate electrode of the thin film transistor was formed of a lower film made of a silicide film having a high etching rate and an upper film made of a polycrystalline silicon film having a small etching rate and doped with impurities. Therefore, it is possible to easily form the offset gate structure in one photo process. As a result, the off-leak current of the thin film transistor becomes extremely small, and the pixel holding characteristics are improved. Further, there is a great effect on reduction of current consumption.

On the other hand, the silicide film has a very large uneven surface. By stacking a polycrystalline silicon film on the uppermost layer, the unevenness can be smoothed and a flat surface can be obtained. As a result, the adhesion of the oxide film stacked on the gate electrode is improved, and the abnormal etching when a contact hole is formed in the oxide film is eliminated.

Since it has an offset gate structure,
The pixel retention characteristics are improved. Further, a great effect is expected to reduce current consumption.

The use of the solid phase growth method makes it possible to produce a silicon thin film having excellent crystallinity on an amorphous insulating substrate, which greatly contributes to the development of SOI technology. Reducing the resistance of the gate line has a great effect on maximizing the characteristics of the thin film transistor improved by a method such as solid phase growth and realizing a very excellent liquid crystal display.

When the present invention is applied to a contact-type image sensor in which a photoelectric conversion element and its scanning circuit are integrated on the same chip, it is very difficult to increase the reading speed, increase the resolution, and obtain gradation. To produce great effects. When a higher resolution is achieved, application to a contact image sensor for color reading becomes easier. Of course, the effect is great also for reduction of power supply voltage, reduction of current consumption, and improvement of reliability. In addition, since it can be manufactured by a low-temperature process, the length of the contact-type image sensor chip can be increased, and a single chip can realize a reading device for large facsimile such as A4 size or A3 size. Therefore, it is possible to avoid troublesome techniques such as double splicing of sensor chips and unreliable technology, and the mounting yield is improved.

Not only a quartz substrate and a glass substrate, but also a sapphire substrate or MgO.Al ₂ O ₃ , BP, CaF ₂
And other crystalline insulating substrates.

Although a thin film transistor has been described as an example, an element using a thin film such as a bipolar transistor or a heterojunction bipolar transistor is also applicable.
The present invention can be applied. Further, the present invention can be applied to an element using the SOI technology such as a three-dimensional device.

The present invention has been described by taking the solid phase growth method as an example.
The present invention can also be applied to the case where a thin-film semiconductor device is manufactured using a poly-Si thin film formed by a VD method or another method, for example, an EB evaporation method, a sputtering method, or an MBE method. Further, it can be applied to a general MOS type semiconductor device.

[Brief description of the drawings]

FIGS. 1A and 1B are a plan view and a structural cross-sectional view of an active matrix type liquid crystal display device according to an embodiment of the present invention.

FIGS. 2A to 2E are process cross-sectional views illustrating a method for manufacturing an active matrix liquid crystal display device of the present invention. However, FIG. 1A is a cross-sectional view taken along a line AB in FIG.

FIGS. 3A to 3E are process cross-sectional views illustrating a method for manufacturing an active matrix liquid crystal display device of the present invention. However, FIG. 3A is continued from FIG. 2E.

FIGS. 4A to 4C are process cross-sectional views illustrating a method for manufacturing an active matrix liquid crystal display device of the present invention. However, FIG. 4 (a) is continued from FIG. 3 (e).

FIG. 5 is a structural sectional view of a thin film transistor and a scanning line used in a conventional active matrix type liquid crystal display device.

[Explanation of symbols]

 1-2 Thin film with low etching rate in upper layer 1-3 Thin film with high etching rate in lower layer 1-7 Source line 1-8 Pixel electrode 1-10 Source region 1-11 Drain region 1-12 Interlayer insulating film 1- Reference Signs List 13 Polycrystalline silicon / silicide two-layer film 1-14 Lower insulating film 1-15 Offset length 2-1 Insulating transparent substrate 2-3 Polycrystalline silicon thin film 2-4 Gate insulating film 2-5 Lower etching rate of lower layer Thin film 2-6 Upper thin film with small etching rate 2-7 Resist mask 2-8 Offset length 2-9 Source region 2-10 Drain region 2-12 Lower insulating film 2-13 Interlayer insulating film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G02F 1/1368 H01L 29/786

Claims (2)

(57) [Claims] 1. A transistor having a two-layered gate electrode on a source / drain active region with a gate insulating film interposed therebetween, wherein the two-layered film is a lower layered film under the same etching conditions. A thin film having a higher etching rate than the etching rate of the upper layer film, and the upper layer film is overhanging from the lower layer film. 2. A step of forming a gate insulating film on an active region serving as a source / drain; a step of forming a first thin film serving as a first gate electrode on the gate insulating film; Forming a second thin film to be a second gate electrode, and simultaneously etching the first thin film and the second thin film to form the first gate electrode and the second gate electrode, The etching rate of the first thin film is
A method for manufacturing a transistor, wherein the etching rate is higher than an etching rate of the second thin film.