KR100268860B1 - Manufacturing method of a semiconductor device - Google Patents

Manufacturing method of a semiconductor device Download PDF

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Publication number
KR100268860B1
KR100268860B1 KR1019920019345A KR920019345A KR100268860B1 KR 100268860 B1 KR100268860 B1 KR 100268860B1 KR 1019920019345 A KR1019920019345 A KR 1019920019345A KR 920019345 A KR920019345 A KR 920019345A KR 100268860 B1 KR100268860 B1 KR 100268860B1
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Prior art keywords
gate
oxide film
low
substrate
density
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KR1019920019345A
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Korean (ko)
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KR940010381A (en
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이창재
김재정
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to forming a shallow junction by improving the short channel effect. CONSTITUTION: A gate insulating film(3), a gate(4) and a cap gate oxide film(5) are formed on a substrate(1). A low-density source region(2a) and a low-density drain region(2b) are formed by injecting a low-density ion. By forming an oxide film on the whole structure and performing an etch-back process, a sidewall of the oxide film is formed on the side surfaces of the gate(4) and the cap gate oxide film(5). An amorphous silicon film is formed on the whole structure by the low-pressure chemical vapor deposition, and a silicon ion is injected into the amorphous silicon film. By injecting a high-density ion into the substrate and performing a heat treatment, a high-density source/drain region is formed.

Description

반도체 장치의 제조방법Manufacturing Method of Semiconductor Device

제1도는 종래의 기술에 따른 반도체장치 제조시의 접합공정도.1 is a joining process diagram in manufacturing a semiconductor device according to the prior art.

제2도는 본 발명에 따라 반도체장치 제조시의 접합공정도.2 is a joining process diagram in manufacturing a semiconductor device according to the present invention.

〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>

1 : 기판 2a : 저농도 소오스 영역1 Substrate 2a Low Concentration Source Region

2b : 저농도 드레인 영역 3 : 게이트절연막2b: low concentration drain region 3: gate insulating film

4 : 게이트 5 : 캡게이트산화막4 gate 5 capgate oxide film

6 : 산화막측벽 7 : 비정질실리콘막6 oxide film side wall 7 amorphous silicon film

8 : 비정질화된층 9 : 고농도 소오스/드레인 영역8: amorphous layer 9: high concentration source / drain region

본 발명은 반도체 장치의 제조방법에 관한것으로서, 특히 고집적 반도체 기억장치의 제조에 적당하도록한 MOS형 트랜지스터의 소오스/드레인 접합을 얇게(Shallow)하는 접합형성 방법에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a junction for thinning a source / drain junction of a MOS transistor suitable for manufacturing a highly integrated semiconductor memory device.

일반적으로 고집적도를 요하는 반도체 장치에서는 게이트 길이를 짧게하는 것이 필요하다.In general, in a semiconductor device requiring high integration, it is necessary to shorten the gate length.

그러나 게이트 길이가 줄어 들수록 핫 캐리어 발생에 의한 누설전류의 증가, 게이트산화막의 신뢰성 저하 등의 현상이 발생하는 문제점이 있다.However, as the gate length decreases, a phenomenon such as an increase in leakage current due to hot carrier generation and a decrease in reliability of the gate oxide film occurs.

종래에는 이러한 문제를 해결하는 한 방안으로서 접합깊이를 얕게하는 것을 채택하고 있다.Conventionally, as one solution to this problem, a shallow depth of joint has been adopted.

제 1 도는 반도체장치 제조시 접합형성의 공정도를 도시하고 있다.1 shows a process diagram of junction formation in the manufacture of a semiconductor device.

종래의 MOS소자 제조공정을 제 1 도를 참조하여 간략히 설명한다.A conventional MOS device fabrication process will be briefly described with reference to FIG.

1단계(제 1 도(a))로, 실리콘기판(1)상에 필드산화막을 성장시켜서 액티브 영역과 게이트 산화막을 정의하고, 그 위에 폴리실리콘층(4)과 캡게이트산화막(5)을 형성하고 패터닝하여 게이트를 형성한다.In step 1 (a), a field oxide film is grown on a silicon substrate 1 to define an active region and a gate oxide film, and a polysilicon layer 4 and a capgate oxide film 5 are formed thereon. And patterning to form a gate.

2단계(제 1 도 (b))에서는, (a)도의 층상구조를 소오스/드레인을 형성하기 위해 저농도의 불순물을 이온주입한 다음, 게이트 측벽에 SiO2를 증착하고 에치백하여 측벽산화막(6a,6b)을 형성한다.Step 2 (FIG. 1 (b)) in, (a) separate the layered structure in the ion implantation of a low concentration of impurities to form the source / drain, and then to the gate sidewall etching back the SiO 2 to the deposition and the side wall oxide film (6a , 6b).

3단계(제 1 도 (c))에서는 단축채널효과(Short Channel Effect)를 해결하기 위해 얇은 접합형성 기법중의 하나인 Si이온이나 Ge이온을 주입하여 실리콘 기판의 비정질화를 유도하는 단계이다.In the third step (FIG. 1C), in order to solve the short channel effect, Si or Ge ions, which are one of thin junction formation techniques, are injected to induce amorphous phase of the silicon substrate.

도핑을 위한 불순물을 이온주입하는 방식으로 먼저 실리콘 도는 Ge이온을 1.0 x 1013내지 1.0 x 105개의 범위에서 주입에너지 50~100Kev범위를 주입하여 실리콘 기판을 비정질화 한다.By implanting impurities for doping, the silicon substrate is amorphous by first implanting silicon or Ge ions in a range of 1.0 x 10 13 to 1.0 x 10 5 with an implantation energy of 50 to 100 Kev.

그후 도팬트를 이온주입하여, 이온주입시에 발생하는 도핑 프로파일의 테일(tail)이 느러지는 채널링 현상을 억제한다.Thereafter, the dopant is implanted to suppress a channeling phenomenon in which the tail of the doping profile that occurs during ion implantation is slowed.

제 4 단계(제 1 도 (d))에서는 열처리를 행하여 도팬트를 활성화시킨다.In the fourth step (FIG. 1 (d)), heat treatment is performed to activate the dopant.

제 4 단계 이후의 공정은 일반적인 MOS소자 제조방법으로 진행된다.After the fourth step, the process proceeds to a general MOS device manufacturing method.

이와같은 방식의 MOS트랜지스터의 제조방법의 단점은 실리콘 기판상에 직접 실리콘(Si) 또는 게르마늄(Ge)의 이온을 주입하여 비정질화 시킴으로서, 열처리후 결정결함이 쉽게 발생되어 접합의 전기적 특성이 불량하며, 또한 비정질실리콘 기판이 열처리시 도팬트의 확산이 증대되어 접합을 얕게 조정하여 형성하는 것이 불가능하다.The disadvantage of the manufacturing method of the MOS transistor in this manner is that by implanting ions of silicon (Si) or germanium (Ge) directly on the silicon substrate to amorphize it, crystal defects are easily generated after heat treatment, resulting in poor electrical characteristics of the junction. In addition, when the amorphous silicon substrate is heat-treated, the diffusion of the dopant is increased, so that it is impossible to form a shallow adjustment of the junction.

본 발명의 목적은 이와 같은 종래의 문제점을 개선하기 위한 것으로서, 고집적 기억장치에서 단축채널 효과를 개선하여 얕은 접합형성 방법을 제공하는데 있다.SUMMARY OF THE INVENTION An object of the present invention is to improve such a conventional problem, and to provide a shallow junction forming method by improving a short channel effect in a high density memory device.

이하에서는 첨부도면을 참조한 실시예의 설명을 통하여 본 발명의 내용을 상술한다.Hereinafter, the content of the present invention will be described in detail with reference to the accompanying drawings.

제 2 도는 본 발명의 목적을 달성하는 집합형성의 공정도이다.2 is a process chart of aggregation to achieve the object of the present invention.

이러한 공정의 1단계는 제 2 도(a)에 도시된 것과 같이, 기판(1)상에 게이트절연막(3), 게이트(4) 및 캡게이트산화막(5)을 공지의 방법으로 형성한다. 이후에 저농도 이온주입을 실시하여 저농도 소오스영역(2a) 및 저농도 드레인영역(2b)을 형성한다.In one step of this process, as shown in FIG. 2A, a gate insulating film 3, a gate 4 and a capgate oxide film 5 are formed on a substrate 1 by a known method. Thereafter, low concentration ion implantation is performed to form the low concentration source region 2a and the low concentration drain region 2b.

2단계는 제 2 도(b)에 도시된 것과 같이 상기 결과물 전면에 산화막을 형성한 후 에치백하여 상기 게이트(4) 및 캡게이트산화막(5)측면에 산화막측벽(6)을 형성한다. 이어서 전면에 비정질실리콘막(7)을 500 ~ 1500Å의 두께로 저온화학증착법(LPCVD)에 의해 형성한다. 이어서 실리콘이온을 저에너지로 주입하여 상기 비정질실리콘막(7)을 완전히 비정질화시킨다.In the second step, as shown in FIG. 2 (b), an oxide film is formed on the entire surface of the resultant and then etched back to form an oxide film side wall 6 on the side of the gate 4 and the capgate oxide film 5. Subsequently, an amorphous silicon film 7 is formed on the entire surface by low temperature chemical vapor deposition (LPCVD) to a thickness of 500 to 1500 kPa. Subsequently, silicon ions are implanted at low energy to completely amorphous the amorphous silicon film 7.

이때 상기 비정질실리콘막(7)과 기판(1)의 계면 아래에 약 100-500Å의 두께로 비정질화된층(8)이 형성된다.At this time, an amorphous layer 8 is formed to a thickness of about 100-500 kV under the interface between the amorphous silicon film 7 and the substrate 1.

제 3 단계는 제 2 도(c)에 도시된 것과 같이 고농도 이온주입을 실시하고 열처리를 실시하여 고농도 소오스/드레인영역(9)을 형성한다.In the third step, as shown in FIG. 2C, high concentration ion implantation and heat treatment are performed to form a high concentration source / drain region 9.

제 4 단계는 제 2 도(d)에 도시된 것과 같이 상기 비정질실리콘막(7)을 제거하여 얕은 접합의 소오스/드레인 영역을 가지는 트랜지스터가 완성된다. 본 발명에 따른 접합방법의 효과로는, 실리콘 이온주입을 실리콘기판에 직접하지 않음으로 열처리시 결정결함을 최소화할 수 있고, 기판으로의 도판트 확산을 방지할 수 있어서 접합깊이를 더욱 얕게 할 수 있으며 원하는 농도의 프로파일 제어를 용이하게 할 수 있다.In the fourth step, as shown in FIG. 2 (d), the amorphous silicon film 7 is removed to complete a transistor having a shallow junction source / drain region. As an effect of the bonding method according to the present invention, the crystal defects during the heat treatment can be minimized by not injecting silicon ions directly into the silicon substrate, and the diffusion of the dopant into the substrate can be prevented, so that the depth of bonding can be made shallower. And facilitating profile control of the desired concentration.

Claims (1)

기판상에 게이트절연막, 게이트를 차례로 형성하는 단계와; 상기 게이트측벽에 절연막측벽을 형성하는 단계와; 상기 게이트 및 상기 절연막측벽을 포함한 상기 기판상에 비정질실리콘막을 증착하는 단계와, 상기 비정질실리콘막에 실리콘 이온을 주입하는 단계와, 상기 게이트의 양측의 상기 기판에 불순물 이온을 주입하여 소오스/드레인 영역을 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체장치의 제조방법.Sequentially forming a gate insulating film and a gate on the substrate; Forming an insulating film side wall on the gate side wall; Depositing an amorphous silicon film on the substrate including the gate and the insulating film sidewalls, implanting silicon ions into the amorphous silicon film, and implanting impurity ions into the substrate on both sides of the gate to form a source / drain region Forming the method comprising the step of forming a semiconductor device.
KR1019920019345A 1992-10-21 1992-10-21 Manufacturing method of a semiconductor device KR100268860B1 (en)

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KR100321925B1 (en) * 1998-11-26 2002-10-25 삼성전자 주식회사 Manufacturing method of thin film transistor substrate for liquid crystal display device using four masks and thin film transistor substrate for liquid crystal display device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02244715A (en) * 1989-03-17 1990-09-28 Kawasaki Steel Corp Manufacture of semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02244715A (en) * 1989-03-17 1990-09-28 Kawasaki Steel Corp Manufacture of semiconductor device

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