KR19980048959A - Field effect thin film transistor and its manufacturing method - Google Patents
Field effect thin film transistor and its manufacturing method Download PDFInfo
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- KR19980048959A KR19980048959A KR1019960067614A KR19960067614A KR19980048959A KR 19980048959 A KR19980048959 A KR 19980048959A KR 1019960067614 A KR1019960067614 A KR 1019960067614A KR 19960067614 A KR19960067614 A KR 19960067614A KR 19980048959 A KR19980048959 A KR 19980048959A
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- 230000005669 field effect Effects 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000010409 thin film Substances 0.000 title claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 54
- 239000012535 impurity Substances 0.000 claims description 20
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 18
- 238000005468 ion implantation Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 239000011229 interlayer Substances 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 239000010410 layer Substances 0.000 claims description 6
- 238000001953 recrystallisation Methods 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 장치 제조방법Semiconductor device manufacturing method
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
종래에는 오프 상태에서 드레인 누설 전류가 큰 문제점이 있었으며, 이러한 문제점을 고려하여 드레인 영역을 즐이면 추가적인 직렬 저항 증가를 초래하여 온 상태의 전류를 감소시키는 문제점이 있었음.Conventionally, the drain leakage current in the off state has a large problem, and in consideration of this problem, the drain region enjoys the problem of reducing the current in the on state by causing an additional series resistance increase.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
본 발명은 플로팅 게이트를 형성함으로써 드레인 누설 전류를 줄이고, 높은 온/오프 전류비 특성을 가진 전계 효과 박막트랜지스터 및 그 제조방법을 제공하고자 함.An object of the present invention is to reduce the drain leakage current by forming a floating gate, to provide a field effect thin film transistor having a high on / off current ratio characteristics and a method of manufacturing the same.
4. 발명의 중요한 용도4. Important uses of the invention
고집적 반도체 장치 특히, SRAM 제조에 이용됨.Highly integrated semiconductor devices, especially in the manufacture of SRAMs.
Description
본 발명은 전계 효과 트랜지스터 및 그 제조방법에 관한 것으로, 특히 고집적 반도체 장치에서 로드 저항에서 사용되는 높은 온/오프 전류비 특성을 가진 전계 효과 박막트랜지스터 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method of manufacturing the same, and more particularly, to a field effect thin film transistor having a high on / off current ratio characteristic used in a load resistance in a highly integrated semiconductor device and a method of manufacturing the same.
이하, 첨부된 도면 도 1A 내지 도 1D를 참조하여 종래 기술 및 그 문제점을 살펴본다.Hereinafter, with reference to the accompanying drawings Figures 1A to 1D looks at the prior art and its problems.
먼저, 도 1A에 도시된 바와 같이 실리콘 기판(10) 상에 SOI(Silicon On Insulator) 구조 형성을 위한 매몰 산화막(11)을 증착한 후, 그 상부에 비정질 실리콘막(12)을 증착하고, 비정질 실리콘막(12) 상에 n-채널 형성을 위한 이온주입을 실시한다.First, as shown in FIG. 1A, a buried oxide film 11 for forming a silicon on insulator (SOI) structure is deposited on a silicon substrate 10, and then an amorphous silicon film 12 is deposited thereon, and an amorphous film is deposited thereon. Ion implantation is performed on the silicon film 12 to form an n − channel.
다음으로, 도 1B에 도시된 바와 같이 전체구조 상부에 게이트 산화막(13)을 형성하고, 그 상부에 고농도의 n형 불순물로 도핑된 폴리 실리콘막을 증착한 후, 게이트 전극 형성을 위한 마스크를 사용하여 게이트 산화막(13) 및 폴리 실리콘막을 식각함으로써 게이트 전극(14)을 형성하고, 마스크를 제거한다.Next, as shown in FIG. 1B, the gate oxide film 13 is formed over the entire structure, and a polysilicon film doped with a high concentration of n-type impurities is deposited thereon, and then a mask for forming a gate electrode is used. By etching the gate oxide film 13 and the polysilicon film, the gate electrode 14 is formed, and the mask is removed.
이어서, 도 1C에 도시된 바와 같이 소오스/드레인 형성을 위한 이온주입 마스크(15)를 드레인 오프세트(offset)가 형성되도록 게이트 전극(14) 상부 및 드레인측 측벽 부위에 형성하고, P+소오스/드레인 이온주입을 실시한다.Subsequently, as shown in FIG. 1C, an ion implantation mask 15 for source / drain formation is formed on the upper side of the gate electrode 14 and the drain side sidewall so that a drain offset is formed, and P + source / drain is formed. Drain ion implantation is performed.
끝으로, 도 1D에 도시된 바와 같이 이온주입 마스크(15)를 제거하고, 열처리를 실시한다.Finally, as shown in FIG. 1D, the ion implantation mask 15 is removed and heat treatment is performed.
미설명 도면 부호 16은 p+소오스, 17은 p+드레인, 18은 n-채널, A는 드레인 오프세트 영역을 각각 나타낸 것이다.Reference numeral 16 denotes a p + source, 17 denotes a p + drain, 18 denotes an n - channel, and A denotes a drain offset region.
상기와 같은 드레인 오프세트 구조 또는 흔히 사용되는 저농도 도핑 드레인(LDD) 구조의 종래의 전계 효과 트랜지스터의 가장 큰 문제점은 오프(off) 상태에서 누설 전류가 크다는 것이다. 이러한 누설 전류는 드레인 쪽에서 높은 전계에 의해 폴리 실리콘막의 결정립계(grain boundary)를 따라 전계 방사(field emission)이 일어나기 때문이다.The biggest problem with conventional field effect transistors of such drain offset structures or commonly used low concentration doped drain (LDD) structures is the large leakage current in the off state. This leakage current is because field emission occurs along the grain boundary of the polysilicon film due to a high electric field at the drain side.
이러한 종래의 전계 효과 트랜지스터 구조 자체에서도 드레인 영역을 줄임으로써 누설 전류를 줄일 수 있지만, 추가적인 직렬 저항의 증가를 초래하여 온(ON) 상태에서의 전류까지 줄이는 문제점이 있었다.In the conventional field effect transistor structure itself, the leakage current can be reduced by reducing the drain region, but there is a problem of reducing the current in the ON state by causing an additional series resistance increase.
따라서, 고집적 고밀도를 가지는 SRAM등에서 요구되는 높은 온/오프 전류비를 가지는 소자를 형성하기 어려운 문제점이 있었다.Accordingly, there is a problem in that it is difficult to form a device having a high on / off current ratio required in an SRAM having a high integration density.
본 발명은 플로팅 게이트를 형성함으로써 드레인 누설 전류를 줄이고, 높은 온/오프 전류비 특성을 가진 전계 효과 박막트랜지스터 및 그 제조방법을 제공하는데 그 목적이 있다.An object of the present invention is to reduce the drain leakage current by forming a floating gate, to provide a field effect thin film transistor having a high on / off current ratio characteristics and a method of manufacturing the same.
도 1A도 내지 도 1D는 종래 기술에 따른 전계 효과 박막트랜지스터 제조 공정도,Figure 1a to 1d is a field effect thin film transistor manufacturing process chart according to the prior art,
도 2A도 내지 도 2D는 본 발명의 일실시예에 따른 전계 효과 박막트랜지스터 제조 공정도.2A to 2D are schematic diagrams of a field effect thin film transistor manufacturing process according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
10,20 : 실리콘 기판11,21 : 매몰 산화막10,20 silicon substrate 11,21 buried oxide film
12,24 : 비정질 실리콘막13,25 : 게이트 산화막12,24 amorphous silicon film 13,25 gate oxide film
14,26a : 게이트 전극15 : 이온주입 마스크14, 26a: gate electrode 15: ion implantation mask
16,29a : p+소오스17,29b : p+드레인16,29a: p + source 17,29b: p + drain
18,24a : n-채널A : 드레인 오프세트 영역18,24a: n - channel A: drain offset region
22 : 플로팅 게이트23 : 층간 절연막22: floating gate 23: interlayer insulating film
27 : 스페이서 산화막28a : p-소오스27: a spacer oxide film 28a: p - source
28b : p-드레인M : 게이트 형성을 위한 마스크28b: p - drain M: mask for gate formation
상기와 같은 목적을 달성하기 위하여 본 발명은 저농도 제1 불순물 채널, 저농도 제2 불순물 소오드/드레인 및 고농도 제2 불순물 소오스/드레인을 구비하는 활성 영역과, 상기 활성 영역 상부에 형성된 게이트 절연막 및 게이트 전극을 구비하는 전계 효과 박막트랜지스터에 있어서, 상기 활성 영역 하부에 상기 활성 영역과 절연막을 사이에 두고 형성된 고농도의 제2 불순물이 도핑된 플로팅 게이트와, 상기 플로팅 게이트를 지지하기 위한 매몰 산화막 및 반도체 기판을 더 구비하여 이루어진다.In order to achieve the above object, the present invention provides an active region including a low concentration first impurity channel, a low concentration second impurity source / drain, and a high concentration second impurity source / drain, and a gate insulating film and a gate formed on the active area. A field effect thin film transistor having an electrode, comprising: a floating gate doped with a high concentration of a second impurity formed between the active region and an insulating layer beneath the active region, a buried oxide film and a semiconductor substrate for supporting the floating gate It is further provided with.
또한, 본 발명은 반도체 기판 상부에 매몰 산화막을 형성하는 단계; 상기 매몰 산화막 상부에 고농도의 제1 불순물이 도핑된 플로팅 게이트를 형성하고, 층간 절연막을 형성하는 단계; 상기 층간 절연막 상부에 활성 영역 형성을 위한, 저농도의 제2 불순물이 도핑된 비정질 실리콘막을 형성하고, 이를 재결정화하는 단계; 재결정화된 상기 비정질 실리콘막 상부에 게이트 절연막 및 게이트 전극을 형성하는 단계; 재결정화된 상기 비정질 실리콘막 상에 고농도의 제1 불순물을 이온주입하는 단계를 포함하여 이루어진다.In addition, the present invention comprises the steps of forming a buried oxide film on the semiconductor substrate; Forming a floating gate doped with a high concentration of first impurities on the buried oxide film and forming an interlayer insulating film; Forming an amorphous silicon film doped with a low concentration of a second impurity to form an active region on the interlayer insulating film, and recrystallizing the amorphous silicon film; Forming a gate insulating film and a gate electrode on the recrystallized amorphous silicon film; And implanting a high concentration of the first impurity on the recrystallized amorphous silicon film.
이하, 첨부된 도면 도 2A 내지 도 2D를 참조하여 본 발명의 일실시예를 상술한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings, FIGS. 2A to 2D.
먼저, 도 2A에 도시된 바와 같이 실리콘 기판(20) 상부에 매몰 산화막(21)을 증착하고, 그 상부에 폴리 실리콘막을 증착하고, 고농도의 p형 불순물을 이온주입하여 플로팅 게이트(22)를 형성한다. 계속하여, 전체구조 상부에 층간 절연막(23)을 증착하고, 그 상부에 비정질 실리콘막(24)을 증착한 다음, n-채널 형성을 위한 이온주입을 실시하고, 비정질 실리콘막(24)의 재결정화를 실시한다. 계속하여, 전체구조 상부에 게이트 산화막(25)을 증착하고, 그 상부에 폴리 실리콘막(26)을 증착한 다음, 폴리 실리콘막(26) 상에 고농도의 p형 불순물을 이온주입하고, 그 상부에 게이트 전극 형성을 위한 마스크(M)를 형성한다.First, as shown in FIG. 2A, a buried oxide film 21 is deposited on the silicon substrate 20, a polysilicon film is deposited on the silicon substrate 20, and a floating gate 22 is formed by ion implantation of a high concentration of p-type impurities. do. Subsequently, an interlayer insulating film 23 is deposited over the entire structure, an amorphous silicon film 24 is deposited over the entire structure, ion implantation for n − channel formation is performed, and recrystallization of the amorphous silicon film 24 is performed. Conduct anger. Subsequently, a gate oxide film 25 is deposited over the entire structure, a polysilicon film 26 is deposited over the entire structure, and a high concentration of p-type impurities are ion implanted onto the polysilicon film 26, and the upper portion thereof. A mask M for forming a gate electrode is formed on the substrate.
여기서, 상기한 층간 절연막(23)은 저압 화학 기상 증착 방식(LPCVD)을 사용하여 약 250Å 내지 약 500Å 두께로 형성하며, 상기한 비정질 실리콘막(24)은 약 1000Å 내지 약 2000Å 두께로 형성하며, 재결정화 공정은 Ar 분위기 및 약 500℃ 내지 약 600℃ 온도 범위에서 약 20분 동안 이루어진다.Here, the interlayer insulating film 23 is formed to a thickness of about 250 kPa to about 500 kPa using low pressure chemical vapor deposition (LPCVD), and the amorphous silicon film 24 is formed to a thickness of about 1000 kPa to about 2000 kPa, The recrystallization process takes about 20 minutes in an Ar atmosphere and a temperature range of about 500 ° C to about 600 ° C.
이어서, 도 2B에 도시된 바와 같이 마스크(M)를 식각 장벽으로하여 폴리 실리콘막(26)을 선택적 식각하여 게이트 전극(26a)을 형성하고, 마스크(M)를 제거한다. 계속하여, 비정질 실리콘막(24) 상에 저농도 도핑 드레인(LDD) 구조를 형성하기 위한 p-이온주입을 실시한다.Subsequently, as shown in FIG. 2B, the polysilicon layer 26 is selectively etched using the mask M as an etch barrier to form the gate electrode 26a, and the mask M is removed. Subsequently, p − ion implantation is performed to form a low concentration doped drain (LDD) structure on the amorphous silicon film 24.
다음으로, 도 2C에 도시된 바와 같이 전체구조 상부에 저농도 도핑 드레인 구조 형성을 위한 스페이서 형성용 산화막을 증착하고, 이를 전면성 식각하여 게이트 전극(26a) 측벽에 스페이서 산화막(27)을 형성한 다음, 비정질 실리콘막(24) 상에 고농도의 P형 불순물을 이온주입한다.Next, as shown in FIG. 2C, an oxide film for forming a spacer for forming a low concentration doped drain structure is deposited on the entire structure, and the spacer oxide film 27 is formed on the sidewall of the gate electrode 26a by etching the entire surface. A high concentration of P-type impurities are ion implanted onto the amorphous silicon film 24.
끝으로, 도 2D는 열처리를 실시한 후 전계 효과 트랜지스터가 형성을 완료한 상태를 나타낸 것이다.Lastly, FIG. 2D shows a state in which the field effect transistor is completed after heat treatment.
미설명 도면부호 24a는 n-채널, 28a는 p-소오스, 28b는 p-드레인, 29a는 n+소오스, 29b는 p+드레인을 각각 나타낸 것이다.Reference numeral 24a denotes an n - channel, 28a denotes a p - source, 28b denotes a p - drain, 29a denotes an n + source, and 29b denotes a p + drain, respectively.
상기한 본 발명의 일실시에에 나타난 본 발명의 전계 효과 박막트랜지스터는 폴리 실리콘막에 의한 플로팅 게이트를 형성함으로써 오프(Off) 상태에서의 누설전류와 킹크 효과(kink effect)를 효과적으로 억제하면서 매우 양호한 온(on) 상태에서의 전류를 얻을 수 있다.The field effect thin film transistor of the present invention shown in one embodiment of the present invention is very good while effectively suppressing leakage current and kink effect in the off state by forming a floating gate by a polysilicon film. The current in the on state can be obtained.
오프(off) 상태(Vd=Vdd, Vg=0)에서, 플로팅 게이트에 의해 드레인과 게이트 사이의 전계가 감소하게 되어 누설 전류가 감소하며, 온(on) 상태(Vd=Vdd, Vg0)에서, 플로팅 게이트가 축적층(accumulation layer) 역할을 함으로써 소오드/드레인 간의 직렬 저항을 감소 시키게 되어 온(on) 전류가 증가하게 된다.In the off state (V d = V dd , V g = 0), the floating gate causes the electric field between the drain and the gate to decrease, reducing the leakage current, and the on state (V d = V dd). , V g 0), the floating gate acts as an accumulation layer, reducing the series resistance between the cathode and the drain, thereby increasing the on current.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기한 바와 같이 본 발명은 플로팅 게이트의 역할로 인하여 드레인측의 누설 전류를 감소시키는 효과가 있으며, 또한 높은 온/오프 전류비를 가진 전계 효과 박막트랜지스터 제조를 가능하게 함으로써 차세대 고집적 반도체 장치 제조에 기여하는 효과가 있다.As described above, the present invention has the effect of reducing the leakage current at the drain side due to the role of the floating gate, and also contributes to the fabrication of the next generation highly integrated semiconductor device by enabling the production of field effect thin film transistors having a high on / off current ratio. It is effective.
Claims (8)
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| WO2009099732A1 (en) * | 2008-02-06 | 2009-08-13 | Micron Technology, Inc. | Memory cells, methods of forming memory cells, and methods of forming programmed memory cells |
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| WO2009099732A1 (en) * | 2008-02-06 | 2009-08-13 | Micron Technology, Inc. | Memory cells, methods of forming memory cells, and methods of forming programmed memory cells |
| US7883931B2 (en) | 2008-02-06 | 2011-02-08 | Micron Technology, Inc. | Methods of forming memory cells, and methods of forming programmed memory cells |
| US8189375B2 (en) | 2008-02-06 | 2012-05-29 | Micron Technology, Inc. | Methods of forming memory cells and methods of forming programmed memory cells |
| US8320173B2 (en) | 2008-02-06 | 2012-11-27 | Micron Technology, Inc. | Methods of forming programmed memory cells |
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