WO2019028934A1 - Low temperature polysilicon thin film transistor and preparation method therefor - Google Patents

Low temperature polysilicon thin film transistor and preparation method therefor Download PDF

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WO2019028934A1
WO2019028934A1 PCT/CN2017/098337 CN2017098337W WO2019028934A1 WO 2019028934 A1 WO2019028934 A1 WO 2019028934A1 CN 2017098337 W CN2017098337 W CN 2017098337W WO 2019028934 A1 WO2019028934 A1 WO 2019028934A1
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layer
polysilicon
active layer
polysilicon active
thin film
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PCT/CN2017/098337
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French (fr)
Chinese (zh)
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肖东辉
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武汉华星光电技术有限公司
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Priority to US15/575,107 priority Critical patent/US10516058B2/en
Publication of WO2019028934A1 publication Critical patent/WO2019028934A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • the present invention relates to a manufacturing process of a semiconductor device, and more particularly to a low temperature polysilicon thin film transistor and a method of fabricating the same.
  • the flat panel display device has many advantages such as thin body, power saving, no radiation, and has been widely used.
  • the conventional flat panel display device mainly includes a liquid crystal display (LCD) and an organic light emitting display (OLED).
  • Thin Film Transistors (TFTs) are an important part of flat panel display devices and can be formed on glass substrates or plastic substrates, and are commonly used as light-emitting devices and driving devices such as LCDs and OLEDs.
  • LTPS thin film transistors have many advantages. For example, LTPS thin film transistors have high electron mobility, which not only can effectively reduce the area of thin film transistors, increase the aperture ratio, but also improve the display brightness while reducing the overall power consumption. For example, a higher electron mobility can integrate part of the driving circuit on the substrate, reduce the driving integrated circuit IC, greatly improve the reliability of the display panel, and greatly reduce the manufacturing cost. Therefore, LTPS thin film transistors have gradually become a research hotspot in the field of display technology.
  • the structure of the existing LTPS thin film transistor mainly comprises a base substrate and a polysilicon active layer, a gate insulating layer, a gate electrode, a source electrode and a drain electrode which are sequentially disposed on the base substrate, and the source electrode and the drain electrode pass through the via hole Electrically connected to the polysilicon active layer.
  • the gate insulating layer covering the active layer of the polysilicon is formed by a deposition process, the defect density of the gate insulating layer is large, and carriers in the active layer of the polysilicon are easily diffused into the gate insulating layer, forming a comparison Large leakage current increases the instability of the electrical properties of LTPS thin film transistors. Therefore, the prior art has yet to be improved and developed.
  • the present invention provides a low temperature polysilicon thin film transistor and a method of fabricating the same, which can reduce the defect density of the interface between the active layer of the polysilicon and the gate insulating layer, and reduce the leakage of the thin film transistor.
  • the current makes the thin film transistor have good and stable electrical properties.
  • a method for preparing a low-temperature polysilicon thin film transistor comprising: sequentially forming a polysilicon active layer and a gate insulating layer covering the polysilicon active layer on a substrate; applying an ion implantation process, wherein the polysilicon has Nitrogen ions are implanted into the surface of the source layer facing the gate insulating layer to form an ion implantation layer; the ion implantation layer is recrystallized by a high temperature annealing process, and the polysilicon active layer and the gate insulating layer are A silicon nitride spacer layer is formed between them.
  • the preparation method comprises the steps of:
  • the preparation method comprises the steps of:
  • the step S1 specifically includes: S11, sequentially depositing a buffer layer and an amorphous silicon film layer on the substrate substrate; S12, applying an excimer laser annealing process to form the amorphous silicon film layer to form a polysilicon film Floor.
  • the buffer layer comprises a silicon nitride layer and a silicon oxide layer sequentially formed on the substrate substrate.
  • the method further comprises the steps of: S0, preparing a patterned light-shielding unit on the substrate substrate, wherein the light-shielding unit is for preparing a patterned polysilicon active layer formed in a subsequent process.
  • the polysilicon active layer is doped by an ion implantation process, so that the polysilicon active layer is sequentially formed from the middle to the both ends. a dummy region, a lightly doped region, and a heavily doped region; wherein the source electrode is electrically connected to a heavily doped region of one end of the polysilicon active layer, and the drain electrode is electrically connected to the polysilicon A heavily doped region at the other end of the source layer.
  • the gate insulating layer is a silicon oxide layer or a silicon nitride layer or a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
  • the present invention also provides a low temperature crystalline silicon thin film transistor comprising a polysilicon active layer, a gate insulating layer, a gate electrode, a source electrode and a drain electrode sequentially disposed on a base substrate, wherein the polysilicon active layer and The connection interface between the gate insulating layers is formed with a silicon nitride spacer layer, and the silicon nitride spacer layer and the polysilicon active layer are integrally connected to each other.
  • the silicon nitride spacer layer is passed through an ion implanter on the surface of the polysilicon active layer Formed by a high temperature annealing process, the gate insulating layer is formed on the polysilicon active layer by a deposition process, and a defect density of the silicon nitride spacer layer is smaller than a defect density of the gate insulating layer.
  • the low-temperature polysilicon thin film transistor and the preparation method thereof are provided in the embodiment of the present invention, and a silicon nitride spacer layer is formed at a connection interface between the polysilicon active layer and the gate insulating layer by an ion implantation process and a high temperature annealing process, the nitrogen
  • the silicon spacer layer can reduce the defect density of the connection interface between the polysilicon active layer and the gate insulating layer, reduce the leakage current of the thin film transistor, increase the breakdown voltage, and make the thin film transistor have good and stable electrical properties.
  • FIG. 1 is a schematic structural view of a low temperature polysilicon thin film transistor according to Embodiment 1 of the present invention.
  • Figure 2 is an enlarged schematic view of a portion A in Figure 1;
  • 3a-3k are exemplary illustrations of device structures obtained in accordance with respective steps in a method of fabricating a low temperature polysilicon thin film transistor according to Embodiment 2 of the present invention.
  • 4a to 4f are exemplary illustrations of device structures obtained in accordance with respective steps in a method of fabricating a low temperature polysilicon thin film transistor according to a third embodiment of the present invention.
  • the present embodiment provides a low-temperature crystalline silicon thin film transistor.
  • the low-temperature crystalline silicon thin film transistor includes a polysilicon active layer 2, a gate insulating layer 3, and a gate electrode which are sequentially disposed on a base substrate 1. 4.
  • Source electrode 5a and drain electrode 5b are sequentially disposed on a base substrate 1.
  • a connection interface between the polysilicon active layer 2 and the gate insulating layer 3 is formed with a silicon nitride spacer layer 6, and the silicon nitride spacer layer 6 and the polysilicon active layer 2 are integrated with each other. The structure of the connection.
  • the base substrate 1 is first provided with a buffer layer 7 including a silicon nitride layer 71 and silicon oxide sequentially formed on the substrate substrate.
  • the polysilicon active layer 2 is prepared to be formed on the buffer layer 7.
  • the silicon nitride spacer layer 6 is formed on the surface of the polysilicon active layer 2 by an ion implantation process and a high temperature annealing process.
  • the gate insulating layer 3 is formed on the buffer layer 7 by a deposition process and covers the polysilicon active layer 2 and the silicon nitride spacer layer 6, and the silicon nitride spacer layer 6 is formed in the On the connection interface of the polysilicon active layer 2 and the gate insulating layer 3.
  • the gate electrode 4 is formed on the gate insulating layer 3 and directly above the polysilicon active layer 2, and the gate electrode 4 is covered with an interlayer dielectric layer 8.
  • the source electrode 5a and the drain electrode 5b are formed on the interlayer dielectric layer 8, and the source electrode 5a passes through the first via 81 provided in the interlayer dielectric layer 8 and the gate insulating layer 3. Electrically connected to one end of the polysilicon active layer 2, the drain electrode 5b is electrically connected to the second via 82 disposed in the interlayer dielectric layer 8 and the gate insulating layer 3 The other end of the polysilicon active layer 2 is described.
  • a patterned light shielding unit 9 is disposed between the substrate substrate 1 and the buffer layer 7 , and the light shielding unit 9 is directly opposite to the patterned polysilicon active layer 2 . .
  • the polysilicon active layer 2 is further subjected to a sub-region doping process, and the polysilicon active layer 2 is sequentially formed with an undoped region 21 from the middle to the both ends, and lightly doped.
  • the source electrode 5a penetrates the silicon nitride spacer 6 to be electrically connected to the heavily doped region 23 of one end of the polysilicon active layer 2
  • the drain electrode 2b penetrates the silicon nitride spacer layer 6 is electrically connected to the heavily doped region 23 at the other end of the polysilicon active layer 2.
  • the low temperature polysilicon thin film transistor provided in the above embodiment is prepared to form a silicon nitride spacer layer at a connection interface between the polysilicon active layer and the gate insulating layer, and the silicon nitride spacer layer is formed by an ion implantation process and a high temperature annealing process.
  • the polysilicon active layer On the surface of the polysilicon active layer, the polysilicon active layer is integrally connected to each other, and the defect density is much smaller than the defect density of the gate insulating layer.
  • the silicon nitride spacer layer reduces the defect density of the connection interface between the polysilicon active layer and the gate insulating layer, reduces the leakage current of the thin film transistor, increases the breakdown voltage, and enables the thin film transistor to have good and stable electrical properties.
  • This embodiment provides a method for preparing a low temperature polysilicon thin film transistor.
  • the preparation method includes the steps of:
  • a substrate 1 is provided on which a pattern is formed on the substrate substrate 1 Shading unit 9.
  • the base substrate 1 may be an optional glass substrate, and a patterned shading unit 9 is prepared by a deposition process and a photolithography process in sequence.
  • a polysilicon thin film layer 2a is formed on the base substrate 1. This step specifically includes:
  • step S1 specifically includes:
  • a buffer layer 7 and an amorphous silicon film layer 2b are sequentially deposited on the substrate substrate 1 by using a semiconductor deposition process, and the buffer layer 7 is sequentially formed on the substrate substrate 1.
  • the silicon nitride layer 71 and the silicon oxide layer 72 cover the light shielding unit 9.
  • S12 is processed by an excimer laser annealing (ELA) process to crystallize the amorphous silicon thin film layer 2b to form a polysilicon thin film layer 2a.
  • ELA excimer laser annealing
  • the amorphous silicon thin film layer 2b is also subjected to a heating dehydrogenation treatment before the ELA process of step S12 is performed, thereby making the finally prepared polycrystalline silicon thin film layer 2a have better electrical properties.
  • the temperature of the heating dehydrogenation treatment may be selected to be 350 to 450 °C.
  • the polysilicon thin film layer 2a is etched to form a patterned polysilicon active layer 2 by using a photolithography process, and the ion implantation layer 6a is left on the surface of the polysilicon active layer 2.
  • the patterned polysilicon active layer 2 is facing the patterned shading unit 9 below.
  • the polysilicon active layer 2 is doped by an ion implantation process, so that the polysilicon active layer 2 is sequentially formed with an undoped region from the middle to the both ends.
  • the polysilicon active layer 2 may be doped by ion implantation in a halftone mask process or a gray tone mask process to form the undoped region 21 and the lightly doped region. 22 and heavily doped region 23.
  • a gate insulating layer 3 covering the polysilicon active layer 2 is deposited on the base substrate 1.
  • the gate insulating layer 3 is formed on the buffer layer 7 and covers the polysilicon active layer 2 and the ion implantation layer 6a, and the gate insulating layer 3 may be silicon oxide (SiO x ).
  • a gate electrode 4 and an interlayer dielectric layer 8 are sequentially formed on the gate insulating layer 3. Specifically, first, a patterned gate electrode 4 is formed by a deposition process and a photolithography process, the gate electrode 4 is located directly above the polysilicon active layer 2, and the material of the gate electrode 4 is selected from It is not limited to one or more of Cr, Mo, Al, and Cu, and may be one or more layers stacked.
  • the interlayer dielectric layer 8 may be a silicon oxide (SiO x) layer or a silicon nitride (SiN x
  • the layer is a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
  • the device structure prepared in the above step is annealed by a high temperature annealing process to recrystallize the ion implantation layer 6a, and the polysilicon active layer 2 and the gate insulating layer 3 are A silicon nitride spacer layer 6 is formed therebetween.
  • Most of the nitrogen in the implanted silicon is embedded in the lattice loss region formed by the implantation, and at the high temperature annealing, the damaged region begins to recrystallize and grow to form a continuous solid solution Si-N band, in the polysilicon active layer 2 and the gate.
  • the interface of the pole insulating layer 3 is deposited to form a silicon nitride spacer layer and to generate a silicon surface oxidation inhibiting effect.
  • the implantation of nitrogen ions can effectively suppress the TED (Transient Enhanced Diffusion) problem in the heat treatment, control the channel length of the polysilicon active layer 2, and improve the leakage problem of the p-n junction.
  • TED Transient Enhanced Diffusion
  • TED is formed by the supersaturated self-gap silicon atoms combined with the doping atoms of the substitution sites to form a gap state, which is then moved in a high temperature heat treatment.
  • the nitrogen ions are more likely to combine with the self-gap atoms to form a movable atom than the dopant atoms, thereby suppressing TED, that is, suppressing diffusion of the dopant atoms to the gate insulating layer 3.
  • a first via 81 and a second via 82 are etched into the interlayer dielectric layer 8 and the gate insulating layer 3 by using a photolithography process, the first pass
  • the hole 81 and the second via 82 penetrate the silicon nitride spacer layer 6 until the polysilicon active layer 2 is exposed.
  • the first via 81 and the second via 82 are respectively connected to the heavily doped region 23 at both ends of the polysilicon active layer 2.
  • the source electrode 5a being connected to the polysilicon active through the first via 81 Layer 2
  • the drain electrode 5b is connected to the polysilicon active layer 2 through the second via 82.
  • the patterned source electrode 5a and the drain electrode 5b are prepared by a deposition process and a photolithography process, and the source electrode 5a is electrically connected to the heavily doped region 23 of one end of the polysilicon active layer 2
  • the drain electrode 5b is electrically connected to the heavily doped region 23 at the other end of the polysilicon active layer 2.
  • the material of the source electrode 5a and the drain electrode 5b is selected from, but not limited to, Cr, Mo, Al, Cu. One or more of them may be stacked in one or more layers.
  • a photolithography process (patterning process) is employed in a plurality of steps.
  • Each of the photolithography processes includes masking, exposure, development, etching, and stripping processes, respectively, wherein the etching process includes dry etching and wet etching.
  • Lithography is already a relatively mature process technology in the field. The details are not described here.
  • This embodiment provides a method for preparing a low-temperature polysilicon thin film transistor. Compared with the preparation method provided in Embodiment 2, the preparation method of the present embodiment differs in the order of partial steps.
  • a polysilicon thin film layer 2a is formed on the base substrate 1, as shown in Fig. 3c. After the preparation of the polycrystalline silicon thin film layer 2a, the following steps are different from those in the second embodiment.
  • the polysilicon thin film layer 2a is etched to form a patterned polysilicon active layer 2 by a photolithography process.
  • the patterned polysilicon active layer 2 is facing the patterned shading unit 9 below.
  • the polysilicon active layer 2 is doped by an ion implantation process, so that the polysilicon active layer 2 is sequentially formed with an undoped region from the middle to the both ends.
  • the polysilicon active layer 2 may be doped by ion implantation in a halftone mask process or a gray tone mask process to form the undoped region 21 and the lightly doped region. 22 and heavily doped region 23.
  • a gate insulating layer 3 covering the polysilicon active layer 2 is deposited on the base substrate 1.
  • the gate insulating layer 3 is formed on the buffer layer 7 to cover the polysilicon active layer 2, the gate insulating layer 3 may be a silicon oxide (SiO x) layer or a silicon nitride (SiN The x ) layer is a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
  • a gate electrode 4 and an interlayer dielectric layer 8 are sequentially formed on the gate insulating layer 3. This step is carried out with reference to step S5 in the second embodiment.
  • the device structure prepared in the above step is annealed by a high temperature annealing process to recrystallize the ion implantation layer 6a, and the polysilicon active layer 2 and the gate insulating layer 3 are A silicon nitride spacer layer 6 is formed therebetween.
  • This step is carried out with reference to step S6 in the second embodiment.
  • a patterned source electrode 5a and a drain electrode 5b are formed on the interlayer dielectric layer 8, and the source electrode 5a passes through the first pass.
  • Hole 81 is connected to the heavily doped region 23 of one end of the polysilicon active layer 2
  • the drain electrode 5b is connected to the heavily doped region of the other end of the polysilicon active layer 2 through the second via 5b 23.
  • the finally prepared low temperature polysilicon thin film transistor is shown in Figure 3k.
  • the low temperature polysilicon thin film transistor and the preparation method thereof are provided in the embodiment of the present invention, and a silicon nitride spacer layer is formed at a connection interface between the polysilicon active layer and the gate insulating layer, and the silicon nitride spacer layer is passed through
  • the ion implantation process and the high temperature annealing process are formed on the surface of the polysilicon active layer, and are integrally connected to the polysilicon active layer, and the defect density is much smaller than the defect density of the gate insulating layer.
  • the silicon nitride spacer layer reduces the defect density of the connection interface between the polysilicon active layer and the gate insulating layer, reduces the leakage current of the thin film transistor, increases the breakdown voltage, and enables the thin film transistor to have good and stable electrical properties. Further improvements in the quality of the final product (such as LCD or OLED).

Abstract

A preparation method for a low temperature polysilicon thin film transistor, comprising steps of: sequentially forming a polysilicon active layer (2) and a gate insulation layer (3) covering the polysilicon active layer (2) on a base substrate (1); using an ion implantation process to implant nitrogen ions to the surface of the polysilicon active layer (2) facing towards the gate insulation layer (3), so as to form an ion implantation layer (6a); and using a high temperature annealing process to recrystallize the ion implantation layer (6a), so as to form a silicon nitride spacer layer (6) between the polysilicon active layer (2) and the gate insulation layer (3). A low temperature crystalline silicon thin film transistor, comprising a polysilicon active layer (2), a gate insulation layer (3), a gate electrode (4), a source electrode (5a), and a drain electrode (5b) which are successively provided on a base substrate (1), a silicon nitride spacer layer (6) being formed on a joint interface between the polysilicon active layer (2) and the gate insulation layer (3), the silicon nitride spacer layer (6) and the polysilicon active layer (2) being of an integrated interconnected structure.

Description

低温多晶硅薄膜晶体管及其制备方法Low temperature polysilicon thin film transistor and preparation method thereof 技术领域Technical field
本发明涉及半导体器件的制造工艺，尤其涉及一种低温多晶硅薄膜晶体管及其制备方法。The present invention relates to a manufacturing process of a semiconductor device, and more particularly to a low temperature polysilicon thin film transistor and a method of fabricating the same.
背景技术Background technique
平板显示装置具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有的平板显示装置主要包括液晶显示装置(Liquid Crystal Display，LCD)及有机电致发光显示装置(Organic Light Emitting Display，OLED)。薄膜晶体管(Thin Film Transistor，TFT)是平板显示装置的重要组成部分，可形成在玻璃基板或塑料基板上，通常作为开光装置和驱动装置用在诸如LCD、OLED。The flat panel display device has many advantages such as thin body, power saving, no radiation, and has been widely used. The conventional flat panel display device mainly includes a liquid crystal display (LCD) and an organic light emitting display (OLED). Thin Film Transistors (TFTs) are an important part of flat panel display devices and can be formed on glass substrates or plastic substrates, and are commonly used as light-emitting devices and driving devices such as LCDs and OLEDs.
近年来，显示技术得到快速发展，薄膜晶体管技术由原来的非晶硅(a-Si)薄膜晶体管发展到低温多晶硅(Low Temperature Poly-Silicon，LTPS)薄膜晶体管。LTPS薄膜晶体管具有多方面的优势，例如，LTPS薄膜晶体管具有较高的电子迁移率，其不仅可有效减小薄膜晶体管的面积，提高开口率，而且可以在提高显示亮度的同时降低整体功耗。又如，较高的电子迁移率可以将部分驱动电路集成在基板上，减少驱动集成电路IC，大幅度提升显示面板的可靠度，大幅度降低制造成本。因此，LTPS薄膜晶体管逐步成为显示技术领域的研究热点。In recent years, display technology has been rapidly developed, and thin film transistor technology has evolved from the original amorphous silicon (a-Si) thin film transistor to the low temperature poly-Silicon (LTPS) thin film transistor. LTPS thin film transistors have many advantages. For example, LTPS thin film transistors have high electron mobility, which not only can effectively reduce the area of thin film transistors, increase the aperture ratio, but also improve the display brightness while reducing the overall power consumption. For example, a higher electron mobility can integrate part of the driving circuit on the substrate, reduce the driving integrated circuit IC, greatly improve the reliability of the display panel, and greatly reduce the manufacturing cost. Therefore, LTPS thin film transistors have gradually become a research hotspot in the field of display technology.
现有的LTPS薄膜晶体管的结构，主要包括衬底基板以及依次设置在衬底基板上的多晶硅有源层、栅极绝缘层、栅电极、源电极和漏电极，源电极和漏电极通过过孔电性连接到多晶硅有源层。其中，覆盖在多晶硅有源层的栅极绝缘层是通过沉积工艺制备形成，栅极绝缘层的缺陷密度较大，多晶硅有源层中的载流子易于扩散到栅极绝缘层中，形成较大的漏电流，增加LTPS薄膜晶体管的电性能的不稳定性。因此，现有技术还有待于改善和发展。The structure of the existing LTPS thin film transistor mainly comprises a base substrate and a polysilicon active layer, a gate insulating layer, a gate electrode, a source electrode and a drain electrode which are sequentially disposed on the base substrate, and the source electrode and the drain electrode pass through the via hole Electrically connected to the polysilicon active layer. Wherein, the gate insulating layer covering the active layer of the polysilicon is formed by a deposition process, the defect density of the gate insulating layer is large, and carriers in the active layer of the polysilicon are easily diffused into the gate insulating layer, forming a comparison Large leakage current increases the instability of the electrical properties of LTPS thin film transistors. Therefore, the prior art has yet to be improved and developed.
发明内容Summary of the invention
有鉴于此，本发明提供了一种低温多晶硅薄膜晶体管及其制备方法，其可以减小多晶硅有源层和栅极绝缘层连接界面的缺陷密度，降低薄膜晶体管的漏 电流，使得薄膜晶体管具有良好且稳定的电性能。In view of this, the present invention provides a low temperature polysilicon thin film transistor and a method of fabricating the same, which can reduce the defect density of the interface between the active layer of the polysilicon and the gate insulating layer, and reduce the leakage of the thin film transistor. The current makes the thin film transistor have good and stable electrical properties.
为了实现上述目的，本发明采用了如下的技术方案：In order to achieve the above object, the present invention adopts the following technical solutions:
一种低温多晶硅薄膜晶体管的制备方法，其包括：在衬底基板上依次制备形成多晶硅有源层和覆盖所述多晶硅有源层的栅极绝缘层；应用离子植入工艺，在所述多晶硅有源层的朝向所述栅极绝缘层的表面上注入氮离子，形成离子注入层；应用高温退火工艺，使所述离子注入层重结晶，在所述多晶硅有源层和所述栅极绝缘层之间形成氮化硅间隔层。A method for preparing a low-temperature polysilicon thin film transistor, comprising: sequentially forming a polysilicon active layer and a gate insulating layer covering the polysilicon active layer on a substrate; applying an ion implantation process, wherein the polysilicon has Nitrogen ions are implanted into the surface of the source layer facing the gate insulating layer to form an ion implantation layer; the ion implantation layer is recrystallized by a high temperature annealing process, and the polysilicon active layer and the gate insulating layer are A silicon nitride spacer layer is formed between them.
其中，所述制备方法包括步骤：Wherein, the preparation method comprises the steps of:
S1、在衬底基板上制备形成多晶硅薄膜层；S1, preparing a polysilicon film layer on the substrate;
S21、应用离子植入工艺，在所述多晶硅薄膜层的表面上注入氮离子，形成离子注入层；S21, applying an ion implantation process, implanting nitrogen ions on the surface of the polysilicon film layer to form an ion implantation layer;
S31、将所述多晶硅薄膜层刻蚀形成图案化的多晶硅有源层，所述多晶硅有源层的表面上保留所述离子注入层；S31, etching the polysilicon thin film layer to form a patterned polysilicon active layer, the ion implantation layer is retained on a surface of the polysilicon active layer;
S41、在所述衬底基板上沉积形成覆盖所述多晶硅有源层的栅极绝缘层；S41, depositing a gate insulating layer covering the polysilicon active layer on the substrate;
S5、在所述栅极绝缘层上依次制备形成栅电极和层间介质层；S5, sequentially forming a gate electrode and an interlayer dielectric layer on the gate insulating layer;
S6、应用高温退火工艺，使所述离子注入层重结晶，在所述多晶硅有源层和所述栅极绝缘层之间形成氮化硅间隔层；S6, applying a high temperature annealing process, recrystallizing the ion implantation layer, forming a silicon nitride spacer layer between the polysilicon active layer and the gate insulating layer;
S7、在所述层间介质层和所述栅极绝缘层中刻蚀形成暴露出所述多晶硅有源层的第一过孔和第二过孔；S7, etching in the interlayer dielectric layer and the gate insulating layer to form a first via and a second via exposing the active layer of the polysilicon;
S8、在所述层间介质层上制备形成图案化的源电极和漏电极，所述源电极通过所述第一过孔连接到所述多晶硅有源层，所述漏电极通过所述第二过孔连接到所述多晶硅有源层。S8, preparing a patterned source electrode and a drain electrode on the interlayer dielectric layer, wherein the source electrode is connected to the polysilicon active layer through the first via hole, and the drain electrode passes the second layer A via is connected to the polysilicon active layer.
其中，所述制备方法包括步骤：Wherein, the preparation method comprises the steps of:
S1、在衬底基板上制备形成多晶硅薄膜层；S1, preparing a polysilicon film layer on the substrate;
S22、将所述多晶硅薄膜层刻蚀形成图案化的多晶硅有源层；S22, etching the polysilicon thin film layer to form a patterned polysilicon active layer;
S32、在所述衬底基板上沉积形成覆盖所述多晶硅有源层的栅极绝缘层；S32, depositing a gate insulating layer covering the polysilicon active layer on the substrate;
S42、应用离子植入工艺，从所述栅极绝缘层的上方注入氮离子，在所述多 晶硅有源层的表面上形成离子注入层；S42, applying an ion implantation process, injecting nitrogen ions from above the gate insulating layer, in the Forming an ion implantation layer on a surface of the crystalline silicon active layer;
S5、在所述栅极绝缘层上依次制备形成栅电极和层间介质层；S5, sequentially forming a gate electrode and an interlayer dielectric layer on the gate insulating layer;
S6、应用高温退火工艺，使所述离子注入层重结晶，在所述多晶硅有源层和所述栅极绝缘层之间形成氮化硅间隔层；S6, applying a high temperature annealing process, recrystallizing the ion implantation layer, forming a silicon nitride spacer layer between the polysilicon active layer and the gate insulating layer;
S7、在所述层间介质层和所述栅极绝缘层中刻蚀形成暴露出所述多晶硅有源层的第一过孔和第二过孔；S7, etching in the interlayer dielectric layer and the gate insulating layer to form a first via and a second via exposing the active layer of the polysilicon;
S8、在所述层间介质层上制备形成图案化的源电极和漏电极，所述源电极通过所述第一过孔连接到所述多晶硅有源层，所述漏电极通过所述第二过孔连接到所述多晶硅有源层。S8, preparing a patterned source electrode and a drain electrode on the interlayer dielectric layer, wherein the source electrode is connected to the polysilicon active layer through the first via hole, and the drain electrode passes the second layer A via is connected to the polysilicon active layer.
其中，步骤S1具体包括：S11、在所述衬底基底上依次沉积缓冲层和非晶硅薄膜层；S12、应用准分子激光退火工艺进行处理，使所述非晶硅薄膜层结晶形成多晶硅薄膜层。The step S1 specifically includes: S11, sequentially depositing a buffer layer and an amorphous silicon film layer on the substrate substrate; S12, applying an excimer laser annealing process to form the amorphous silicon film layer to form a polysilicon film Floor.
其中，所述缓冲层包括依次形成在所述衬底基底上的氮化硅层和氧化硅层。Wherein, the buffer layer comprises a silicon nitride layer and a silicon oxide layer sequentially formed on the substrate substrate.
其中，在进行步骤S1之前还包括步骤：S0、在所述衬底基底上制备形成图案化的遮光单元，所述遮光单元正对于后续工艺中制备形成的图案化的多晶硅有源层。Wherein, before performing step S1, the method further comprises the steps of: S0, preparing a patterned light-shielding unit on the substrate substrate, wherein the light-shielding unit is for preparing a patterned polysilicon active layer formed in a subsequent process.
其中，在制备形成所述图案化的多晶硅有源层之后，应用离子植入工艺对所述多晶硅有源层进行掺杂处理，使所述多晶硅有源层从中间向两端依次形成有未掺杂区、轻掺杂区和重掺杂区；其中，所述源电极电性连接到所述多晶硅有源层的其中一端的重掺杂区，所述漏电极电性连接到所述多晶硅有源层的另一端的重掺杂区。After the preparation of the patterned polysilicon active layer, the polysilicon active layer is doped by an ion implantation process, so that the polysilicon active layer is sequentially formed from the middle to the both ends. a dummy region, a lightly doped region, and a heavily doped region; wherein the source electrode is electrically connected to a heavily doped region of one end of the polysilicon active layer, and the drain electrode is electrically connected to the polysilicon A heavily doped region at the other end of the source layer.
其中，所述栅极绝缘层为氧化硅层或氮化硅层或者是氧化硅层与氮化硅层叠加的复合结构层。The gate insulating layer is a silicon oxide layer or a silicon nitride layer or a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
本发明还提供了一种低温晶硅薄膜晶体管，包括依次设置在衬底基板上的多晶硅有源层、栅极绝缘层、栅电极、源电极和漏电极，其中，所述多晶硅有源层和所述栅极绝缘层之间的连接界面形成有氮化硅间隔层，所述氮化硅间隔层与所述多晶硅有源层是一体相互连接的结构。The present invention also provides a low temperature crystalline silicon thin film transistor comprising a polysilicon active layer, a gate insulating layer, a gate electrode, a source electrode and a drain electrode sequentially disposed on a base substrate, wherein the polysilicon active layer and The connection interface between the gate insulating layers is formed with a silicon nitride spacer layer, and the silicon nitride spacer layer and the polysilicon active layer are integrally connected to each other.
其中，所述氮化硅间隔层是在所述多晶硅有源层的表面上通过离子植入工 艺和高温退火工艺制备形成，所述栅极绝缘层是通过沉积工艺形成在所述多晶硅有源层上，所述氮化硅间隔层的缺陷密度小于所述栅极绝缘层的缺陷密度。Wherein the silicon nitride spacer layer is passed through an ion implanter on the surface of the polysilicon active layer Formed by a high temperature annealing process, the gate insulating layer is formed on the polysilicon active layer by a deposition process, and a defect density of the silicon nitride spacer layer is smaller than a defect density of the gate insulating layer.
本发明实施例中提供的低温多晶硅薄膜晶体管及其制备方法，通过离子植入工艺和高温退火工艺，在多晶硅有源层和栅极绝缘层的连接界面制备形成氮化硅间隔层，所述氮化硅间隔层可以减小多晶硅有源层和栅极绝缘层连接界面的缺陷密度，降低了薄膜晶体管的漏电流，增大击穿电压，使得薄膜晶体管具有良好且稳定的电性能。The low-temperature polysilicon thin film transistor and the preparation method thereof are provided in the embodiment of the present invention, and a silicon nitride spacer layer is formed at a connection interface between the polysilicon active layer and the gate insulating layer by an ion implantation process and a high temperature annealing process, the nitrogen The silicon spacer layer can reduce the defect density of the connection interface between the polysilicon active layer and the gate insulating layer, reduce the leakage current of the thin film transistor, increase the breakdown voltage, and make the thin film transistor have good and stable electrical properties.
附图说明DRAWINGS
图1是本发明实施例1提供的低温多晶硅薄膜晶体管的结构示意图；1 is a schematic structural view of a low temperature polysilicon thin film transistor according to Embodiment 1 of the present invention;
图2是如图1中A部分的放大示意图；Figure 2 is an enlarged schematic view of a portion A in Figure 1;
图3a～3k是本发明实施例2提供的低温多晶硅薄膜晶体管的制备方法中，各个步骤对应获得的器件结构的示例性图示；3a-3k are exemplary illustrations of device structures obtained in accordance with respective steps in a method of fabricating a low temperature polysilicon thin film transistor according to Embodiment 2 of the present invention;
图4a～4f是本发明实施例3提供的低温多晶硅薄膜晶体管的制备方法中，各个步骤对应获得的器件结构的示例性图示。4a to 4f are exemplary illustrations of device structures obtained in accordance with respective steps in a method of fabricating a low temperature polysilicon thin film transistor according to a third embodiment of the present invention.
具体实施方式Detailed ways
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明的具体实施方式进行详细说明。这些优选实施方式的示例在附图中进行了例示。附图中所示和根据附图描述的本发明的实施方式仅仅是示例性的，并且本发明并不限于这些实施方式。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Examples of these preferred embodiments are illustrated in the drawings. The embodiments of the invention shown in the drawings and described in the drawings are merely exemplary, and the invention is not limited to the embodiments.
在此，还需要说明的是，为了避免因不必要的细节而模糊了本发明，在附图中仅仅示出了与根据本发明的方案密切相关的结构和/或处理步骤，而省略了与本发明关系不大的其他细节。In this context, it is also to be noted that in order to avoid obscuring the invention by unnecessary detail, only the structures and/or processing steps closely related to the solution according to the invention are shown in the drawings, and the Other details that are not relevant to the present invention.
实施例1Example 1
本实施例提供了一种低温晶硅薄膜晶体管，如图1所示，所述低温晶硅薄膜晶体管包括依次设置在衬底基板1上的多晶硅有源层2、栅极绝缘层3、栅电极4、源电极5a和漏电极5b。其中，所述多晶硅有源层2和所述栅极绝缘层3之间的连接界面形成有氮化硅间隔层6，所述氮化硅间隔层6与所述多晶硅有源层2是一体相互连接的结构。 The present embodiment provides a low-temperature crystalline silicon thin film transistor. As shown in FIG. 1, the low-temperature crystalline silicon thin film transistor includes a polysilicon active layer 2, a gate insulating layer 3, and a gate electrode which are sequentially disposed on a base substrate 1. 4. Source electrode 5a and drain electrode 5b. Wherein, a connection interface between the polysilicon active layer 2 and the gate insulating layer 3 is formed with a silicon nitride spacer layer 6, and the silicon nitride spacer layer 6 and the polysilicon active layer 2 are integrated with each other. The structure of the connection.
具体地，如图1和图2所示，所述衬底基板1上首先设置有缓冲层7，所述缓冲层7包括依次形成在所述衬底基底上的氮化硅层71和氧化硅层72。所述多晶硅有源层2制备形成在所述缓冲层7上。所述氮化硅间隔层6通过离子植入工艺和高温退火工艺制备形成在所述多晶硅有源层2的表面上。所述栅极绝缘层3是通过沉积工艺形成在所述缓冲层7上并覆盖所述多晶硅有源层2和所述氮化硅间隔层6，所述氮化硅间隔层6形成在所述多晶硅有源层2和所述栅极绝缘层3的连接界面上。所述栅电极4形成在所述栅极绝缘层3上并且相对位于所述多晶硅有源层2的正上方，所述栅电极4上覆设有层间介质层8。所述源电极5a和漏电极5b形成在所述层间介质层8上，所述源电极5a通过设置在所述层间介质层8和所述栅极绝缘层3中的第一过孔81电性连接到所述多晶硅有源层2的一端，所述漏电极5b则通过设置在所述层间介质层8和所述栅极绝缘层3中的第二过孔82电性连接到所述多晶硅有源层2的另一端。Specifically, as shown in FIG. 1 and FIG. 2, the base substrate 1 is first provided with a buffer layer 7 including a silicon nitride layer 71 and silicon oxide sequentially formed on the substrate substrate. Layer 72. The polysilicon active layer 2 is prepared to be formed on the buffer layer 7. The silicon nitride spacer layer 6 is formed on the surface of the polysilicon active layer 2 by an ion implantation process and a high temperature annealing process. The gate insulating layer 3 is formed on the buffer layer 7 by a deposition process and covers the polysilicon active layer 2 and the silicon nitride spacer layer 6, and the silicon nitride spacer layer 6 is formed in the On the connection interface of the polysilicon active layer 2 and the gate insulating layer 3. The gate electrode 4 is formed on the gate insulating layer 3 and directly above the polysilicon active layer 2, and the gate electrode 4 is covered with an interlayer dielectric layer 8. The source electrode 5a and the drain electrode 5b are formed on the interlayer dielectric layer 8, and the source electrode 5a passes through the first via 81 provided in the interlayer dielectric layer 8 and the gate insulating layer 3. Electrically connected to one end of the polysilicon active layer 2, the drain electrode 5b is electrically connected to the second via 82 disposed in the interlayer dielectric layer 8 and the gate insulating layer 3 The other end of the polysilicon active layer 2 is described.
进一步地，如图1所示，所述衬底基底1和所述缓冲层7之间还设置有图案化的遮光单元9，所述遮光单元9正对于上方的图案化的多晶硅有源层2。Further, as shown in FIG. 1 , a patterned light shielding unit 9 is disposed between the substrate substrate 1 and the buffer layer 7 , and the light shielding unit 9 is directly opposite to the patterned polysilicon active layer 2 . .
进一步地，如图2所示，所述多晶硅有源层2还进行分区域掺杂处理，所述多晶硅有源层2从中间向两端依次形成有未掺杂(Undoped)区21、轻掺杂(Lightiy Drain Doping，LDD)区22和重掺杂(Heavily Drain Doping，HDD)区23。所述源电极5a穿透所述氮化硅间隔层6电性连接到所述多晶硅有源层2的其中一端的重掺杂区23，所述漏电极2b穿透所述氮化硅间隔层6电性连接到所述多晶硅有源层2的另一端的重掺杂区23。Further, as shown in FIG. 2, the polysilicon active layer 2 is further subjected to a sub-region doping process, and the polysilicon active layer 2 is sequentially formed with an undoped region 21 from the middle to the both ends, and lightly doped. Lightiy Drain Doping (LDD) zone 22 and Heavily Drain Doping (HDD) zone 23. The source electrode 5a penetrates the silicon nitride spacer 6 to be electrically connected to the heavily doped region 23 of one end of the polysilicon active layer 2, and the drain electrode 2b penetrates the silicon nitride spacer layer 6 is electrically connected to the heavily doped region 23 at the other end of the polysilicon active layer 2.
如上实施例提供的低温多晶硅薄膜晶体管，在多晶硅有源层和栅极绝缘层的连接界面制备形成氮化硅间隔层，所述氮化硅间隔层是通过离子植入工艺和高温退火工艺制备形成在多晶硅有源层的表面上，与多晶硅有源层是一体相互连接的结构，其缺陷密度远远小于栅极绝缘层的缺陷密度。所述氮化硅间隔层减小了多晶硅有源层和栅极绝缘层连接界面的缺陷密度，降低了薄膜晶体管的漏电流，增大击穿电压，使得薄膜晶体管具有良好且稳定的电性能。The low temperature polysilicon thin film transistor provided in the above embodiment is prepared to form a silicon nitride spacer layer at a connection interface between the polysilicon active layer and the gate insulating layer, and the silicon nitride spacer layer is formed by an ion implantation process and a high temperature annealing process. On the surface of the polysilicon active layer, the polysilicon active layer is integrally connected to each other, and the defect density is much smaller than the defect density of the gate insulating layer. The silicon nitride spacer layer reduces the defect density of the connection interface between the polysilicon active layer and the gate insulating layer, reduces the leakage current of the thin film transistor, increases the breakdown voltage, and enables the thin film transistor to have good and stable electrical properties.
实施例2Example 2
本实施例提供了一种低温多晶硅薄膜晶体管的制备方法，参阅图3a～3k，所述制备方法包括步骤：This embodiment provides a method for preparing a low temperature polysilicon thin film transistor. Referring to Figures 3a to 3k, the preparation method includes the steps of:
S0、如图3a所示，提供衬底基板1，在所述衬底基底1上制备形成图案化 的遮光单元9。具体地，所述衬底基板1可以是选用玻璃基板，依次通过沉积工艺和光刻工艺，制备形成图案化的遮光单元9。S0, as shown in FIG. 3a, a substrate 1 is provided on which a pattern is formed on the substrate substrate 1 Shading unit 9. Specifically, the base substrate 1 may be an optional glass substrate, and a patterned shading unit 9 is prepared by a deposition process and a photolithography process in sequence.
S1、在衬底基板1上制备形成多晶硅薄膜层2a。该步骤具体包括：S1, a polysilicon thin film layer 2a is formed on the base substrate 1. This step specifically includes:
其中，步骤S1具体包括：Wherein, step S1 specifically includes:
S11、如图3b所示，应用半导体沉积工艺，在所述衬底基底1上依次沉积缓冲层7和非晶硅薄膜层2b，所述缓冲层7包括依次形成在所述衬底基底1上的氮化硅层71和氧化硅层72，所述缓冲层7覆盖所述遮光单元9。S11, as shown in FIG. 3b, a buffer layer 7 and an amorphous silicon film layer 2b are sequentially deposited on the substrate substrate 1 by using a semiconductor deposition process, and the buffer layer 7 is sequentially formed on the substrate substrate 1. The silicon nitride layer 71 and the silicon oxide layer 72 cover the light shielding unit 9.
S12、如图3c所示，应用准分子激光退火(ELA)工艺进行处理，使所述非晶硅薄膜层2b结晶形成多晶硅薄膜层2a。S12, as shown in FIG. 3c, is processed by an excimer laser annealing (ELA) process to crystallize the amorphous silicon thin film layer 2b to form a polysilicon thin film layer 2a.
在优选的方案中，在进行步骤S12的ELA工艺之前，还对所述非晶硅薄膜层2b进行加热去氢处理，由此使得最终制备得到的多晶硅薄膜层2a具有更良好的电性能。具体地，加热去氢处理的温度可以选择为350～450℃。In a preferred embodiment, the amorphous silicon thin film layer 2b is also subjected to a heating dehydrogenation treatment before the ELA process of step S12 is performed, thereby making the finally prepared polycrystalline silicon thin film layer 2a have better electrical properties. Specifically, the temperature of the heating dehydrogenation treatment may be selected to be 350 to 450 °C.
S21、如图3d所示，应用离子植入工艺，在所述多晶硅薄膜层2a的表面上注入氮离子，形成离子注入层6a。S21, as shown in FIG. 3d, by applying an ion implantation process, nitrogen ions are implanted into the surface of the polysilicon thin film layer 2a to form an ion implantation layer 6a.
S31、如图3e所示，应用光刻工艺，将所述多晶硅薄膜层2a刻蚀形成图案化的多晶硅有源层2，所述多晶硅有源层2的表面上保留所述离子注入层6a。其中，所述图案化的多晶硅有源层2正对于下方的所述图案化的遮光单元9。S31. As shown in FIG. 3e, the polysilicon thin film layer 2a is etched to form a patterned polysilicon active layer 2 by using a photolithography process, and the ion implantation layer 6a is left on the surface of the polysilicon active layer 2. Wherein, the patterned polysilicon active layer 2 is facing the patterned shading unit 9 below.
进一步地，如图3f所示，应用离子植入工艺对所述多晶硅有源层2进行掺杂处理，使所述多晶硅有源层2从中间向两端依次形成有未掺杂(Undoped)区21、轻掺杂(Lightiy Drain Doping，LDD)区22和重掺杂(Heavily Drain Doping，HDD)区23。具体地，可以采用半色调掩膜工艺或者是灰色调掩膜工艺，分两次对所述多晶硅有源层2进行离子植入掺杂，从而形成所述未掺杂区21、轻掺杂区22和重掺杂区23。Further, as shown in FIG. 3f, the polysilicon active layer 2 is doped by an ion implantation process, so that the polysilicon active layer 2 is sequentially formed with an undoped region from the middle to the both ends. 21. Lightiy Drain Doping (LDD) region 22 and Heavily Drain Doping (HDD) region 23. Specifically, the polysilicon active layer 2 may be doped by ion implantation in a halftone mask process or a gray tone mask process to form the undoped region 21 and the lightly doped region. 22 and heavily doped region 23.
S41、如图3g所示，在所述衬底基板1上沉积形成覆盖所述多晶硅有源层2的栅极绝缘层3。具体地，所述栅极绝缘层3形成在所述缓冲层7上并覆盖所述多晶硅有源层2和所述离子注入层6a，所述栅极绝缘层3可以是氧化硅(SiOx)层或氮化硅(SiNx)层或者是氧化硅层与氮化硅层叠加的复合结构层。S41, as shown in FIG. 3g, a gate insulating layer 3 covering the polysilicon active layer 2 is deposited on the base substrate 1. Specifically, the gate insulating layer 3 is formed on the buffer layer 7 and covers the polysilicon active layer 2 and the ion implantation layer 6a, and the gate insulating layer 3 may be silicon oxide (SiO x ). A layer or a silicon nitride (SiN x ) layer or a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
S5、如图3h所示，在所述栅极绝缘层3上依次制备形成栅电极4和层间介质层8。具体地，首先依次通过沉积工艺和光刻工艺，制备形成图案化的栅电极 4，所述栅电极4相对位于所述多晶硅有源层2的正上方，所述栅电极4的材料选自但不限于Cr、Mo、Al、Cu中的一种或多种，可为一层或多层堆叠。然后在通过沉积工艺制备形成层间介质层8，所述层间介质层8覆盖所述栅电极4，所述层间介质层8可以是氧化硅(SiOx)层或氮化硅(SiNx)层或者是氧化硅层与氮化硅层叠加的复合结构层。S5. As shown in FIG. 3h, a gate electrode 4 and an interlayer dielectric layer 8 are sequentially formed on the gate insulating layer 3. Specifically, first, a patterned gate electrode 4 is formed by a deposition process and a photolithography process, the gate electrode 4 is located directly above the polysilicon active layer 2, and the material of the gate electrode 4 is selected from It is not limited to one or more of Cr, Mo, Al, and Cu, and may be one or more layers stacked. Is then prepared by the deposition process forming the interlayer dielectric layer 8, the interlayer dielectric layer 8 covering the gate electrode 4, the interlayer dielectric layer 8 may be a silicon oxide (SiO x) layer or a silicon nitride (SiN x The layer is a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
S6、如图3i所示，应用高温退火工艺对上述步骤制备得到的器件结构进行退火，使所述离子注入层6a重结晶，在所述多晶硅有源层2和所述栅极绝缘层3之间形成氮化硅间隔层6。注入硅中氮大部分被嵌在注入所形成的晶格损失区域内，而在高温退火时，损伤区域开始重结晶生长，形成连续的固溶Si-N带，在多晶硅有源层2和栅极绝缘层3的界面堆积，形成氮化硅间隔层以及产生硅表面氧化抑制作用。另外，氮离子的注入可以有效地抑制热处理中的TED(Transient enhanced diffusion)问题，控制多晶硅有源层2沟道长度，改善p-n结的漏电问题。TED是由于过饱和的自间隙硅原子和替代位的掺杂原子结合形成间隙态，进而在高温热处理中移动形成的。注入氮离子之后，氮离子相比于掺杂原子更容易与自间隙原子结合形成可动原子，从而抑制TED，也就是抑制掺杂原子向栅极绝缘层3扩散。S6, as shown in FIG. 3i, the device structure prepared in the above step is annealed by a high temperature annealing process to recrystallize the ion implantation layer 6a, and the polysilicon active layer 2 and the gate insulating layer 3 are A silicon nitride spacer layer 6 is formed therebetween. Most of the nitrogen in the implanted silicon is embedded in the lattice loss region formed by the implantation, and at the high temperature annealing, the damaged region begins to recrystallize and grow to form a continuous solid solution Si-N band, in the polysilicon active layer 2 and the gate. The interface of the pole insulating layer 3 is deposited to form a silicon nitride spacer layer and to generate a silicon surface oxidation inhibiting effect. In addition, the implantation of nitrogen ions can effectively suppress the TED (Transient Enhanced Diffusion) problem in the heat treatment, control the channel length of the polysilicon active layer 2, and improve the leakage problem of the p-n junction. TED is formed by the supersaturated self-gap silicon atoms combined with the doping atoms of the substitution sites to form a gap state, which is then moved in a high temperature heat treatment. After the nitrogen ions are implanted, the nitrogen ions are more likely to combine with the self-gap atoms to form a movable atom than the dopant atoms, thereby suppressing TED, that is, suppressing diffusion of the dopant atoms to the gate insulating layer 3.
S7、如图3j所示，应用光刻工艺，在所述层间介质层8和所述栅极绝缘层3中刻蚀形成第一过孔81和第二过孔82，所述第一过孔81和第二过孔82穿透所述氮化硅间隔层6直至暴露出所述多晶硅有源层2。所述第一过孔81和第二过孔82分别连通至所述多晶硅有源层2两端的重掺杂区23。S7, as shown in FIG. 3j, a first via 81 and a second via 82 are etched into the interlayer dielectric layer 8 and the gate insulating layer 3 by using a photolithography process, the first pass The hole 81 and the second via 82 penetrate the silicon nitride spacer layer 6 until the polysilicon active layer 2 is exposed. The first via 81 and the second via 82 are respectively connected to the heavily doped region 23 at both ends of the polysilicon active layer 2.
S8、如图3k所示，在所述层间介质层8上制备形成图案化的源电极5a和漏电极5b，所述源电极5a通过所述第一过孔81连接到所述多晶硅有源层2，所述漏电极5b通过所述第二过孔82连接到所述多晶硅有源层2。具体地，依次通过沉积工艺和光刻工艺，制备形成图案化的源电极5a和漏电极5b，所述源电极5a电性连接到所述多晶硅有源层2的其中一端的重掺杂区23，所述漏电极5b电性连接到所述多晶硅有源层2的另一端的重掺杂区23，所述源电极5a和漏电极5b的材料选自但不限于Cr、Mo、Al、Cu中的一种或多种，可为一层或多层堆叠。S8, as shown in FIG. 3k, forming a patterned source electrode 5a and a drain electrode 5b formed on the interlayer dielectric layer 8, the source electrode 5a being connected to the polysilicon active through the first via 81 Layer 2, the drain electrode 5b is connected to the polysilicon active layer 2 through the second via 82. Specifically, the patterned source electrode 5a and the drain electrode 5b are prepared by a deposition process and a photolithography process, and the source electrode 5a is electrically connected to the heavily doped region 23 of one end of the polysilicon active layer 2 The drain electrode 5b is electrically connected to the heavily doped region 23 at the other end of the polysilicon active layer 2. The material of the source electrode 5a and the drain electrode 5b is selected from, but not limited to, Cr, Mo, Al, Cu. One or more of them may be stacked in one or more layers.
以上的工艺过程中，在多个步骤中采用了光刻工艺(构图工艺)。其中，每一次光刻工艺中又分别包括掩膜、曝光、显影、刻蚀和剥离等工艺，其中刻蚀工艺包括干法刻蚀和湿法刻蚀。光刻工艺已经是本领域中的比较成熟的工艺技 术，在此不再展开详细说明。In the above process, a photolithography process (patterning process) is employed in a plurality of steps. Each of the photolithography processes includes masking, exposure, development, etching, and stripping processes, respectively, wherein the etching process includes dry etching and wet etching. Lithography is already a relatively mature process technology in the field. The details are not described here.
实施例3Example 3
本实施例提供了一种低温多晶硅薄膜晶体管的制备方法，与实施例2提供的制备方法相比，本实施例的制备方法在部分步骤的顺序上有所不同。This embodiment provides a method for preparing a low-temperature polysilicon thin film transistor. Compared with the preparation method provided in Embodiment 2, the preparation method of the present embodiment differs in the order of partial steps.
参照实施例2中的步骤S0和S1，在衬底基板1上制备形成多晶硅薄膜层2a，如图3c所示的结构。在制备获得多晶硅薄膜层2a后，以下的步骤与实施例2中的有所不同。Referring to steps S0 and S1 in Embodiment 2, a polysilicon thin film layer 2a is formed on the base substrate 1, as shown in Fig. 3c. After the preparation of the polycrystalline silicon thin film layer 2a, the following steps are different from those in the second embodiment.
S22、如图4a所示，应用光刻工艺，将所述多晶硅薄膜层2a刻蚀形成图案化的多晶硅有源层2。其中，所述图案化的多晶硅有源层2正对于下方的图案化的遮光单元9。S22. As shown in FIG. 4a, the polysilicon thin film layer 2a is etched to form a patterned polysilicon active layer 2 by a photolithography process. Wherein, the patterned polysilicon active layer 2 is facing the patterned shading unit 9 below.
进一步地，如图4b所示，应用离子植入工艺对所述多晶硅有源层2进行掺杂处理，使所述多晶硅有源层2从中间向两端依次形成有未掺杂(Undoped)区21、轻掺杂(Lightiy Drain Doping，LDD)区22和重掺杂(Heavily Drain Doping，HDD)区23。具体地，可以采用半色调掩膜工艺或者是灰色调掩膜工艺，分两次对所述多晶硅有源层2进行离子植入掺杂，从而形成所述未掺杂区21、轻掺杂区22和重掺杂区23。Further, as shown in FIG. 4b, the polysilicon active layer 2 is doped by an ion implantation process, so that the polysilicon active layer 2 is sequentially formed with an undoped region from the middle to the both ends. 21. Lightiy Drain Doping (LDD) region 22 and Heavily Drain Doping (HDD) region 23. Specifically, the polysilicon active layer 2 may be doped by ion implantation in a halftone mask process or a gray tone mask process to form the undoped region 21 and the lightly doped region. 22 and heavily doped region 23.
S32、如图4c所示，在所述衬底基板1上沉积形成覆盖所述多晶硅有源层2的栅极绝缘层3。具体地，所述栅极绝缘层3形成在所述缓冲层7上并覆盖所述多晶硅有源层2，所述栅极绝缘层3可以是氧化硅(SiOx)层或氮化硅(SiNx)层或者是氧化硅层与氮化硅层叠加的复合结构层。S32. As shown in FIG. 4c, a gate insulating layer 3 covering the polysilicon active layer 2 is deposited on the base substrate 1. Specifically, the gate insulating layer 3 is formed on the buffer layer 7 to cover the polysilicon active layer 2, the gate insulating layer 3 may be a silicon oxide (SiO x) layer or a silicon nitride (SiN The x ) layer is a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
S42、如图4d所示，应用离子植入工艺，从所述栅极绝缘层3的上方注入氮离子，在所述多晶硅有源层2的表面上形成离子注入层6a。S42. As shown in FIG. 4d, an ion implantation process is applied, nitrogen ions are implanted from above the gate insulating layer 3, and an ion implantation layer 6a is formed on the surface of the polysilicon active layer 2.
S5、如图4e所示，在所述栅极绝缘层3上依次制备形成栅电极4和层间介质层8。该步骤参照实施例2中的步骤S5进行。S5. As shown in FIG. 4e, a gate electrode 4 and an interlayer dielectric layer 8 are sequentially formed on the gate insulating layer 3. This step is carried out with reference to step S5 in the second embodiment.
S6、如图4f所示，应用高温退火工艺对上述步骤制备得到的器件结构进行退火，使所述离子注入层6a重结晶，在所述多晶硅有源层2和所述栅极绝缘层3之间形成氮化硅间隔层6。该步骤参照实施例2中的步骤S6进行。S6, as shown in FIG. 4f, the device structure prepared in the above step is annealed by a high temperature annealing process to recrystallize the ion implantation layer 6a, and the polysilicon active layer 2 and the gate insulating layer 3 are A silicon nitride spacer layer 6 is formed therebetween. This step is carried out with reference to step S6 in the second embodiment.
在完成上述步骤之后，参照实施例2中的步骤S7和S8，在所述层间介质层8上制备形成图案化的源电极5a和漏电极5b，所述源电极5a通过所述第一过孔 81连接到所述多晶硅有源层2的其中一端的重掺杂区23，所述漏电极5b通过所述第二过孔5b连接到所述多晶硅有源层2的另一端的重掺杂区23，最后制备得到的低温多晶硅薄膜晶体管如图3k所示。After the above steps are completed, referring to steps S7 and S8 in Embodiment 2, a patterned source electrode 5a and a drain electrode 5b are formed on the interlayer dielectric layer 8, and the source electrode 5a passes through the first pass. Hole 81 is connected to the heavily doped region 23 of one end of the polysilicon active layer 2, and the drain electrode 5b is connected to the heavily doped region of the other end of the polysilicon active layer 2 through the second via 5b 23. The finally prepared low temperature polysilicon thin film transistor is shown in Figure 3k.
综上所述，本发明实施例提供的低温多晶硅薄膜晶体管及其制备方法，在多晶硅有源层和栅极绝缘层的连接界面制备形成氮化硅间隔层，所述氮化硅间隔层是通过离子植入工艺和高温退火工艺制备形成在多晶硅有源层的表面上，与多晶硅有源层是一体相互连接的结构，其缺陷密度远远小于栅极绝缘层的缺陷密度。所述氮化硅间隔层减小了多晶硅有源层和栅极绝缘层连接界面的缺陷密度，降低了薄膜晶体管的漏电流，增大击穿电压，使得薄膜晶体管具有良好且稳定的电性能，进一地也提高了最终产品(例如LCD或OLED)的品质。In summary, the low temperature polysilicon thin film transistor and the preparation method thereof are provided in the embodiment of the present invention, and a silicon nitride spacer layer is formed at a connection interface between the polysilicon active layer and the gate insulating layer, and the silicon nitride spacer layer is passed through The ion implantation process and the high temperature annealing process are formed on the surface of the polysilicon active layer, and are integrally connected to the polysilicon active layer, and the defect density is much smaller than the defect density of the gate insulating layer. The silicon nitride spacer layer reduces the defect density of the connection interface between the polysilicon active layer and the gate insulating layer, reduces the leakage current of the thin film transistor, increases the breakdown voltage, and enables the thin film transistor to have good and stable electrical properties. Further improvements in the quality of the final product (such as LCD or OLED).
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个......”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。It should be noted that, in this context, relational terms such as first and second are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these entities or operations. There is any such actual relationship or order between them. Furthermore, the term "comprises" or "comprises" or "comprises" or any other variations thereof is intended to encompass a non-exclusive inclusion, such that a process, method, article, or device that comprises a plurality of elements includes not only those elements but also Other elements, or elements that are inherent to such a process, method, item, or device. An element that is defined by the phrase "comprising a ..." does not exclude the presence of additional equivalent elements in the process, method, item, or device that comprises the element.
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。 The above description is only a specific embodiment of the present application, and it should be noted that those skilled in the art can also make several improvements and retouchings without departing from the principles of the present application. It should be considered as the scope of protection of this application.

Claims (15)

  1. 一种低温多晶硅薄膜晶体管的制备方法，其中，包括：A method for preparing a low temperature polysilicon thin film transistor, comprising:
    在衬底基板上依次制备形成多晶硅有源层和覆盖所述多晶硅有源层的栅极绝缘层；Forming a polysilicon active layer and a gate insulating layer covering the polysilicon active layer sequentially on the base substrate;
    应用离子植入工艺，在所述多晶硅有源层的朝向所述栅极绝缘层的表面上注入氮离子，形成离子注入层；Applying an ion implantation process to implant a nitrogen ion on a surface of the polysilicon active layer facing the gate insulating layer to form an ion implantation layer;
    应用高温退火工艺，使所述离子注入层重结晶，在所述多晶硅有源层和所述栅极绝缘层之间形成氮化硅间隔层。The ion implantation layer is recrystallized by a high temperature annealing process to form a silicon nitride spacer layer between the polysilicon active layer and the gate insulating layer.
  2. 根据权利要求1所述的低温多晶硅薄膜晶体管的制备方法，其中，所述制备方法包括步骤：The method of fabricating a low temperature polysilicon thin film transistor according to claim 1, wherein the preparation method comprises the steps of:
    S1、在衬底基板上制备形成多晶硅薄膜层；S1, preparing a polysilicon film layer on the substrate;
    S21、应用离子植入工艺，在所述多晶硅薄膜层的表面上注入氮离子，形成离子注入层；S21, applying an ion implantation process, implanting nitrogen ions on the surface of the polysilicon film layer to form an ion implantation layer;
    S31、将所述多晶硅薄膜层刻蚀形成图案化的多晶硅有源层，所述多晶硅有源层的表面上保留所述离子注入层；S31, etching the polysilicon thin film layer to form a patterned polysilicon active layer, the ion implantation layer is retained on a surface of the polysilicon active layer;
    S41、在所述衬底基板上沉积形成覆盖所述多晶硅有源层的栅极绝缘层；S41, depositing a gate insulating layer covering the polysilicon active layer on the substrate;
    S5、在所述栅极绝缘层上依次制备形成栅电极和层间介质层；S5, sequentially forming a gate electrode and an interlayer dielectric layer on the gate insulating layer;
    S6、应用高温退火工艺，使所述离子注入层重结晶，在所述多晶硅有源层和所述栅极绝缘层之间形成氮化硅间隔层；S6, applying a high temperature annealing process, recrystallizing the ion implantation layer, forming a silicon nitride spacer layer between the polysilicon active layer and the gate insulating layer;
    S7、在所述层间介质层和所述栅极绝缘层中刻蚀形成暴露出所述多晶硅有源层的第一过孔和第二过孔；S7, etching in the interlayer dielectric layer and the gate insulating layer to form a first via and a second via exposing the active layer of the polysilicon;
    S8、在所述层间介质层上制备形成图案化的源电极和漏电极，所述源电极通过所述第一过孔连接到所述多晶硅有源层，所述漏电极通过所述第二过孔连接到所述多晶硅有源层。S8, preparing a patterned source electrode and a drain electrode on the interlayer dielectric layer, wherein the source electrode is connected to the polysilicon active layer through the first via hole, and the drain electrode passes the second layer A via is connected to the polysilicon active layer.
  3. 根据权利要求2所述的低温多晶硅薄膜晶体管的制备方法，其中，步骤S1具体包括： The method of fabricating a low-temperature polysilicon thin film transistor according to claim 2, wherein the step S1 specifically comprises:
    S11、在所述衬底基底上依次沉积缓冲层和非晶硅薄膜层；S11, sequentially depositing a buffer layer and an amorphous silicon film layer on the substrate substrate;
    S12、应用准分子激光退火工艺进行处理，使所述非晶硅薄膜层结晶形成多晶硅薄膜层。S12: processing by using an excimer laser annealing process to crystallize the amorphous silicon film layer to form a polysilicon film layer.
  4. 根据权利要求3所述的低温多晶硅薄膜晶体管的制备方法，其中，所述缓冲层包括依次形成在所述衬底基底上的氮化硅层和氧化硅层。The method of manufacturing a low temperature polysilicon thin film transistor according to claim 3, wherein the buffer layer comprises a silicon nitride layer and a silicon oxide layer sequentially formed on the substrate substrate.
  5. 根据权利要求3所述的低温多晶硅薄膜晶体管的制备方法，其中，在进行步骤S1之前还包括步骤：The method of fabricating a low temperature polysilicon thin film transistor according to claim 3, further comprising the steps of: before performing step S1:
    S0、在所述衬底基底上制备形成图案化的遮光单元，所述遮光单元正对于后续工艺中制备形成的图案化的多晶硅有源层。S0, preparing a patterned light-shielding unit on the substrate substrate, the light-shielding unit being prepared for a patterned polysilicon active layer formed in a subsequent process.
  6. 根据权利要求3所述的低温多晶硅薄膜晶体管的制备方法，其中，在制备形成所述图案化的多晶硅有源层之后，应用离子植入工艺对所述多晶硅有源层进行掺杂处理，使所述多晶硅有源层从中间向两端依次形成有未掺杂区、轻掺杂区和重掺杂区；其中，所述源电极电性连接到所述多晶硅有源层的其中一端的重掺杂区，所述漏电极电性连接到所述多晶硅有源层的另一端的重掺杂区。The method of fabricating a low temperature polysilicon thin film transistor according to claim 3, wherein after preparing the patterned polysilicon active layer, the polysilicon active layer is doped by an ion implantation process to The polysilicon active layer is sequentially formed with an undoped region, a lightly doped region, and a heavily doped region from the middle to the both ends; wherein the source electrode is electrically connected to the heavy doping of one end of the polysilicon active layer The impurity region is electrically connected to the heavily doped region at the other end of the polysilicon active layer.
  7. 根据权利要求2所述的低温多晶硅薄膜晶体管的制备方法，其中，所述栅极绝缘层为氧化硅层或氮化硅层或者是氧化硅层与氮化硅层叠加的复合结构层。The method of fabricating a low temperature polysilicon thin film transistor according to claim 2, wherein the gate insulating layer is a silicon oxide layer or a silicon nitride layer or a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
  8. 一种低温多晶硅薄膜晶体管的制备方法，其中，所述制备方法包括步骤：A method for preparing a low temperature polysilicon thin film transistor, wherein the preparation method comprises the steps of:
    S1、在衬底基板上制备形成多晶硅薄膜层；S1, preparing a polysilicon film layer on the substrate;
    S22、将所述多晶硅薄膜层刻蚀形成图案化的多晶硅有源层；S22, etching the polysilicon thin film layer to form a patterned polysilicon active layer;
    S32、在所述衬底基板上沉积形成覆盖所述多晶硅有源层的栅极绝缘层；S32, depositing a gate insulating layer covering the polysilicon active layer on the substrate;
    S42、应用离子植入工艺，从所述栅极绝缘层的上方注入氮离子，在所述多晶硅有源层的表面上形成离子注入层；S42, applying an ion implantation process, implanting nitrogen ions from above the gate insulating layer, forming an ion implantation layer on a surface of the polysilicon active layer;
    S5、在所述栅极绝缘层上依次制备形成栅电极和层间介质层；S5, sequentially forming a gate electrode and an interlayer dielectric layer on the gate insulating layer;
    S6、应用高温退火工艺，使所述离子注入层重结晶，在所述多晶硅有源层和所述栅极绝缘层之间形成氮化硅间隔层；S6, applying a high temperature annealing process, recrystallizing the ion implantation layer, forming a silicon nitride spacer layer between the polysilicon active layer and the gate insulating layer;
    S7、在所述层间介质层和所述栅极绝缘层中刻蚀形成暴露出所述多晶硅有 源层的第一过孔和第二过孔；S7, etching and forming in the interlayer dielectric layer and the gate insulating layer to expose the polysilicon a first via and a second via of the source layer;
    S8、在所述层间介质层上制备形成图案化的源电极和漏电极，所述源电极通过所述第一过孔连接到所述多晶硅有源层，所述漏电极通过所述第二过孔连接到所述多晶硅有源层。S8, preparing a patterned source electrode and a drain electrode on the interlayer dielectric layer, wherein the source electrode is connected to the polysilicon active layer through the first via hole, and the drain electrode passes the second layer A via is connected to the polysilicon active layer.
  9. 根据权利要求8所述的低温多晶硅薄膜晶体管的制备方法，其中，步骤S1具体包括：The method of fabricating a low-temperature polysilicon thin film transistor according to claim 8, wherein the step S1 specifically comprises:
    S11、在所述衬底基底上依次沉积缓冲层和非晶硅薄膜层；S11, sequentially depositing a buffer layer and an amorphous silicon film layer on the substrate substrate;
    S12、应用准分子激光退火工艺进行处理，使所述非晶硅薄膜层结晶形成多晶硅薄膜层。S12: processing by using an excimer laser annealing process to crystallize the amorphous silicon film layer to form a polysilicon film layer.
  10. 根据权利要求9所述的低温多晶硅薄膜晶体管的制备方法，其中，所述缓冲层包括依次形成在所述衬底基底上的氮化硅层和氧化硅层。The method of manufacturing a low temperature polysilicon thin film transistor according to claim 9, wherein the buffer layer comprises a silicon nitride layer and a silicon oxide layer sequentially formed on the substrate substrate.
  11. 根据权利要求9所述的低温多晶硅薄膜晶体管的制备方法，其中，在进行步骤S1之前还包括步骤：The method of fabricating a low temperature polysilicon thin film transistor according to claim 9, wherein the step further comprises: before performing step S1:
    S0、在所述衬底基底上制备形成图案化的遮光单元，所述遮光单元正对于后续工艺中制备形成的图案化的多晶硅有源层。S0, preparing a patterned light-shielding unit on the substrate substrate, the light-shielding unit being prepared for a patterned polysilicon active layer formed in a subsequent process.
  12. 根据权利要求9所述的低温多晶硅薄膜晶体管的制备方法，其中，在制备形成所述图案化的多晶硅有源层之后，应用离子植入工艺对所述多晶硅有源层进行掺杂处理，使所述多晶硅有源层从中间向两端依次形成有未掺杂区、轻掺杂区和重掺杂区；其中，所述源电极电性连接到所述多晶硅有源层的其中一端的重掺杂区，所述漏电极电性连接到所述多晶硅有源层的另一端的重掺杂区。The method of fabricating a low temperature polysilicon thin film transistor according to claim 9, wherein after preparing the patterned polysilicon active layer, the polysilicon active layer is doped by an ion implantation process to The polysilicon active layer is sequentially formed with an undoped region, a lightly doped region, and a heavily doped region from the middle to the both ends; wherein the source electrode is electrically connected to the heavy doping of one end of the polysilicon active layer The impurity region is electrically connected to the heavily doped region at the other end of the polysilicon active layer.
  13. 根据权利要求8所述的低温多晶硅薄膜晶体管的制备方法，其中，所述栅极绝缘层为氧化硅层或氮化硅层或者是氧化硅层与氮化硅层叠加的复合结构层。The method of fabricating a low temperature polysilicon thin film transistor according to claim 8, wherein the gate insulating layer is a silicon oxide layer or a silicon nitride layer or a composite structural layer in which a silicon oxide layer and a silicon nitride layer are stacked.
  14. 一种低温晶硅薄膜晶体管，包括依次设置在衬底基板上的多晶硅有源层、栅极绝缘层、栅电极、源电极和漏电极，其中，所述多晶硅有源层和所述栅极绝缘层之间的连接界面形成有氮化硅间隔层，所述氮化硅间隔层与所述多晶硅有源层是一体相互连接的结构。 A low temperature crystalline silicon thin film transistor comprising a polysilicon active layer, a gate insulating layer, a gate electrode, a source electrode and a drain electrode sequentially disposed on a substrate, wherein the polysilicon active layer and the gate are insulated The connection interface between the layers is formed with a silicon nitride spacer layer, and the silicon nitride spacer layer and the polysilicon active layer are integrally connected to each other.
  15. 根据权利要求14所述的低温晶硅薄膜晶体管，其中，所述氮化硅间隔层是在所述多晶硅有源层的表面上通过离子植入工艺和高温退火工艺制备形成，所述栅极绝缘层是通过沉积工艺形成在所述多晶硅有源层上，所述氮化硅间隔层的缺陷密度小于所述栅极绝缘层的缺陷密度。 The low-temperature crystalline silicon thin film transistor according to claim 14, wherein the silicon nitride spacer layer is formed on an surface of the polysilicon active layer by an ion implantation process and a high-temperature annealing process, the gate insulation A layer is formed on the polysilicon active layer by a deposition process, and a defect density of the silicon nitride spacer layer is smaller than a defect density of the gate insulating layer.
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