JP4683696B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor film having a crystal structure formed over a substrate having an insulating surface, and a method for manufacturing a semiconductor device using the semiconductor film as an active layer. In particular, the present invention relates to a method for manufacturing a thin film transistor in which an active layer is formed using a crystalline semiconductor layer. Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, an electro-optical device typified by an active matrix liquid crystal display device formed using thin film transistors, and its An electronic device equipped with such an electro-optical device falls under the category of a semiconductor device.
[0002]
[Prior art]
Thin film transistors (hereinafter referred to as thin film transistors) in which an amorphous semiconductor layer is formed on a light-transmitting insulating substrate such as glass and the active layer is a crystalline semiconductor layer crystallized by laser annealing or thermal annealing. , Written as TFT). As the insulating substrate, a glass substrate such as barium borosilicate glass or alumino borosilicate glass is often used. Although such a glass substrate is inferior in heat resistance to a quartz substrate, but has a low commercial price, it has an advantage that a large-area substrate can be easily manufactured.
[0003]
The laser annealing method is known as a crystallization technique that does not raise the temperature of a glass substrate so much and can crystallize only an amorphous semiconductor layer by applying high energy. In particular, an excimer laser capable of obtaining a large output of light having a short wavelength is considered to be most suitable for this application. In the laser annealing method using an excimer laser, a laser beam is processed by an optical system so as to be spot-like or linear on the irradiated surface, and the irradiated surface is scanned with the processed laser light (laser light irradiation). The irradiation position is moved relative to the irradiated surface). For example, the excimer laser annealing method using linear laser light can also perform laser annealing of the entire irradiated surface by scanning only in the direction perpendicular to the longitudinal direction, and is excellent in productivity. It is becoming mainstream as a display device manufacturing technology. The technology enables a monolithic liquid crystal display device in which a pixel TFT for forming a pixel portion on a single glass substrate and a TFT for a driving circuit provided around the pixel portion are formed.
[0004]
However, the crystalline semiconductor layer produced by the laser annealing method is formed by aggregating a plurality of crystal grains, and the positions and sizes of the crystal grains are random. A TFT manufactured on a glass substrate is formed by separating a crystalline semiconductor layer into an island-like pattern for element isolation. In that case, the crystal grain position and size could not be specified and formed. At the crystal grain interface (grain boundary), the current transport characteristics of the carrier deteriorate due to the influence of recombination centers, trap centers, and potential levels at the grain boundaries due to amorphous structures and crystal defects. was there. However, it has been almost impossible to form a channel formation region in which the properties of the crystal significantly affect the characteristics of the TFT with a single crystal grain by eliminating the influence of the grain boundary. For this reason, TFTs having a crystalline silicon film as an active layer have not been obtained to date with characteristics equivalent to those of MOS transistors fabricated on a single crystal silicon substrate.
[0005]
In order to solve such problems, attempts have been made to grow crystal grains greatly. For example, "" High-Mobility Poly-Si Thin-Film Transistors Fabricated by a Novel Excimer Laser Crystallization Method ", K. Shimizu, O. Sugiura and M. Matumura, IEEE Transactions on Electron Devices vol.40, No.1, pp112 -117,1993 "includes Si / SiO2 on the substrate. ₂ There is a report on a dual beam laser annealing method in which a film having a three-layer structure of / Si is formed and excimer laser light is irradiated from both the film side and the substrate side. According to the method, it is shown that the crystal grains can be enlarged by irradiating laser light with a certain predetermined energy intensity.
[0006]
[Problems to be solved by the invention]
In a monolithic liquid crystal display device, a pixel portion that performs image display and a drive circuit are formed over the same substrate. A pixel TFT and a storage capacitor are provided in the pixel portion, and a drive circuit is configured by a shift register circuit, a level shifter circuit, a buffer circuit, a sampling circuit, and the like that are formed based on a CMOS circuit. However, the operating conditions of the pixel TFT and the TFT of the driving circuit are not the same, and therefore, the characteristics required for the TFT are not a little different. For example, the pixel TFT functions as a switch element, and is driven by applying a voltage to the liquid crystal. Since the liquid crystal is driven by alternating current, a method called frame inversion driving is often employed. In this method, in order to keep power consumption low, a characteristic required for the pixel TFT is to sufficiently reduce an off-current value (a drain current that flows when the TFT is turned off). On the other hand, since a high drive voltage is applied to the buffer circuit of the control circuit, it is necessary to increase the withstand voltage so as not to break even when a high voltage is applied. In order to increase the current driving capability, it is necessary to secure a sufficient on-current value (drain current that flows when the TFT is on).
[0007]
In addition, in order to control the threshold voltage (hereinafter referred to as Vth), which is an important characteristic parameter in the TFT, within a predetermined range, in addition to controlling the valence electrons in the channel formation region, the threshold voltage is closely It is necessary to reduce the charge defect density of the base film, the gate insulating film, and the interlayer insulating film formed of the insulating film, and to consider the balance of the internal stress. In response to such a requirement, a material containing silicon as a constituent element, such as a silicon oxide film or a silicon oxynitride film, was suitable.
[0008]
Thus, in order to improve the performance of the monolithic liquid crystal display device, it is not sufficient to improve the performance of the TFT only by increasing the crystal grains of the crystalline semiconductor layer forming the active layer. It was necessary to consider the characteristics of the layer and the underlying film, gate insulating film, and interlayer insulating film formed above and below the layer.
[0009]
The present invention is a technique for solving such a problem. A semiconductor region formed in an island-like pattern is formed as a single crystal or a region that can be regarded as a single crystal, and various characteristics of the TFT are stabilized. The object is to realize a stack structure that can be used simultaneously. Furthermore, in a semiconductor device typified by a monolithic liquid crystal display device in which a plurality of functional circuits are formed on the same substrate, it is possible to arrange TFTs with appropriate performance according to the specifications required by the functional circuits. The purpose is to greatly improve the operating characteristics and reliability.
[0010]
[Means for Solving the Problems]
Laser annealing is used as a method for forming a crystalline semiconductor layer from an amorphous semiconductor layer formed on a substrate such as glass. In the laser annealing method of the present invention, a pulse oscillation type or continuous light emission type excimer laser or argon laser is used as a light source, and a laser beam linearly formed by an optical system is in contact with a base film of a semiconductor layer. Irradiate from both the surface and the second surface on the opposite side.
[0011]
FIG. 3A is a diagram showing the configuration of such a laser annealing apparatus. The laser annealing apparatus includes a laser oscillator 1201, an optical system 1100, and a stage 1202 for fixing the substrate. A heater 1203 and a heater controller 1204 are added to the stage 1202, and the substrate can be heated to 100 to 450 ° C. . A reflective plate 1205 is provided on the stage 1202, and a substrate 1206 is set thereon. A method for holding the substrate 1206 in the structure of the laser annealing apparatus having the structure shown in FIG. 3A will be described with reference to FIG. The substrate 1206 held on the stage 1202 is placed in the reaction chamber 1213 and irradiated with laser light. The reaction chamber can be in a reduced pressure state or an inert gas atmosphere by an exhaust system or a gas system not shown, and can be heated to 100 to 450 ° C. without contaminating the semiconductor film. The stage 1202 can move in the reaction chamber along the guide rail 1216, and the entire surface of the substrate can be irradiated with linear laser light. The laser light is incident from a quartz window (not shown) provided on the upper surface of the substrate 1206. In FIG. 3B, a transfer chamber 1210, an intermediate chamber 1211, and a load / unload chamber 1212 are connected to the reaction chamber 1213 and separated by gate valves 1217 and 1218. A cassette 1214 capable of holding a plurality of substrates is installed in the load / unload chamber 1212, and the substrates are transferred by a transfer robot 1215 provided in the transfer chamber 1210. A substrate 1206 represents the substrate being transferred. With such a configuration, laser annealing can be continuously processed under reduced pressure or in an inert gas atmosphere.
[0012]
2A and 2B are views for explaining the optical system configuration of the laser annealing apparatus shown in FIG. An excimer laser, an argon laser, or the like is applied to the laser oscillator 1101. FIG. 2A is a side view of the optical system 1100, and the laser light emitted from the laser oscillator 1101 is divided in the vertical direction by the cylindrical lens array 1102. The divided laser light is once condensed by the cylindrical lens 1104 and then spread, reflected by the mirror 1107, and then converted into linear laser light on the irradiation surface 1109 by the cylindrical lens 1108. Thereby, the energy distribution in the width direction of the linear laser beam can be made uniform. FIG. 2B is a view of the optical system 1100 as viewed from above, and the laser light emitted from the laser oscillator 1101 is divided in the horizontal direction by the cylindrical lens array 1102. Thereafter, the laser light is combined into one on the irradiation surface 1109 by the cylindrical lens 1105. Thereby, the energy distribution in the longitudinal direction of the linear laser beam can be made uniform.
[0013]
FIG. 1 is a diagram for explaining the concept of the laser annealing method according to the present invention. An insulating film 1002 is formed over a substrate 1001 such as glass, and an island-shaped semiconductor layer 1003 is formed thereover. As the insulating film 1002, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an insulating film containing aluminum, or the like is used, and these films are used alone or in appropriate combination. 2A and 2B, the laser light that has passed through the cylindrical lens 1005 having the same function as the cylindrical lens 1108 is irradiated to the island-shaped semiconductor layer 1003 as linear laser light. The The island-shaped semiconductor layer 1003 is transmitted through the cylindrical lens 1005 and directly irradiated from the second surface of the island-shaped semiconductor layer 1003, the direct laser beam component 1006, the insulating film 1002, and the substrate 1001, and reflected by the reflector 1004. Then, there is a diffused laser light component 1007 that is reflected from the first surface of the island-shaped semiconductor layer 1003 through the substrate 1001 and the insulating film 1002 again. In any case, since the laser light that has passed through the cylindrical lens 1005 has an incident angle of 45 to 90 ° with respect to the substrate surface in the process of being condensed, the laser light reflected by the reflector 1004 is an island-shaped semiconductor. It also reflects in the direction inside the layer 1003. The reflective plate 1004 forms a reflective surface with aluminum or the like. If this reflective surface is a mirror surface, a regular reflectance of about 90% can be obtained in the wavelength range of 240 to 320 nm. Further, when aluminum is used as the material and a fine uneven shape of several hundreds of nanometers is formed on the surface thereof, the diffuse reflectance (integral reflectance-regular reflectance) is 50 to 70%.
[0014]
In this way, the laser light is irradiated from the second surface and the first surface of the substrate 1001, and the island-like semiconductor layer 1003 formed on the substrate 1001 is laser-annealed from both sides. In the laser annealing method, the semiconductor film is instantaneously heated and melted by optimizing the conditions of the laser beam to be irradiated, thereby controlling the generation density of crystal nuclei and the crystal growth from the crystal nuclei. Since the excimer laser oscillation pulse width is several nsec to several hundred nsec, for example 30 nsec, when the pulse oscillation frequency is set to 30 Hz, the semiconductor layer in the region irradiated with the laser beam is instantaneously heated by the pulse laser beam, Cooling is much longer than the heating time.
[0015]
Laser irradiation from only one side of the semiconductor layer formed on the substrate heats only one side, so the cycle of heating and melting and cooling and solidification becomes steep, and the generation density of crystal nuclei is controlled. Even if it is possible, sufficient crystal growth cannot be expected. However, when laser light is irradiated from both sides of the semiconductor layer, this heating and melting and cooling and solidification cycle becomes gradual, and the time allowed for crystal growth in the cooling and solidification process becomes relatively long. Crystal growth can be obtained.
[0016]
At the wavelength of the excimer laser light, the laser light is absorbed only at the outermost surface of the semiconductor layer and converted into heat. For example, in the case of XeCl excimer laser light having a wavelength of 308 nm, most of the light is absorbed and generated in the region from the surface of the silicon layer to 20 nm. Thereafter, the entire silicon layer is annealed by conducting heat from that region to the inner silicon layer. That is, the surface temperature of the silicon layer is always higher than that in other regions while the laser beam is irradiated. This can be inferred from the results obtained from the thermal conduction simulation in laser annealing.
[0017]
Here, it is assumed that when the laser beam is irradiated from one side from the front side and when the laser beam is irradiated from both the front side and the back side, the energy absorbed by the silicon layer and converted into heat is the same. FIG. 26 shows the simulation results of the laser light intensity distribution in the depth direction of the silicon layer for each case of single-sided irradiation and double-sided irradiation. In the case of double-sided irradiation, the case where the ratio of front-side irradiation intensity to back-side irradiation intensity is 3: 1 is shown. As shown in FIG. 26, in the temperature rise process in which laser light is irradiated, in the case of double-sided irradiation, there are two regions that absorb the laser light and generate heat, the front surface side and the base interface side. That is, it is possible to effectively expand the region that generates heat. For this reason, ablation is less likely to occur compared to single-sided irradiation (it is known that ablation occurs above a certain laser energy density when excimer laser light is applied to a semiconductor layer). That is, in the double-sided irradiation, the semiconductor layer can be heated with an effective high energy density without causing ablation in the semiconductor layer.
[0018]
The present invention applies such a laser annealing method (dual beam laser annealing method) to form a region where the island-like semiconductor layer can be regarded as a single crystal or a single crystal, and such an island-like semiconductor layer is activated in the TFT. A semiconductor device having a TFT having a structure corresponding to the function of each circuit is manufactured using the layer.
[0019]
Therefore, in order to solve the above problems, the configuration of the present invention includes a first step of forming a base film in close contact with the substrate, a first surface in contact with the base film on the base film, A second step of forming a first shape amorphous semiconductor layer having a second surface on the opposite side; and irradiating the second surface of the first shape amorphous semiconductor layer with a first laser beam In addition, a second laser beam incident from a peripheral region of the first shape amorphous semiconductor layer and transmitted through the substrate and reflected by a reflecting plate is irradiated from the first surface. In the third step of forming the crystalline semiconductor layer of the first shape and the region overlapping with the gate electrode of the crystalline semiconductor layer of the first shape or the region of forming the channel formation region, Remove 2 μm or more from the edge of the crystalline semiconductor layer to form the second shape crystalline semiconductor layer A fourth step of forming an impurity region of one conductivity type in the second shape crystalline semiconductor layer, and a sixth step of adding hydrogen to the second shape crystalline semiconductor layer. It is characterized by having these processes.
[0020]
According to another aspect of the invention, there is provided a first step of forming a base film in close contact with the substrate, a first surface in contact with the base film on the base film, and a second surface on the opposite side. A second step of forming a first shape amorphous semiconductor layer comprising: a third step of introducing an element that promotes crystallization of a semiconductor into the first shape amorphous semiconductor layer; Irradiating the second surface of the one-shaped amorphous semiconductor layer with the first laser beam and entering from the peripheral region of the first-shaped amorphous semiconductor layer, the light passes through the substrate. A fourth step of irradiating a second laser beam reflected by the reflector from the first surface to form a first-shaped crystalline semiconductor layer; and In the region overlapping with the gate electrode or the region forming the channel formation region, the edge of the crystalline semiconductor layer having the first shape A fifth step of forming a second shape crystalline semiconductor layer by removing 1 μm or more from the first shape, and a sixth step of forming an impurity region of one conductivity type in the second shape crystalline semiconductor layer; And a seventh step of adding hydrogen to the second shape crystalline semiconductor layer.
[0021]
According to another aspect of the invention, there is provided a first step of forming a base film in close contact with a substrate, a second step of forming an amorphous semiconductor layer on the base film, and the amorphous semiconductor layer. An element for promoting crystallization of the amorphous semiconductor, and a third step of forming a crystalline semiconductor film by heat treatment; a first surface in contact with the base film on the base film; and A fourth step of forming a first shape crystalline semiconductor layer having a second surface on the opposite side; and irradiating the second surface of the first shape crystalline semiconductor layer with a first laser beam. And a second laser beam incident from a peripheral region of the crystalline semiconductor layer of the first shape and transmitted through the substrate and reflected by a reflecting plate is irradiated from the first surface. A region overlapping with the gate electrode of the crystalline semiconductor layer of the first shape, or a channel formation region A sixth step of forming a second-shaped crystalline semiconductor layer by removing 1 μm or more from the end of the first-shaped crystalline semiconductor layer in the region to be formed; and the second-shaped crystalline semiconductor layer And a seventh step of forming an impurity region of one conductivity type and an eighth step of adding hydrogen to the crystalline semiconductor layer having the second shape.
[0022]
The above-described structure of the present invention can also be suitably applied to a method for manufacturing a semiconductor device having a p-channel TFT and an n-channel TFT on the same substrate.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
An embodiment of the present invention will be described with reference to FIG. In FIG. 4A, an alkali-free glass substrate such as barium borosilicate glass or alumino borosilicate glass is used for the substrate 401. For example, Corning # 7059 glass or # 1737 glass base can be preferably used. In addition, a plastic substrate having no optical anisotropy such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES) can be used. When a glass substrate is used, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. A base film 402 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed in close contact with one main surface of the substrate 401 on which the TFT is formed in order to prevent impurity diffusion from the substrate 401. For example, SiH by plasma CVD method _Four , NH _Three , N ₂ A silicon oxynitride film 402a made of O is 10 to 200 nm (preferably 50 to 100 nm), similarly SiH. _Four , N ₂ A silicon oxynitride silicon film 402b formed from O is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm).
[0024]
The silicon oxynitride film is formed by using a conventional parallel plate type plasma CVD method. The silicon oxynitride film 402a is made of SiH. _Four 10SCCM, NH _Three To 100 SCCM, N ₂ O was introduced into the reaction chamber as 20 SCCM, the substrate temperature was 325 ° C., the reaction pressure was 40 Pa, and the discharge power density was 0.41 W / cm. ² The discharge frequency was 60 MHz. On the other hand, the silicon oxynitride silicon film 402b is formed of SiH. _Four 5SCCM, N ₂ O for 120 SCCM, H ₂ Was introduced into the reaction chamber as 125 SCCM, the substrate temperature was 400 ° C., the reaction pressure was 20 Pa, and the discharge power density was 0.41 W / cm. ² The discharge frequency was 60 MHz. These films can be formed continuously only by changing the substrate temperature and switching the reaction gas. It is desirable to stabilize the threshold voltage (Vth) if such a base film is formed so that the internal stress has a tensile stress with respect to the substrate. Further, it is desirable that the internal stress does not change during heat treatment at 400 to 600 ° C.
[0025]
The silicon oxynitride film 402a thus fabricated has a density of 9.28 × 10 ^{twenty two} /cm ^Three And ammonium hydrogen fluoride (NH _Four HF ₂ ) 7.13% and ammonium fluoride (NH _Four F) is a dense and hard film having a slow etching rate of about 63 nm / min at 20 ° C. in a mixed solution containing 15.4% (product name: LAL500, manufactured by Stella Chemifa). When such a film is used for the base film, it is effective to prevent the alkali metal element from the glass substrate from diffusing into the semiconductor layer formed thereon.
[0026]
Next, an amorphous semiconductor layer 403 having an amorphous structure with a thickness of 25 to 80 nm (preferably 30 to 60 nm) is formed by a known method such as a plasma CVD method or a sputtering method. For example, an amorphous silicon film is formed to a thickness of 55 nm by plasma CVD. The semiconductor film having an amorphous structure includes an amorphous semiconductor layer and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. In addition, the base film 102 and the amorphous semiconductor layer 403 can be formed continuously. For example, as described above, after the silicon oxynitride film 402a and the silicon oxynitride silicon film 402b are continuously formed by plasma CVD, the reaction gas is changed to SiH. _Four , N ₂ O, H ₂ To SiH _Four And H ₂ Or SiH _Four If it is switched to only, it can be continuously formed without being once exposed to the air atmosphere. As a result, contamination of the surface of the silicon oxynitride silicon film 402b can be prevented, and variation in characteristics and threshold voltage variation of a TFT to be manufactured can be reduced.
[0027]
Then, as illustrated in FIG. 4B, an island-shaped semiconductor layer 404 having a first shape is formed from the amorphous semiconductor semiconductor layer 403. The first shape can be a square, a rectangle, or an arbitrary polygon, but has a region having a distance from the center to the end of 50 μm or less. This is because laser light is incident on the substrate from the peripheral region of the island-shaped semiconductor layer 403 in the laser annealing step, and the laser light reflected by the reflector placed on the lower side of the substrate is again reflected on the island-shaped semiconductor layer 403. It is a value limited for the purpose of making it incident on the surface of 1 and effectively performing crystallization. If one side is equal to or greater than this value, the reflected laser light does not enter the inside of the island-like semiconductor layer 403, and crystallization is not performed well.
[0028]
Next, crystallization is performed by laser annealing as shown in FIG. In order to crystallize, it is desirable to first release the hydrogen contained in the amorphous semiconductor layer. When heat treatment is performed at 400 to 500 ° C. for about 1 hour to reduce the amount of hydrogen contained to 5 atomic% or less. good. The laser annealing method uses a pulse oscillation type or continuous light emission type excimer laser or argon laser as its light source. The configuration and concept of the apparatus is the same as that described with reference to FIGS. 1 and 3 as described above.
[0029]
The laser annealing conditions are appropriately selected by the practitioner. For example, the pulse oscillation frequency of the excimer laser is 30 Hz, and the laser energy density is 100 to 500 mJ / cm. ² (Typically 300-350mJ / cm ² ) Is irradiated with a linear beam having a line width of 100 to 1000 μm, for example, a line width of 400 μm. Since this line width is larger than that of the island-shaped semiconductor layer 404, the entire surface of the second surface of at least one island-shaped semiconductor layer 404 and the periphery of the island-shaped semiconductor layer 404 are irradiated with a linear beam of one pulse. Can do. A part of the light irradiated with the incident angle θ around the island-like semiconductor layer 404 reaches the lower reflector of the substrate, and a part of the light reflected with the reflection angle θ ′ there The first surface of the semiconductor layer 404 is irradiated. Moreover, you may irradiate several times, scanning a linear beam. At this time, the linear beam superposition ratio (overlap ratio) is preferably set to 50 to 98%. Actually, the number of irradiation pulses is preferably 20 to 40 pulses. The shape of the laser beam can be processed in the same manner even if it is a plane.
[0030]
In such a laser annealing method, light irradiated with an incident angle θ around the island-like semiconductor layer 404 is attenuated by about 50% in the process of passing through the substrate 401. Even if the regular reflectance of the reflector is 90%, the laser light actually irradiated on the first surface of the island-like semiconductor layer 404 is considered to be about 15 to 30% of the direct laser light. However, the island-shaped semiconductor layer 404 is sufficiently heated by the diffused laser beam having such an intensity. As a result, the cooling process of the semiconductor layer melted by the direct laser light and the diffusion laser light becomes gentle, and it is possible to sufficiently achieve crystal growth.
[0031]
This is because the substrate can also be heated to 100 to 450 ° C. by the heater 1203 provided on the stage 1202 shown in FIG. 3A, but the heating of the semiconductor layer by the diffused laser light has an effect higher than this temperature.
[0032]
Further, in order to make the diffused laser light effectively enter the inside of the island-like semiconductor layer 404, the reflector is made of aluminum, a fine uneven shape of several hundred nm is formed on the surface, and the diffuse reflectance is 50 to 70. % Is effective. This is because the scattering angle of the laser light is increased by the fine uneven surface.
[0033]
As a result of laser annealing in this way, as shown in FIG. 4C, the island-shaped semiconductor layer 404 becomes dense by transition from an amorphous structure to a crystalline structure and contracts by about 1 to 15% ( The dotted line in the figure indicates the size of the island-shaped semiconductor layer before annealing). Then, an island-shaped semiconductor layer 405 having a crystal structure is formed. A region 406 in which strain due to shrinkage is accumulated is formed in the periphery of the island-shaped semiconductor layer 405. The strain accumulation region 406 has a number of defect levels such as capture centers and recombination centers, and is therefore not suitable for use in at least a TFT channel formation region. For this purpose, Japanese Patent Application Laid-Open No. 8-228006 discloses a technique for forming an island-shaped semiconductor layer having a new shape by removing such a region where strain around the island-shaped semiconductor layer is accumulated. Therefore, as shown in FIG. 4D, the region 406 in which strain is accumulated is removed by etching to form an island-shaped semiconductor layer 407 (408 shown by a dotted line in the drawing indicates a region removed by etching). .
[0034]
Thereafter, the island-shaped semiconductor layer 407 is subjected to a heat treatment at 300 to 450 ° C. in an atmosphere containing 3 to 100% hydrogen, or a heat treatment at 200 to 450 ° C. in an atmosphere containing hydrogen generated by plasma. Residual defects can be neutralized. The island-shaped semiconductor layer 407 thus manufactured can be suitably used as an active layer of a TFT.
[0035]
[Embodiment 2]
Another embodiment of the present invention will be described with reference to FIG. In FIG. 5A, a substrate 501, a base film 502, and an amorphous semiconductor layer 503 are manufactured in the same manner as in Embodiment Mode 1. Then, as shown in FIG. 5B, an island-shaped semiconductor layer 504 having a first shape is formed from the amorphous semiconductor semiconductor layer 503. Then, an aqueous solution containing a catalytic element of 5 to 100 ppm in terms of weight is applied by a spin coating method to form a layer 505 containing the catalytic element. Catalyst elements include nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), platinum (Pt), copper (Cu), gold (Au). The catalyst element-containing layer 505 may be formed with a thickness of 1 to 5 nm by a sputtering method or a vacuum deposition method in addition to the spin coating method.
[0036]
Laser annealing is performed on the substrate in this state in the same manner as in the first embodiment. As a result, in the island-shaped semiconductor layer 506 having a crystal structure once formed through a molten state by direct laser light and diffusion laser light, the catalytic element is 1 × 10 6. ¹⁷ ~ 1x10 ¹⁹ atoms / cm ^Three Contained at a concentration of about. The catalyst element diffuses while forming silicide in the semiconductor layer during crystallization, and has an effect of promoting crystallization of the semiconductor layer in the process. A crystalline semiconductor layer having higher crystallinity than that of the first embodiment is formed. Make it possible to form. However, even in this case, the island-shaped semiconductor layer 506 is densified and contracted by transition from the amorphous structure to the crystalline structure (the dotted line in the figure indicates the size of the island-shaped semiconductor layer before annealing). In the periphery of the island-shaped semiconductor layer 506, a region 507 in which strain due to shrinkage is accumulated is formed. Accordingly, in this case as well, as shown in FIG. 5D, the region 507 in which strain is accumulated is removed by etching to form an island-shaped semiconductor layer 508 having a second shape (509 indicated by a dotted line in the drawing). Indicates a region removed by etching).
[0037]
Thereafter, the island-shaped semiconductor layer 508 is subjected to a heat treatment at 300 to 450 ° C. in an atmosphere containing 3 to 100% hydrogen, or a heat treatment at 200 to 450 ° C. in an atmosphere containing hydrogen generated by plasma. Residual defects can be neutralized. The island-shaped semiconductor layer 508 thus manufactured can be suitably used as an active layer of a TFT.
[0038]
[Embodiment 3]
The method for producing the island-shaped semiconductor layer having a crystal structure as the active layer of the TFT is not produced only by the laser annealing method, and the laser annealing method and the thermal annealing method according to the present invention may be used in combination. In particular, crystallization by thermal annealing can be realized at a temperature of 600 ° C. or lower when applied to the crystallization method using a catalytic element disclosed in Japanese Patent Application Laid-Open No. 7-130652. When the crystalline semiconductor layer is processed by the laser annealing method according to the present invention, a high-quality crystalline semiconductor layer can be obtained. Such an embodiment will be described with reference to FIG.
[0039]
In FIG. 6A, the glass substrate described in Embodiment 1 can be preferably used as the substrate 601. In addition, the base film 602 and the amorphous semiconductor layer 603 are manufactured in the same manner as in Embodiment Mode 1. In this state, a layer 604 containing a catalytic element is formed on the amorphous semiconductor layer 603 in the same manner as in the second embodiment. Thereafter, heat treatment is first performed at 400 to 500 ° C. for about 1 hour, so that the hydrogen content of the amorphous semiconductor layer is 5 atomic% or less. Then, using a furnace annealing furnace, thermal annealing is performed in a nitrogen atmosphere at 550 to 600 ° C. for 1 to 8 hours, preferably at 550 ° C. for 4 hours. Through the above steps, a crystalline semiconductor layer made of a crystalline silicon film can be obtained (not shown). When the crystalline semiconductor layer produced by this thermal annealing is observed macroscopically by observation with an optical microscope, it may be observed that an amorphous region remains locally. 480cm for Raman spectroscopy ^-1 An amorphous component having a broad peak is observed. However, such an amorphous region can be easily removed by the laser annealing method of the present invention, and a high-quality crystalline semiconductor layer can be obtained.
[0040]
Therefore, the island-shaped semiconductor layer 605 having the first shape is formed from the crystalline semiconductor layer subjected to the above-described thermal annealing. Since the crystalline semiconductor layer is densified and contracted by transition from the amorphous structure to the crystalline structure, the thickness of the crystalline semiconductor layer is larger than the thickness of the amorphous semiconductor layer 603 (indicated by a dotted line 606 in the figure). Is about 1 to 15% thinner (FIG. 6B).
[0041]
Laser annealing is performed on the substrate in this state in the same manner as in the first embodiment. As a result, an island-shaped semiconductor layer 607 having a new crystal structure is formed once in a molten state by direct laser light and diffusion laser light. Even in this case, the island-shaped semiconductor layer 605 is slightly densified and contracted due to an increase in crystallinity (the dotted line in the figure indicates the size of the island-shaped semiconductor layer 605 before laser annealing). A region 608 in which distortion due to contraction is accumulated is formed in the periphery of the layer 607. Further, in the island-shaped semiconductor layer 607, a catalytic element is 1 × 10 6. ¹⁷ ~ 1x10 ¹⁹ atoms / cm ^Three Contained at a concentration of about. Even in this case, as shown in FIG. 6D, the region 608 in which strain is accumulated is removed by etching to form an island-shaped semiconductor layer 609 having a second shape (610 shown by a dotted line in the drawing is etched). To indicate the area removed).
[0042]
Thereafter, similarly, the island-shaped semiconductor layer 609 is subjected to a heat treatment at 300 to 450 ° C. in an atmosphere containing 3 to 100% hydrogen, or a heat treatment at 200 to 450 ° C. in an atmosphere containing hydrogen generated by plasma. It is good to give.
[0043]
[Embodiment 4]
The embodiment described with reference to FIG. 7 is a method of forming a crystalline semiconductor layer of higher quality by crystallizing a semiconductor layer with a temperature gradient in a laser annealing method. In FIG. 7A, a substrate 701 similar to that in Embodiment 1 can be used.
[0044]
On the surface of the substrate 701 on which the TFT is to be formed, a heat conductive layer 702 that is light-transmitting, insulating, and excellent in heat conductivity is formed. The thickness of the heat conductive layer 702 is 50 to 500 nm, and the heat conductivity is 10 Wm. ^-1 K ^-1 That is necessary. Such materials include aluminum oxide (aluminum oxide (Al ₂ O _Three ) Is translucent in visible light and has a thermal conductivity of 20 Wm ^-1 K ^-1 It is suitable. Aluminum oxide is not limited to the stoichiometric ratio, and other elements may be added in order to control characteristics such as thermal conductivity characteristics and internal stress. For example, when aluminum oxide is mixed with nitrogen, aluminum oxynitride (AlN _x O _1-x : 0.02 ≦ x ≦ 0.5) or aluminum nitride (AlN) _x ) Can also be used. Alternatively, a compound containing silicon (Si), oxygen (O), nitrogen (N), and M (M is at least one selected from aluminum (Al) or a rare earth element) can be used. For example, AlSiON or LaSiON can be suitably used. In addition, boron nitride or the like can also be applied. Any of the above oxides, nitrides, and compounds can be formed by sputtering. This can be formed by sputtering using a target having a desired composition and using an inert gas such as argon (Ar) or nitrogen. Also, the thermal conductivity is 1000Wm ^-1 K ^-1 A thin-film diamond layer or a DLC (Diamond Like Carbon) layer that reaches the maximum thickness may be provided.
[0045]
An island-like insulating layer 703 is formed thereon. The thermal conductivity of the island-like insulating layer 703 is 10 Wm ^-1 K ^-1 Use material that is less than. As such a material, a silicon oxide film, a silicon nitride film, or the like can be selected, but a silicon oxynitride film is preferably formed. The silicon oxynitride film is made of SiH by plasma CVD. _Four , N ₂ O is produced as a source gas. O in this source gas ₂ May be added. Although the manufacturing conditions are not limited, the silicon oxynitride film as the island-shaped insulating film 703 has a thickness of 50 to 500 nm, an oxygen concentration of 55 atomic% to less than 70 atomic%, and a nitrogen concentration of 1 atomic% or more. It should be less than 20 atomic%. With such a composition, the internal stress of the silicon oxynitride film is reduced and the fixed charge density is reduced.
[0046]
Next, a semiconductor film 704 having an amorphous structure with a thickness of 25 to 80 nm (preferably 30 to 60 nm) is formed by a known method such as a plasma CVD method or a sputtering method. For example, an amorphous silicon film having a thickness of 55 nm is formed by plasma CVD. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor layer and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. After that, an island-shaped semiconductor layer 705 having a first shape is formed from the semiconductor film 704 having an amorphous structure. This island-shaped semiconductor layer 705 is preferably formed so as to cover the island-shaped insulating layer 703 and have an end portion in contact with the heat conductive layer 702 (FIG. 6B).
[0047]
Then, the island-shaped semiconductor layer 705 is crystallized using a dual beam laser annealing method. In this process, a region where the end portion of the island-shaped semiconductor layer 705 is in contact with the heat conductive layer 702 is rapidly cooled, so that crystal nuclei are first generated in this region, and fine crystal grains are formed in this region. The On the other hand, the semiconductor layer on the island-shaped insulating layer 703 has a relatively gentle change in temperature between heating and cooling, and the semiconductor layer in this region has a relatively gentle crystal grain from the end close to the heat conduction layer 702. Thus, a single crystal grain can be grown over almost the entire surface of the island-shaped insulating layer 703.
[0048]
As a result, as shown in FIG. 7C, the island-like semiconductor layer 705 is densified by the transition from the amorphous structure to the crystalline structure and contracts by about 1 to 15% (the dotted line in the figure indicates the pre-annealing). Shows the size of the island-like semiconductor layer). Then, an island-shaped semiconductor layer 706 having a crystal structure is formed. A region 707 where strain due to shrinkage is accumulated is formed in the periphery of the island-shaped semiconductor layer 706. Since this strain accumulation region 707 has a number of defect levels such as trap centers and recombination centers, it is not suitable to be used at least for a channel formation region of a TFT. Finally, as shown in FIG. 7D, the region 707 in which strain is accumulated is removed by etching to form an island-shaped semiconductor layer 708 having a second shape (709 shown by a dotted line in the drawing is etched). To indicate the area removed).
[0049]
Thereafter, similarly, the island-shaped semiconductor layer 708 is subjected to a heat treatment at 300 to 450 ° C. in an atmosphere containing 3 to 100% hydrogen, or a heat treatment at 200 to 450 ° C. in an atmosphere containing hydrogen generated by plasma. It is good to give. As described above, in the present embodiment, an example in which the method of providing a thermal conductive layer on the base film and using the temperature gradient of the semiconductor layer is applied to the laser annealing method described in the first embodiment has been described. The method may be performed in combination with Embodiment 2 or Embodiment 3.
[0050]
【Example】
[Example 1]
An embodiment of the present invention will be described with reference to FIGS. Here, a method for simultaneously manufacturing a pixel TFT and a storage capacitor in a pixel portion and an n-channel TFT and a p-channel TFT in a driver circuit provided around the pixel portion will be described according to steps.
[0051]
In FIG. 8A, the substrate 101 includes a glass substrate such as barium borosilicate glass or alumino borosilicate glass represented by Corning # 7059 glass or # 1737 glass, and a crystallization or activation process. Can be performed only by laser annealing, a plastic substrate having no optical anisotropy, such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES) can be used. When a glass substrate is used, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. Then, a base film 102 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 101 on which the TFT is formed in order to prevent impurity diffusion from the substrate 101. For example, SiH by plasma CVD method _Four , NH _Three , N ₂ A silicon oxynitride film 102a made of O is 10 to 200 nm (preferably 50 to 100 nm), similarly SiH. _Four , N ₂ A silicon oxynitride silicon film 102b formed from O is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm).
[0052]
The silicon oxynitride film is formed by using a conventional parallel plate type plasma CVD method. The silicon oxynitride film 102a is made of SiH. _Four 10SCCM, NH _Three To 100 SCCM, N ₂ O was introduced into the reaction chamber as 20 SCCM, the substrate temperature was 325 ° C., the reaction pressure was 40 Pa, and the discharge power density was 0.41 W / cm. ² The discharge frequency was 60 MHz. On the other hand, the silicon oxynitride silicon film 102b is made of SiH. _Four 5SCCM, N ₂ O for 120 SCCM, H ₂ Was introduced into the reaction chamber as 125 SCCM, the substrate temperature was 400 ° C., the reaction pressure was 20 Pa, and the discharge power density was 0.41 W / cm. ² The discharge frequency was 60 MHz. These films can be formed continuously only by changing the substrate temperature and switching the reaction gas.
[0053]
Further, the silicon oxynitride film 102a is formed so that the internal stress becomes tensile stress with the substrate as the center. The silicon oxynitride silicon film 102b is also given internal stress in the same direction, but is smaller than the silicon oxynitride film 102a in absolute value.
[0054]
Next, a semiconductor layer 103 having an amorphous structure with a thickness of 25 to 80 nm (preferably 30 to 60 nm) is formed by a known method such as a plasma CVD method or a sputtering method. For example, an amorphous silicon film is formed to a thickness of 55 nm by plasma CVD. The semiconductor film having an amorphous structure includes an amorphous semiconductor layer and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. In addition, the base film 102 and the amorphous semiconductor layer 103 can be formed continuously. For example, as described above, after the silicon oxynitride film 102a and the silicon oxynitride silicon film 102b are continuously formed by the plasma CVD method, the reaction gas is changed to SiH. _Four , N ₂ O, H ₂ To SiH _Four And H ₂ Or SiH _Four If it is switched to only, it can be continuously formed without being once exposed to the air atmosphere. As a result, contamination of the surface of the silicon oxynitride silicon film 102b can be prevented, and variation in characteristics and threshold voltage of the manufactured TFT can be reduced.
[0055]
Then, first, island-shaped semiconductor layers 104 to 108 having a first shape are formed from the semiconductor layer 103 having an amorphous structure as indicated by a dotted line in FIG. FIG. 11A is a top view of the island-shaped semiconductor layers 104 and 105 in this state, and similarly, FIG. 12A shows a top view of the island-shaped semiconductor layer 108. In FIGS. 11 and 12, the island-shaped semiconductor layer is rectangular and is formed so that one side is 50 μm or less. However, the shape of the island-shaped semiconductor layer can be arbitrary, and preferably from the center to the end. Any polygon or circle can be used as long as the minimum distance to the part is 50 μm or less.
[0056]
Next, a crystallization process is performed on such island-shaped semiconductor layers 104 to 108. Any method described in Embodiments 1 to 4 can be applied to the crystallization step. In any case, by applying the dual beam laser annealing method according to the present invention, island-like semiconductor layers 109 to 113 made of a crystalline silicon film indicated by a solid line in FIG. 8B are newly formed. In this case as well, the film becomes dense as the amorphous silicon film is crystallized and contracts by about 1 to 15%. Therefore, the island-like semiconductor layer made of such a crystalline silicon film has a tensile stress with the substrate as the center. Further, in the region around the island-shaped semiconductor layers 109 to 113, a region 114 in which strain is accumulated by this contraction is formed. 11B and 12B are top views of the island-shaped semiconductor layers 109, 110, and 113 in this state, respectively. In the drawing, regions 104, 105, and 108 indicated by dotted lines indicate the sizes of the original island-shaped semiconductor layers 104, 105, and 108, respectively.
[0057]
When the TFT gate electrode is formed over the region 114 where such strain is accumulated, the TFT has a large number of defect levels as described above, and the crystallinity is not good. Cause. For example, the off-current value (current value that flows when the TFT is off) increases, or the current concentrates in this region and locally generates heat. Therefore, as shown in FIG. 8C, the second shape island-shaped semiconductor layers 115 to 119 are formed so that the region 114 in which such strain is accumulated is removed. 114 ′ indicated by a dotted line in the figure is a region where the region 114 where strain is accumulated exists, and shows a state where island-shaped semiconductor layers 115 to 119 having the second shape are formed inside the region 114 ′. The shape of the second shape island-shaped semiconductor layers 115 to 119 may be an arbitrary shape. FIG. 11C is a top view of the island-shaped semiconductor layers 115 and 114 in this state. Similarly, FIG. 12C shows a top view of the island-shaped semiconductor layer 119.
[0058]
Thereafter, a mask layer 137 made of a silicon oxide film having a thickness of 50 to 100 nm is formed by plasma CVD method or sputtering method so as to cover the island-like semiconductor layers 115 to 119.
[0059]
In this state, an impurity element imparting p-type is added to the island-like semiconductor layer for the purpose of controlling the threshold voltage (Vth) of the TFT by 1 × 10 ¹⁶ ~ 5x10 ¹⁷ atoms / cm ^Three You may add to the whole surface of an island-like semiconductor layer with a density | concentration of a grade. As an impurity element imparting p-type to a semiconductor, elements of Group 13 of the periodic table such as boron (B), aluminum (Al), and gallium (Ga) are known. As the method, an ion implantation method or an ion doping method can be used, but an ion doping method is suitable for processing a large-area substrate. In the ion doping method, diborane (B ₂ H ₆ ) As a source gas and boron (B) is added. Such implantation of the impurity element is not always necessary and may be omitted. However, this is a technique that is particularly suitable for keeping the threshold voltage of the n-channel TFT within a predetermined range.
[0060]
In order to form the LDD region of the n-channel TFT of the driver circuit, an impurity element imparting n-type conductivity is selectively added to the island-like semiconductor layers 116 and 118. Therefore, resist masks 120a to 120e are formed in advance. As the impurity element imparting n-type conductivity, phosphorus (P) or arsenic (As) may be used. Here, phosphorous (PH) is added to add phosphorus (P). _Three ) Was applied. The formed impurity regions are low-concentration n-type impurity regions 121 and 122, and the phosphorus (P) concentration is 2 × 10. ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three It may be in the range. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 121 and 122 formed here is defined as (n ^- ). The impurity region 123 is a semiconductor layer for forming a storage capacitor of the pixel matrix circuit, and phosphorus (P) is added to this region at the same concentration (FIG. 8D).
[0061]
Next, a step of activating the added impurity element is performed. The activation can be performed by a heat treatment at 500 to 600 ° C. for 1 to 4 hours or a laser activation method in a nitrogen atmosphere. Moreover, you may carry out using both together. In the case of the laser activation method, a KrF excimer laser beam (wavelength 248 nm) is used to form a linear beam, the oscillation frequency is 5 to 50 Hz, and the energy density is 100 to 500 mJ / cm. ² As a result, the entire surface of the substrate on which the island-shaped semiconductor layer was formed was processed by scanning the linear beam with an overlap ratio of 80 to 98%. Note that there are no particular limitations on the irradiation conditions of the laser beam, and the practitioner may make an appropriate decision. The mask layer 137 is etched away with a solution such as hydrofluoric acid at this stage.
[0062]
In FIG. 8E, the gate insulating film 127 is formed using an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. For example, it is preferable to form a silicon oxynitride film with a thickness of 120 nm. SiH _Four And N ₂ O to O ₂ A silicon oxynitride film manufactured by adding N is a preferable material for this application because the fixed charge density in the film is reduced. Needless to say, the gate insulating film 127 is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. In any case, the gate insulating film 127 is formed so as to have a compressive stress with the substrate as the center.
[0063]
Then, as shown in FIG. 8E, a heat resistant conductive layer for forming a gate electrode is formed over the gate insulating film 127. Although the heat-resistant conductive layer may be formed as a single layer, it may have a laminated structure including a plurality of layers such as two layers or three layers as necessary. Using such a heat-resistant conductive material, for example, a structure in which a conductive layer (A) 124 made of a conductive nitride metal film and a conductive layer (B) 125 made of a metal film are stacked may be used. The conductive layer (B) 125 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the element as a main component, or an alloy film in which the elements are combined. (Typically, a Mo—W alloy film or a Mo—Ta alloy film) may be formed. The conductive layer (A) 124 is a tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, or nitride. It is made of molybdenum (MoN) or the like. Further, tungsten silicide, titanium silicide, or molybdenum silicide may be applied to the conductive layer (A) 124. In the conductive layer (B) 125, it is preferable to reduce the concentration of impurities contained in order to reduce the resistance. In particular, the oxygen concentration is preferably 30 ppm or less. For example, tungsten (W) was able to realize a specific resistance value of 20 μΩcm or less by setting the oxygen concentration to 30 ppm or less.
[0064]
The conductive layer (A) 124 may be 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 125 may be 200 to 400 nm (preferably 250 to 350 nm). When W is used as a gate electrode, argon (Ar) gas and nitrogen (N ₂ ) Gas is introduced to form the conductive layer (A) 125 with tungsten nitride (WN) to a thickness of 50 nm, and the conductive layer (B) 124 is formed with W to a thickness of 250 nm. As another method, W film is tungsten hexafluoride (WF ₆ Can also be formed by a thermal CVD method. In any case, it is necessary to reduce the resistance in order to use it as a gate electrode, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is hindered and the resistance is increased. Therefore, in the case of sputtering, the resistivity is obtained by using a W target with a purity of 99.9999% and forming a W film with sufficient consideration so that impurities are not mixed in the gas phase during film formation. 9-20 μΩcm can be realized.
[0065]
On the other hand, when a TaN film is used for the conductive layer (A) 124 and a Ta film is used for the conductive layer (B) 125, it can be similarly formed by sputtering. The TaN film is formed using Ta as a target and a mixed gas of Ar and nitrogen as a sputtering gas, and the Ta film uses Ar as a sputtering gas. In addition, when an appropriate amount of Xe or Kr is added to these sputtering gases, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used as a gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm, which is not suitable for a gate electrode. Since the TaN film has a crystal structure close to an α phase, an α phase Ta film can be easily obtained by forming a Ta film thereon. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A) 124. This improves adhesion and prevents oxidation of the conductive film formed thereon, and at the same time, an alkali metal element contained in a trace amount in the conductive layer (A) 124 or the conductive layer (B) 125 is added to the gate insulating film 127. It can be prevented from spreading. In any case, the conductive layer (B) 125 preferably has a resistivity in the range of 10 to 50 μΩcm.
[0066]
Next, resist masks 126a to 126f are formed using a photomask using a photolithographic technique, and the conductive layer (A) 124 and the conductive layer (B) 125 are collectively etched to form gate electrodes 128 to 132. And the capacitor wiring 133 is formed. The gate electrodes 128 to 132 and the capacitor wiring 133 are integrally formed of 128a to 132a made of a conductive layer (A) and 128b to 132b made of a conductive layer (B) (FIG. 9A). FIG. 11D shows the positional relationship between the island-shaped semiconductor layers 115 and 116 and the gate insulating films 128 and 129 in this state. Similarly, the relationship between the island-shaped semiconductor layer 119, the gate electrode 132, and the capacitor wiring 133 is illustrated in FIG. In FIGS. 11D and 12D, the gate insulating film 127 is omitted.
[0067]
A method for etching the conductive layer (A) and the conductive layer (B) may be appropriately selected by a practitioner. However, when the conductive layer (A) and the conductive layer (B) are formed of a material mainly composed of W as described above, the method In order to perform etching with high accuracy, it is desirable to apply a dry etching method using high-density plasma. As a method for obtaining high-density plasma, microwave plasma or inductively coupled plasma (ICP) etching apparatus may be used. For example, the W etching method using an ICP etching apparatus uses CF as an etching gas. _Four And Cl ₂ These gases are introduced into the reaction chamber, the pressure is set to 0.5 to 1.5 Pa (preferably 1 Pa), and 200 to 1000 W of high frequency (13.56 MHz) power is applied to the inductive coupling portion. At this time, high-frequency power of 20 W is applied to the stage on which the substrate is placed, and the negative ions are charged by self-bias, whereby positive ions are accelerated and anisotropic etching can be performed. By using an ICP etching apparatus, a hard metal film such as W can obtain an etching rate of 2 to 5 nm / second. Further, in order to perform etching without leaving a residue, overetching is preferably performed by increasing the etching time at a rate of about 10 to 20%. However, it is necessary to pay attention to the etching selectivity with the base at this time. For example, since the selection ratio of the silicon oxynitride film (gate insulating film 127) to the W film is 2.5 to 3, the surface where the silicon oxynitride film is exposed by such over-etching is etched by about 20 to 50 nm. Has been substantially thinned.
[0068]
Then, in order to form an LDD region in the n-channel TFT of the pixel TFT, an impurity element addition step (n ^- Doping process) was performed. An impurity element imparting n-type in a self-aligning manner is added by ion doping using the gate electrodes 128 to 132 as a mask. The concentration of phosphorus (P) added as an impurity element imparting n-type is 1 × 10 ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three Add in the concentration range of. In this manner, low-concentration n-type impurity regions 134 to 139 are formed in the island-like semiconductor layer as shown in FIG.
[0069]
Next, in the n-channel TFT, a high concentration n-type impurity region functioning as a source region or a drain region was formed (n ⁺ Doping process). First, resist masks 140a to 140d were formed using a photomask, and an n-type impurity element was added to form high-concentration n-type impurity regions 141 to 146. Phosphorus (P) is used for the impurity element imparting n-type, and its concentration is 1 × 10. ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three The phosphine (PH _Three ) Using an ion doping method (FIG. 9C).
[0070]
Then, high-concentration p-type impurity regions 148 and 149 serving as a source region and a drain region are formed in the island-shaped semiconductor layers 115 and 117 forming the p-channel TFT. Here, an impurity element imparting p-type is added using the gate electrodes 128 and 130 as a mask, and a high-concentration p-type impurity region is formed in a self-aligning manner. At this time, the island-shaped semiconductor films 116, 118, and 119 forming the n-channel TFT are covered with resist masks 147a to 147c using a photomask. High-concentration p-type impurity regions 148 and 149 are formed of diborane (B ₂ H ₆ ) Using an ion doping method. The boron (B) concentration in this region is 3 × 10 ²⁰ ~ 3x10 ^{twenty one} atoms / cm ^Three (FIG. 9D). The high-concentration p-type impurity regions 148 and 149 are doped with phosphorus (P) in the previous step, and the high-concentration p-type impurity regions 148a and 149a are 1 × 10 6. ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three In the high concentration p-type impurity regions 148b and 149b, 1 × 10 ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three In order to function as a source region and a drain region of a p-channel TFT by increasing the concentration of boron (B) added in this step from 1.5 to 3 times. There was no problem.
[0071]
After that, as shown in FIG. 10A, a protective insulating film 150 is formed over the gate electrode and the gate insulating film. The protective insulating film may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film including a combination thereof. In any case, the protective insulating film 150 is formed from an inorganic insulating material. The thickness of the protective insulating film 150 is 100 to 200 nm. Here, when a silicon oxide film is used, tetraethyl orthosilicate (TEOS) and O2 are formed by plasma CVD. ₂ The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. ² And can be formed by discharging. When using a silicon oxynitride film, SiH is formed by plasma CVD. _Four , N ₂ O, NH _Three Silicon oxynitride film manufactured from SiH or SiH _Four , N ₂ A silicon oxynitride film formed from O may be used. The production conditions in this case are a reaction pressure of 20 to 200 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm. ² Can be formed. SiH _Four , N ₂ O, H ₂ Alternatively, a silicon oxynitride silicon film manufactured from the above may be used. Similarly, the silicon nitride film is made of SiH by plasma CVD. _Four , NH _Three It is possible to make from. Such a protective insulating film is formed so as to have a compressive stress with the substrate as the center.
[0072]
Thereafter, a step of activating the impurity element imparting n-type or p-type added at each concentration is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm or less in a nitrogen atmosphere at 400 to 700 ° C., typically 500 to 600 ° C. In this embodiment, the temperature is 550 ° C. for 4 hours. Heat treatment was performed. In the case where a plastic substrate having a low heat resistant temperature is used for the substrate 101, it is preferable to apply a laser annealing method (FIG. 10B).
[0073]
After the activation step, a heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is performed on the island-like semiconductor layer 10 by thermally excited hydrogen. ¹⁶ -10 ¹⁸ /cm ^Three This is a step of terminating the dangling bond. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed. Alternatively, the island-shaped semiconductor layer may be hydrogenated by diffusing hydrogen in the silicon oxynitride silicon film 102 b of the base film 102 and the silicon oxynitride film of the protective insulating film 150 by heat treatment at 300 to 450 ° C.
[0074]
When the activation and hydrogenation steps are completed, an interlayer insulating film 151 made of an organic insulating material is formed with an average thickness of 1.0 to 2.0 μm. As the organic resin material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. For example, when using a type of polyimide that is thermally polymerized after being applied to the substrate, it is formed by baking at 300 ° C. using a clean oven. In the case of using acrylic, a two-component type is used, and after mixing the main material and the curing agent, applying to the entire surface of the substrate using a spinner, using a hot plate, preparatory for 60 seconds at 80 ° C. It can be formed by heating and further baking at 250 ° C. for 60 minutes using a clean oven.
[0075]
By forming the interlayer insulating film with an organic insulating material, the surface can be satisfactorily flattened. In addition, since organic resin materials generally have a low dielectric constant, parasitic capacitance can be reduced. However, since it is hygroscopic and not suitable as a protective film, it needs to be used in combination with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like formed as the protective insulating film 150 as in this embodiment.
[0076]
After that, a resist mask having a predetermined pattern is formed using a photomask, and contact holes reaching the source region or the drain region formed in each island-shaped semiconductor film are formed. Contact holes are formed by dry etching. In this case, CF is used as an etching gas. _Four , O ₂ First, the interlayer insulating film made of an organic resin material is etched using a mixed gas of He, and then the etching gas is changed to CF. _Four , O ₂ The protective insulating film 146 is etched as follows. Further, in order to increase the selectivity with the island-shaped semiconductor layer, the etching gas is changed to CHF. _Three The contact hole can be satisfactorily formed by switching to 1 and etching the gate insulating film.
[0077]
Then, a conductive metal film is formed by sputtering or vacuum deposition, a resist mask pattern is formed by a photomask, and source wirings 152 to 156 and drain wirings 157 to 161 are formed by etching. A drain wiring 162 indicates a drain wiring of an adjacent pixel. Here, the drain wiring 161 functions as a pixel electrode. Although not shown, in this embodiment, this electrode is formed by forming a Ti film with a thickness of 50 to 150 nm, forming a contact with the semiconductor film forming the source or drain region of the island-like semiconductor layer, and the Ti film Overlaid on top, aluminum (Al) was formed to a thickness of 300 to 400 nm to form a wiring.
[0078]
FIG. 11E is a top view of the island-shaped semiconductor layers 115 and 116, the gate electrodes 128 and 129, the source wirings 152 and 153, and the drain wirings 157 and 158 in this state. The source wirings 152 and 153 are connected to the island-shaped semiconductor layers 115 and 116 through 230 and 233, respectively, through contact holes provided in an interlayer insulating film and a protective insulating film (not shown). The drain wirings 157 and 158 are connected to the island-shaped semiconductor layers 115 and 116 at 231 and 232, respectively. Similarly, FIG. 12E shows a top view of the island-shaped semiconductor layer 119, the gate electrode 132, the capacitor wiring 133, the source wiring 156, and the drain wiring 161. The source wiring 156 is a contact portion 234, and the drain wiring 161 is The contact portions 235 are connected to the island-shaped semiconductor layers 119, respectively. In any case, the region where the strain remains is removed from the region inside the island-shaped semiconductor layer having the first shape, and the island-shaped semiconductor layer having the second shape is formed to form the TFT. To do.
[0079]
When the hydrogenation treatment was performed in this state, favorable results were obtained with respect to the improvement of TFT characteristics. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect can be obtained by using a plasma hydrogenation method. Further, by such heat treatment, hydrogen present in the protective insulating film 146 and the base film 102 can be diffused into the island-shaped semiconductor films 115 to 119 to be hydrogenated. In any case, the defect density in the island-shaped semiconductor layers 115 to 119 is 10 ¹⁶ /cm ^Three It is desirable that the hydrogen content be 5 × 10 5 for this purpose. ¹⁸ ~ 5x10 ¹⁹ atoms / cm ^Three It should have been added to the extent (FIG. 10C). In the island-like semiconductor layer to which such a treatment was applied, the crystal grain boundaries slightly present became inactive, and a region that could be regarded as a single crystal was formed.
[0080]
In this way, a substrate having the TFT of the driving circuit and the pixel TFT of the pixel portion can be completed on the same substrate. A first p-channel TFT 200, a first n-channel TFT 201, a second p-channel TFT 202, and a second n-channel TFT 203 are formed in the driver circuit, and a pixel TFT 204 and a storage capacitor 205 are formed in the pixel portion. Yes. In this specification, such a substrate is referred to as an active matrix substrate for convenience.
[0081]
The first p-channel TFT 200 of the driving circuit has a single drain structure in which an island-like semiconductor film 115 has a channel formation region 206, source regions 207a and 207b made of high-concentration p-type impurity regions, and drain regions 208a and 208b. have. The first n-channel TFT 201 includes a channel formation region 209, an LDD region 210 that overlaps with the gate electrode 119, a source region 212, and a drain region 211 on the island-shaped semiconductor film 116. In this LDD region, the LDD region overlapping with the gate electrode 119 is Lov, and the length in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 2.0 μm. By making the length of the LDD region in the n-channel TFT in this way, a high electric field generated in the vicinity of the drain region can be relaxed, hot carrier generation can be prevented, and deterioration of the TFT can be prevented. Similarly, the second p-channel TFT 202 of the driver circuit is a single drain having a channel formation region 213, source regions 214a and 214b composed of high-concentration p-type impurity regions, and drain regions 215a and 215b on an island-shaped semiconductor film 117. It has a structure. In the second n-channel TFT 203, a channel formation region 216, LDD regions 217 and 218, a source region 220, and a drain region 219 which partially overlap with the island-shaped semiconductor film 118 are formed. The length of Lov overlapping the gate electrode of this TFT was also 0.5 to 3.0 μm, preferably 1.0 to 2.0 μm. The LDD region that does not overlap the gate electrode is Loff, and the length in the channel length direction is 0.5 to 4.0 μm, preferably 1.0 to 2.0 μm. The pixel TFT 204 has channel formation regions 221 and 222, LDD regions 223 to 225, and source or drain regions 226 to 228 in an island-shaped semiconductor film 119. The length of the LDD region (Loff) in the channel length direction is 0.5 to 4.0 μm, preferably 1.5 to 2.5 μm. Further, a storage capacitor 205 is formed from the capacitor wiring 123, an insulating film made of the same material as the gate insulating film, and a semiconductor layer 229 connected to the drain region 228 of the pixel TFT 204. Although the pixel TFT 204 has a double gate structure in FIG. 10C, it may have a single gate structure or a multi-gate structure in which a plurality of gate electrodes are provided.
[0082]
FIG. 13 is a top view showing almost one pixel in the pixel portion. A cross section AA ′ shown in the drawing corresponds to the cross sectional view of the pixel portion shown in FIG. In the pixel TFT 204, the gate electrode 132 that also serves as a gate wiring intersects the island-like semiconductor layer 119 under the gate insulating film (not shown). Although not shown, a source region, a drain region, and an LDD region are formed in the island-shaped semiconductor layer. Reference numeral 234 denotes a contact portion between the source wiring 156 and the source region 226, and 235 denotes a contact portion between the drain wiring 161 and the drain region 228. The storage capacitor 205 is formed in a region where the capacitor wiring 133 overlaps with the semiconductor layer 229 extending from the drain region 228 of the pixel TFT 204 and the gate insulating film.
[0083]
The island-like semiconductor layer formed from the dual beam laser annealing method according to the present invention through the above steps has a single crystal structure. By using such island-shaped semiconductor layers, the structure of the TFTs constituting each circuit is optimized according to the specifications required by the pixel TFT and the drive circuit, thereby improving the operation performance and reliability of the semiconductor device. Is possible. Further, the gate electrode is made of a heat-resistant conductive material, thereby facilitating activation of the LDD region, the source region, and the drain region. A high-quality display device can be realized with such an active matrix substrate. A reflective liquid crystal display device can be manufactured from the active matrix substrate manufactured in this embodiment.
[0084]
[Example 2]
In the present invention, when the dual beam laser annealing method is applied, the size of the island-shaped semiconductor layer to be annealed is preferably such that the distance from the center portion to the end portion is 50 μm or less. However, there may be a demand for the channel width of the TFT to be 50 μm or more due to circuit characteristics. In this embodiment, a configuration example of an island-shaped semiconductor layer that can sufficiently obtain the effects of the present invention is shown in such a case.
[0085]
FIG. 14 shows a top view corresponding to FIG. 10C in the TFT of the driving circuit of the active matrix substrate described in Embodiment 1 with reference to FIGS. The island-shaped semiconductor layers 115a to 115c and 116a to 116c having the second shape formed by being divided into a plurality of portions are formed with gaps therebetween. By forming the island-shaped semiconductor layer of the first shape with a gap in this way, direct laser light and diffusion laser light can be effectively used in the crystallization process by the dual beam laser annealing method. In other words, the island-shaped semiconductor layers 115a, 115c, 116a, and 116c located on the outer side and the island-shaped semiconductor layers 115b and 116b located on the center can form a crystalline semiconductor layer having equivalent crystallinity. FIG. 14A shows a state where gate electrodes 128 and 129, source wirings 152 and 153, and drain wirings 157 and 158 are formed over such an island-shaped semiconductor layer. The region 114 where the strain is accumulated is left as it is except for the channel formation region where the gate electrode and the island-shaped semiconductor layer are covered and the peripheral region. In this manner, even if a TFT is manufactured with the region 114 where strain is accumulated remaining at least in a portion other than the channel formation region, the above-described characteristics do not deteriorate. Such a configuration can also be applied to each TFT manufactured in Example 1. Of course, the number of dividing the island-shaped semiconductor layer is not limited, and the number of p-channel TFTs can be different from that of n-channel TFTs. With such a TFT, various circuits including an inverter circuit which is a basic form of a CMOS circuit can be formed.
[0086]
FIG. 14B shows an example in which at least one gap 1401 is provided inside each of the island-shaped semiconductor layers 115 and 116 having the second shape. Such a gap 1401 is formed in advance in the first shape. In the same manner, the direct laser beam and the diffused laser beam can be used effectively by performing crystallization by a dual beam laser annealing method. FIG. 14B shows a state where gate electrodes 128 and 129, source wirings 152 and 153, and drain wirings 157 and 158 are formed over such an island-shaped semiconductor layer, and a region 114 where strain is accumulated. The gate electrode and the island-shaped semiconductor layer may be left as they are except for the channel formation region where the gate electrode and the island-shaped semiconductor layer are bulky and the surrounding region.
[0087]
[Example 3]
In the first embodiment, a so-called GOLD (Gate-drain Overlapped LDD) structure in which all or part of the LDD regions of the first n-channel TFT 201 and the second n-channel TFT 203 of the driving circuit overlap with the gate electrode is formed. Formed with. However, in order to simplify the process and manufacture at a lower cost, there is a method in which the GOLD structure is omitted and the n-channel TFT is manufactured with an LDD structure. Although the GOLD structure can prevent the deterioration due to hot carriers in the n-channel TFT, the LDD structure also suppresses the deterioration due to hot carriers by making the length of the LDD region in the channel length direction appropriate. can do.
[0088]
In order to make the first n-channel TFT 201 and the second n-channel TFT 203 of the drive circuit into TFTs having an LDD structure, in the process described in Embodiment 1 with reference to FIGS. ) May be omitted. An active matrix substrate manufactured by such a process is shown in FIG.
[0089]
In FIG. 15, the first p-channel TFT 200 of the drive circuit has a channel formation region 206, source regions 207a and 207b composed of high-concentration p-type impurity regions, and drain regions 208a and 208b in an island-shaped semiconductor film 115. It has a single drain structure. The first n-channel TFT 201 includes a channel formation region 209, an LDD region 210 b that does not overlap with the gate electrode 129, a source region 212, and a drain region 211 on the island-shaped semiconductor film 116. The length of the LDD region in the channel length direction is 1.0 to 4.0 μm, preferably 2.0 to 3.0 μm. By making the length of the LDD region in the n-channel TFT in this way, a high electric field generated in the vicinity of the drain region can be relaxed, hot carrier generation can be prevented, and deterioration of the TFT can be prevented. Similarly, the second p-channel TFT 202 of the driver circuit is a single drain having a channel formation region 213, source regions 214a and 214b composed of high-concentration p-type impurity regions, and drain regions 215a and 215b on an island-shaped semiconductor film 117. It has a structure. In the second n-channel TFT 203, a channel formation region 216, LDD regions 217 b and 218 b, a source region 220, and a drain region 219 are formed in the island-shaped semiconductor film 118. The length of the LDD of this TFT was also set to 1.0 to 4.0 μm. The pixel TFT 204 has channel formation regions 221 and 222, LDD regions 223 to 225, and source or drain regions 226 to 228 in an island-shaped semiconductor film 119. The length of the LDD region in the channel length direction is 0.5 to 4.0 μm, preferably 1.5 to 2.5 μm. Further, a storage capacitor 205 is formed from the capacitor wiring 133, an insulating film made of the same material as the gate insulating film, and a semiconductor layer 229 connected to the drain region 228 of the pixel TFT 204.
[0090]
Also in the process of this embodiment, the structure of the TFT described in Embodiment 2 can be employed. A reflective liquid crystal display device can be manufactured from the active matrix substrate manufactured in this embodiment.
[0091]
[Example 4]
The active matrix substrate manufactured in Embodiment 1 can be applied to a reflective liquid crystal display device as it is. On the other hand, in the case of a transmissive liquid crystal display device, a pixel electrode provided in each pixel of the pixel portion may be formed using a transparent electrode. In this embodiment, a method for manufacturing an active matrix substrate corresponding to a transmissive liquid crystal display device is described with reference to FIGS.
[0092]
The active matrix substrate is manufactured in the same manner as in Example 1. In FIG. 16A, a conductive metal film is formed as a source wiring and a drain wiring by a sputtering method or a vacuum evaporation method. In this method, a Ti film is formed to a thickness of 50 to 150 nm, a contact is formed with a semiconductor film that forms a source or drain region of an island-like semiconductor layer, and aluminum (Al) 300 to 300 is stacked on the Ti film. The film was formed to a thickness of 400 nm, and a Ti film or a titanium nitride (TiN) film was formed to a thickness of 100 to 200 nm to form a three-layer structure. Thereafter, a transparent conductive film is formed over the entire surface, and a pixel electrode 171 is formed by patterning processing and etching processing using a photomask. The pixel electrode 164 is formed on the interlayer insulating film 151, and a portion overlapping the drain wiring 163 of the pixel TFT 204 is provided to form a connection structure.
[0093]
In FIG. 16B, first, a transparent conductive film is formed over the interlayer insulating film 151, patterning treatment and etching treatment are performed to form a pixel electrode 166, and then a drain wiring 165 is provided so as to overlap with the pixel electrode 166. This is an example of formation. In the drain wiring 165, a Ti film is formed to a thickness of 50 to 150 nm, a contact is formed with a semiconductor film that forms a source or drain region of the island-like semiconductor layer, and aluminum (Al) 300 is overlaid on the Ti film. It is formed with a thickness of ˜400 nm. With this configuration, the pixel electrode 166 is in contact with only the Ti film that forms the drain wiring 165. As a result, it is possible to reliably prevent the transparent conductive film material and Al from reacting as compared with the structure of FIG.
[0094]
The material of the transparent conductive film is indium oxide (In ₂ O _Three ) Or indium tin oxide alloy (In ₂ O _Three -SnO ₂ ; ITO) or the like can be formed using a sputtering method, a vacuum deposition method, or the like. Etching treatment of such a material is performed with a hydrochloric acid based solution. However, in particular, etching of ITO is likely to generate a residue, so in order to improve etching processability, an indium oxide-zinc oxide alloy (In ₂ O _Three —ZnO) may also be used. Since the indium oxide-zinc oxide alloy has excellent surface smoothness and thermal stability with respect to ITO, it can prevent the corrosion reaction with Al in contact with the end face of the drain wiring 163 in the structure of FIG. . Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: Ga) to which gallium (Ga) is added to further increase the transmittance and conductivity of visible light can be used.
[0095]
In this manner, an active matrix substrate corresponding to a transmissive liquid crystal display device can be completed. Although this embodiment has been described as a process similar to that of Embodiment 1, such a configuration can be applied to the active matrix substrate shown in Embodiment 2 or Embodiment 3.
[0096]
[Example 5]
In a method for manufacturing an island-shaped semiconductor layer having a crystal structure from an island-shaped semiconductor layer having an amorphous structure by a dual beam laser annealing method according to the present invention, the crystal structure manufactured by the method of Embodiment 2 or Embodiment 3 In the island-shaped semiconductor layer having a small amount (1 × 10 ¹⁷ ~ 1x10 ¹⁹ atoms / cm ^Three Degree) catalyst element remains. Of course, it is possible to complete the TFT even in such a state, but it is more preferable to remove at least the remaining catalyst element from the channel formation region. One means for removing this catalytic element is a means that utilizes the gettering action of phosphorus (P).
[0097]
The gettering process using phosphorus (P) for this purpose can be performed simultaneously in the activation step described with reference to FIG. This will be described with reference to FIG. The concentration of phosphorus (P) necessary for gettering may be approximately the same as the impurity concentration of the high-concentration n-type impurity region, and the catalyst from the channel formation region of the n-channel TFT and the p-channel TFT is formed by thermal annealing in the activation process. The element can be segregated to the impurity region containing phosphorus (P) at that concentration (in the direction of the arrow shown in FIG. 17). As a result, the catalytic element segregates in the impurity region, and the concentration is 1 × 10. ¹⁷ ~ 1x10 ¹⁹ atoms / cm ^Three It became about. The TFT manufactured in this manner has a low off-current value and good crystallinity, so that high field-effect mobility can be obtained and good characteristics can be achieved.
[0098]
[Example 6]
In this embodiment, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described. First, as shown in FIG. 18A, a spacer including a columnar spacer 168 is formed on the active matrix substrate in the state of FIG. The spacer may be provided by dispersing particles of several μm, but here, a method of forming a resin film on the entire surface of the substrate and then patterning it is adopted. Although there is no limitation on the material of such a spacer, for example, NN700 manufactured by JSR Co. is used, and after applying with a spinner, a predetermined pattern is formed by exposure and development processing. Further, it is cured by heating at 150 to 200 ° C. in a clean oven or the like. The spacers produced in this manner can have different shapes depending on the conditions of exposure and development processing. Preferably, the columnar spacers 168 have a columnar shape and a flat top, so that the opposite side has a flat shape. When the substrates are combined, the mechanical strength of the liquid crystal display panel can be ensured. The shape is not particularly limited, such as a conical shape or a pyramid shape. For example, when the shape is conical, the height H is set to 1.2 to 5 μm, the average radius L1 is set to 5 to 7 μm, and the average radius L1 is set. The ratio to the bottom radius L2 is set to 1: 1.5. At this time, the taper angle of the side surface is ± 15 ° or less.
[0099]
The arrangement of the columnar spacers may be arbitrarily determined. Preferably, as shown in FIG. 18A, the pixel portion is overlapped with the contact portion 235 of the drain wiring 161 (pixel electrode) so as to cover the portion. A columnar spacer 168 may be formed. Since the flatness of the contact portion 235 is lost and the liquid crystal is not aligned well in this portion, the columnar spacer 168 is formed in such a manner that the spacer 168 is filled in the contact portion 235 so that disclination or the like is performed. Can be prevented.
[0100]
Thereafter, an alignment film 169 is formed. Usually, a polyimide resin is used for the alignment film of the liquid crystal display element. After the alignment film was formed, rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. The region not rubbed in the rubbing direction from the end of the columnar spacer 168 provided in the pixel portion was set to 2 μm or less. In the rubbing process, the occurrence of static electricity is often a problem. However, if the spacers 167a to 167e are formed on at least the source wiring and the drain wiring on the TFT of the driving circuit, they can be used as spacers in the rubbing process. The original role and the effect of protecting the TFT from static electricity can be obtained.
[0101]
A light shielding film 171, a transparent conductive film 172, and an alignment film 173 are formed on the counter substrate 170 on the opposite side. The light shielding film 171 is made of Ti, Cr, Al or the like with a thickness of 150 to 300 nm. Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are bonded together with a sealant 174. A filler 175 is mixed in the sealant 174, and the two substrates are bonded to each other with a uniform interval by the filler 175 and the spacers 167 and 168. Thereafter, a liquid crystal material 176 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. For example, in addition to the TN liquid crystal, a thresholdless antiferroelectric mixed liquid crystal exhibiting electro-optical response in which the transmittance continuously changes with respect to the electric field can be used. Some thresholdless antiferroelectric mixed liquid crystals exhibit V-shaped electro-optic response characteristics. Thus, the active matrix liquid crystal display device shown in FIG. 18B is completed.
[0102]
In FIG. 18, the spacer 167 is formed on the source wiring and the drain wiring on the TFT of the drive circuit by dividing the spacer 167 into spacers 167a to 167e. However, the spacer 167 may be formed to cover the entire surface of the drive circuit.
[0103]
FIG. 19 is a top view of the active matrix substrate, and is a top view showing the positional relationship between the pixel portion and the drive circuit portion, the spacer and the sealant. Around the pixel portion 700, a scanning signal driving circuit 701 and an image signal driving circuit 702 are provided as driving circuits. Further, a signal processing circuit 703 such as a CPU or a memory may be added. These drive circuits are connected to the external input / output terminal 710 by connection wiring 711. In the pixel portion 700, a gate wiring group 704 extending from the scanning signal driving circuit 701 and a source wiring group 705 extending from the image signal driving circuit 702 intersect to form a pixel, and each pixel has a pixel TFT 204. And a storage capacitor 205 are provided.
[0104]
The columnar spacers 706 provided in the pixel portion correspond to the columnar spacers 168 shown in FIG. 18 and may be provided for all pixels, but every few to several tens of pixels arranged in a matrix. May be provided. That is, the ratio of the number of spacers to the total number of pixels constituting the pixel portion is preferably 20 to 100%. In addition, the spacers 707, 708, and 709 provided in the driver circuit portion may be provided so as to cover the entire surface, or as shown in FIG. 18, the spacers 707, 708, and 709 are divided into a plurality according to the positions of the source and drain wirings of each TFT. May be provided.
[0105]
The sealant 174 is formed outside the pixel portion 700 on the substrate 101, the scanning signal control circuit 701, the image signal control circuit 702, and other signal processing circuits 703 and inside the external input / output terminal 710.
[0106]
The structure of such an active matrix liquid crystal display device will be described with reference to the perspective view of FIG. In FIG. 20, the active matrix substrate includes a pixel portion 700, a scanning signal driving circuit 701, an image signal driving circuit 702, and other signal processing circuits 703 formed on the glass substrate 101. A pixel TFT 204 and a storage capacitor 205 are provided in the pixel portion 700, and a driver circuit provided around the pixel portion is configured based on a CMOS circuit. The scanning signal driving circuit 701 and the image signal driving circuit 702 are connected to the pixel TFT 204 by a gate wiring 132 and a source wiring 156, respectively. A flexible printed circuit (FPC) 713 is connected to an external input terminal 710 and used for inputting an image signal or the like. The flexible printed wiring board 713 is fixed with a reinforcing resin 712 with increased adhesive strength. The connection wiring 711 connects to each drive circuit. The counter substrate 175 is provided with a light shielding film and a transparent electrode (not shown).
[0107]
The liquid crystal display device having such a structure can be formed using the active matrix substrate shown in Embodiments 1 to 5. For example, a reflective liquid crystal display device can be obtained by using the active matrix substrate shown in Embodiments 1 to 3, and a transmissive liquid crystal display device can be obtained by using the active matrix substrate shown in Embodiment 4.
[0108]
[Example 7]
In this embodiment, an example in which the present invention is applied to a display device (organic EL display device) using an active matrix organic electroluminescence (organic EL) material will be described with reference to FIG. FIG. 21A is a circuit diagram of an active matrix organic EL display device in which a display region is provided on a glass substrate and a driver circuit is provided around the display region. This organic EL display device includes a display area 11 provided on a substrate, an X-direction peripheral drive circuit 12, and a Y-direction peripheral drive circuit 13. The display area 11 is configured by a switching TFT 30, a storage capacitor 32, a current control TFT 31, an organic EL element 33, X-direction signal lines 18a and 18b, power supply lines 19a and 19b, Y-direction signal lines 20a, 20b, and 20c. Is done.
[0109]
FIG. 21B shows a top view of almost one pixel. The switching TFT 30 is preferably formed in the same manner as the n-channel TFT 204 shown in FIG. 10C, and the current control TFT 31 is formed in the same manner as the p-channel TFT 200.
[0110]
FIG. 22 is a cross-sectional view taken along the line BB ′ in FIG. 21B, and shows a cross-sectional view of the switching TFT 30, the storage capacitor 32, the current control TFT 31, and the organic EL element portion. In FIG. 22, island-shaped semiconductor layers 43 and 44 are manufactured by the method of Embodiments 1-4. Then, the base films 41 and 42, the gate insulating film 45, the protective insulating film 46, the gate electrodes 47 and 48, the capacitor wiring 49, the source and drain wirings 18a, 19a, 51 and 52, and the interlayer insulating film 50 are implemented on the substrate 40. Prepared in the same manner as in Example 1. Then, a second interlayer insulating film 53 is formed thereon as in the case of the interlayer insulating film 50, a contact hole reaching the drain wiring 52 is formed, and then a pixel electrode 54 made of a transparent conductive film is formed. The organic EL element section includes the pixel electrode 54, an organic EL layer 55 formed over the pixel electrode and the second interlayer insulating film 53, and a first electrode made of MgAg compound formed thereon. 56, a second electrode 57 made of Al. Although not shown, if a color filter is provided, color display is possible. In any case, an active matrix organic EL display device can be easily manufactured by applying the method for manufacturing an active matrix substrate shown in Embodiments 1 to 5.
[0111]
[Example 8]
An active matrix substrate, a liquid crystal display device, and an EL display device manufactured by implementing the present invention can be used in various electro-optical devices. The present invention can be applied to all electronic devices in which such an electro-optical device is incorporated as a display medium. Examples of electronic devices include personal computers, digital cameras, video cameras, portable information terminals (mobile computers, mobile phones, electronic books, etc.), navigation systems, and the like.
[0112]
FIG. 23A illustrates a portable information terminal which includes a main body 2201, an image input portion 2202, an image receiving portion 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205 and other signal control circuits.
[0113]
Such portable information terminals are often used outdoors as well as indoors. In order to enable long-term use, a backlight is not used, and a reflective liquid crystal display device that uses outside light is suitable as a low-power consumption type, but a backlight is provided when the surroundings are dark. A transmissive liquid crystal display device is suitable. From such a background, a hybrid type liquid crystal display device having both characteristics of a reflection type and a transmission type has been developed. However, the present invention can also be applied to such a hybrid type liquid crystal display device. A display device 2205 includes a touch panel 3002, a liquid crystal display device 3003, and an LED backlight 3004. A touch panel 3002 is provided to simplify the operation of the portable information terminal. In the configuration of the touch panel 3002, a light emitting element 3100 such as an LED is provided at one end, a light receiving element 3200 such as a photodiode is provided at the other end, and an optical path is formed therebetween. When the touch panel 3002 is pressed to block the optical path, the output of the light receiving element 3200 changes. By using this principle, the light emitting elements and the light receiving elements are arranged in a matrix on the liquid crystal display device, thereby functioning as an input medium. it can.
[0114]
FIG. 23B shows a structure of a pixel portion of a hybrid liquid crystal display device. A drain wiring 177 and a pixel electrode 178 are provided over an interlayer insulating film over the pixel TFT 204 and the storage capacitor 205. Such a configuration can be formed by applying Example 4. The drain wiring is configured to serve as a pixel electrode as a laminated structure of a Ti film and an Al film. The pixel electrode 177 is formed using the transparent conductive film material described in Embodiment 4. By manufacturing the liquid crystal display device 3003 from such an active matrix substrate, the liquid crystal display device 3003 can be preferably used for a portable information terminal.
[0115]
FIG. 24A illustrates a personal computer which includes a main body 2001 including a microprocessor and a memory, an image input portion 2002, a display device 2003, and a keyboard 2004. The present invention can form the display device 2003 and other signal processing circuits.
[0116]
FIG. 24B shows a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102 and other signal control circuits.
[0117]
FIG. 24C shows a goggle type display, which includes a main body 2901, a display device 2902, and an arm portion 2903. The present invention can be applied to the display device 2902 and other signal control circuits not shown.
[0118]
FIG. 24D illustrates an electronic game device such as a video game or a video game, which is incorporated in a main body 2301, a controller 2305, a display device 2303, and a main body 2301 on which an electronic circuit 2308 such as a CPU and a recording medium 2304 are mounted. A display device 2302 is included. The display device 2303 and the display device 2302 incorporated in the main body 2301 may display the same information, or display the information on the recording medium 2304 using the former as a main display device and the latter as a sub display device. The operation state can be displayed, or a touch sensor function can be added to provide an operation panel. In addition, the main body 2301, the controller 2305, and the display device 2303 may be wired communication in order to transmit signals to each other, or may be wireless communication or optical communication by providing sensor units 2306 and 2307. The present invention can be applied to the display devices 2302 and 2303. The display device 2303 can also use a conventional CRT.
[0119]
FIG. 24E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The player includes a main body 2401, a display device 2402, a speaker portion 2403, a recording medium 2404, and operation switches 2405. A recording medium such as a DVD (Digital Versatile Disc) or a compact disc (CD) can be used to play music programs, display images, display video games (or video games), and display information via the Internet. . The present invention can be suitably used for the display device 2402 and other signal control circuits.
[0120]
FIG. 24F illustrates a digital camera which includes a main body 2501, a display device 2502, an eyepiece unit 2503, an operation switch 2504, and an image receiving unit (not illustrated). The present invention can be applied to the display device 2502 and other signal control circuits.
[0121]
FIG. 25A shows a front projector, which includes a light source optical system, a display device 2601, and a screen 2602. The present invention can be applied to display devices and other signal control circuits. FIG. 25B shows a rear projector, which includes a main body 2701, a light source optical system and display device 2702, a mirror 2703, and a screen 2704. The present invention can be applied to display devices and other signal control circuits.
[0122]
Note that FIG. 25C illustrates an example of the structure of the light source optical system and the display devices 2601 and 2702 in FIGS. 25A and 25B. The light source optical system and the display devices 2601 and 2702 include a light source optical system 2801, mirrors 2802, 2804 to 2806, a dichroic mirror 2803, a beam splitter 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810. The projection optical system 2810 includes a plurality of optical lenses. FIG. 25C illustrates a three-plate type example in which three liquid crystal display devices 2808 are used. However, the present invention is not limited to such a method, and a single-plate optical system may be used. In addition, a suitable optical lens, a film having a polarization function, a film for adjusting a phase, an IR film, or the like may be provided in an optical path indicated by an arrow in FIG. FIG. 25D shows an example of the structure of the light source optical system 2801 in FIG. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. The light source optical system shown in FIG. 25D is an example and is not limited to the illustrated configuration.
[0123]
Although not shown here, the present invention can also be applied to a navigation system, a reading circuit of an image sensor, and the like. As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic device of a present Example is realizable using the technique of Examples 1-5.
[0124]
[Example 9]
FIG. 27 shows a scanning electron micrograph of a sample obtained by crystallizing an island-shaped semiconductor layer made of amorphous silicon by laser annealing. FIG. 27A shows a sample irradiated with laser light from the front side of the island-shaped semiconductor layer, and FIG. 27B shows a photograph of the sample irradiated from both the front side and the back side. Sample surface is Seco liquid (main component (volume ratio) HF: H ₂ O = 67: 33, additive K ₂ Cr ₂ O ₇ The surface is etched with This etching process utilizes the difference in the etching rate between the crystal grains and the crystal grain boundaries, and was performed to make the crystal grains obvious.
[0125]
As the laser annealing conditions, an excimer laser beam having a wavelength of 308 nm is used, and the light intensity is 370 mJ / cm. ² The same place was irradiated 20 times at a repetition frequency of 30 Hz. In the dual laser annealing method in which laser light is irradiated from both sides, an Al reflector is provided on the back side of the island-like semiconductor layer, that is, below the glass substrate. This reflector used was a mirror-polished silicon wafer with an Al film formed by sputtering on the surface.
[0126]
The average particle diameter is 0.05 to 0.2 μm in FIG. 27 (A) and 0.3 to 1.5 μm in FIG. 27 (B). Obviously, the latter has a larger particle size, and the superiority of the dual beam laser annealing method can be confirmed.
[0127]
【The invention's effect】
By using the present invention to crystallize an amorphous semiconductor region formed in an island-like pattern, the size of crystal grains can be increased. By using such island-shaped semiconductor layers, the structure of the TFTs constituting each circuit is optimized according to the specifications required by the pixel TFT and the drive circuit, thereby improving the operation performance and reliability of the semiconductor device. Is possible.
[Brief description of the drawings]
FIG. 1 is a view for explaining the concept of a laser annealing method according to the present invention.
FIG. 2 is a diagram illustrating a configuration of an optical system of a laser annealing apparatus.
FIG. 3 is a diagram illustrating a configuration of an optical system of a laser annealing apparatus.
4A and 4B illustrate a manufacturing process of an island-shaped semiconductor layer of the present invention.
5A and 5B illustrate a manufacturing process of an island-shaped semiconductor layer of the present invention.
6A and 6B illustrate a manufacturing process of an island-shaped semiconductor layer of the present invention.
7A and 7B illustrate a manufacturing process of an island-shaped semiconductor layer of the present invention.
FIG. 8 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 9 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a driver circuit TFT;
FIG. 10 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.
FIG. 11 is a top view illustrating a manufacturing process of a TFT of a driver circuit.
FIG. 12 is a top view illustrating a manufacturing process of a pixel TFT.
FIG. 13 is a top view illustrating a pixel in a pixel portion.
FIG. 14 is a top view illustrating a structure of a TFT.
FIG. 15 is a cross-sectional view illustrating a configuration of a pixel TFT and a TFT of a driver circuit.
FIG. 16 is a cross-sectional view illustrating a configuration of a pixel TFT and a TFT of a driver circuit.
17 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a driver circuit TFT. FIG.
FIG. 18 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.
FIG. 19 is a top view illustrating an arrangement of input / output terminals, wiring, circuit arrangement, spacers, and a sealant of a liquid crystal display device.
FIG. 20 is a perspective view illustrating a structure of a liquid crystal display device.
FIG. 21 illustrates a structure of an active matrix EL display device.
FIG 22 is a cross-sectional view illustrating a structure of a pixel portion of an active matrix EL display device.
FIG 23 illustrates an example of a semiconductor device.
FIG 24 illustrates an example of a semiconductor device.
FIG. 25 is a diagram showing a configuration of a projection type liquid crystal display device.
FIG. 26 is a graph showing a simulation result of the laser light intensity distribution in the depth direction of the silicon layer.
FIG. 27 is an electron micrograph of a silicon film crystallized by a laser annealing method.

Claims (8)

Form a base film on the substrate,
Wherein on the base film, forming a first surface in contact with the lower fabric layer, and a second surface on the opposite side, an amorphous semiconductor layer of the first shape having,
Wherein the second surface of the first amorphous semiconductor layer shape by irradiating a first laser beam, and is incident from the region around the amorphous semiconductor layer of the first shape, the substrate and transmitted by irradiating the second laser beam reflected from the first surface by the reflection plate to form a crystalline semiconductor layer of a first shape,
The first shape from the end portion of the crystalline semiconductor layer is removed over 1μm in, to form a crystalline semiconductor layer of the second shape,
A crystalline semiconductor layer of the second shape, by the addition of one conductivity type impurity, a method for manufacturing a semiconductor device comprising the Turkey to form a high-concentration n-type impurity region or the high-concentration p-type impurity regions . Form a base film on the substrate,
Wherein on the base film, forming a first surface in contact with the lower fabric layer, and a second surface on the opposite side, an amorphous semiconductor layer of the first shape having,
An element which promotes binding crystallization in the amorphous semiconductor layer of the first shape,
Wherein the second surface of the first amorphous semiconductor layer shape by irradiating a first laser beam, and is incident from the region around the amorphous semiconductor layer of the first shape, the substrate and transmitted by irradiating the second laser beam reflected from the first surface by the reflection plate to form a crystalline semiconductor layer of a first shape,
The first shape from the end portion of the crystalline semiconductor layer is removed over 1μm in, to form a crystalline semiconductor layer of the second shape,
A crystalline semiconductor layer of the second shape, by the addition of one conductivity type impurity, a method for manufacturing a semiconductor device comprising the Turkey to form a high-concentration n-type impurity region or the high-concentration p-type impurity regions . Form a base film on the substrate,
Forming an amorphous semiconductor layer on the base film;
An element which promotes binding crystallization in the amorphous semiconductor layer by heat treatment to form a crystalline semiconductor film,
A first surface, to form a crystalline semiconductor layer of the first shape having a second surface on the opposite side,
The first surface of the crystalline semiconductor layer having the first shape is irradiated with the first laser light and incident from a peripheral region of the crystalline semiconductor layer having the first shape, and is transmitted through the substrate. the second laser beam reflected by the reflection plate Te is irradiated from said first surface,
The first shape from the end portion of the crystalline semiconductor layer is removed over 1μm in, to form a crystalline semiconductor layer of the second shape,
A crystalline semiconductor layer of the second shape, by the addition of one conductivity type impurity, a method for manufacturing a semiconductor device comprising the Turkey to form a high-concentration n-type impurity region or the high-concentration p-type impurity regions . Oite to claim 2 or claim 3,
Prior Symbol high concentration n-type impurity region, a method for manufacturing a semiconductor device characterized by element for promoting the crystallization is contained at a concentration of ^{1 × 10 17 ~1 × 10 19} atoms / cm 3. In any one of Claims 1 thru | or 4,
The method for manufacturing a semiconductor device, wherein the reflector has an uneven shape. In any one of Claims 1 thru | or 5 ,
A method for manufacturing a semiconductor device, wherein the reflection plate has a diffuse reflectance of 50 to 70% with respect to the second laser light. In any one of Claims 1 thru | or 6,
A method for manufacturing a semiconductor device, comprising forming a gate electrode on the second shape crystalline semiconductor layer by an ICP etching method. Any one to Oite of claims 1 to 7,
The semiconductor device is a display device using an organic electroluminescent material, a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disk player, a goggle type display, an electronic game machine, or a projector. A method for manufacturing a semiconductor device.

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