JPH0319223A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0319223A JPH0319223A JP15344489A JP15344489A JPH0319223A JP H0319223 A JPH0319223 A JP H0319223A JP 15344489 A JP15344489 A JP 15344489A JP 15344489 A JP15344489 A JP 15344489A JP H0319223 A JPH0319223 A JP H0319223A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- insulating film
- interlayer insulating
- film
- metal wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000002184 metal Substances 0.000 claims abstract description 20
- 239000011229 interlayer Substances 0.000 claims abstract description 19
- 238000001312 dry etching Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000010410 layer Substances 0.000 abstract description 19
- 230000015572 biosynthetic process Effects 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、複数の金属配線層と複数のシリコン窒化膜を
層間絶縁膜とする半導体装置の製造方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using a plurality of metal wiring layers and a plurality of silicon nitride films as interlayer insulating films.
従来の技術
第２図に従来の製造方法によシ形成された半導体装置の
断面を示す。１１は半導体基板、１２は下部金属配線層
、１３は層間絶縁膜、１４は上部金属配線層である。従
来の半導体装置の層間絶縁膜（シリコン窒化膜）１３は
，同層間絶縁膜１３形或中の形成温度が一定であク、同
層間絶縁膜１３の膜質の厚さ方向の違いはなかった為、
等方性のドライエッチング技術を用いてのスルーホール
形成で，スルーホール断面にテーパーがつかない為に、
前記層間絶縁膜１３上に形成される上部金属配線層１４
のステップカバレッジを著しく悪化させていた。Prior Art FIG. 2 shows a cross section of a semiconductor device formed by a conventional manufacturing method. 11 is a semiconductor substrate, 12 is a lower metal wiring layer, 13 is an interlayer insulating film, and 14 is an upper metal wiring layer. The interlayer insulating film (silicon nitride film) 13 of the conventional semiconductor device has a constant formation temperature, and there is no difference in the film quality of the interlayer insulating film 13 in the thickness direction. ,
The through-hole is formed using isotropic dry etching technology, so the cross-section of the through-hole does not taper.
Upper metal wiring layer 14 formed on the interlayer insulating film 13
The step coverage was significantly deteriorated.
発明が解決しようとする課題
前記の様な構或では、層間絶縁膜１３のスルーホール断
面にテーパーがつかない為、上部金属配線層１４のステ
ップ力バレッジが悪かった。Problems to be Solved by the Invention In the above structure, the step force barrier of the upper metal wiring layer 14 was poor because the cross section of the through hole in the interlayer insulating film 13 was not tapered.
本発明は上記問題点に対し、良好なステップカバレソジ
を実現するスルーホール形成が可能な層間絶縁膜を有す
る半導体装置の製造方法の提供を目的とする。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device having an interlayer insulating film in which through-hole formation is possible and which realizes a good step coverage strategy.
課題を解決するための手段
この課題を解決する為に、本発明は下部金属配線層と上
部金属配線層間の、層間絶縁膜（シリコン窒化膜）形成
時の形成温度を最初は高温で成長させ、形成中に形成温
度を低温に変化させる事により、前記層間絶縁膜に等方
性ドライエッチング技術を用いてスルーホールを形成す
る事によって、前記層間絶縁膜のスルーホールにテーハ
ーヲつけるものである。Means for Solving the Problem In order to solve this problem, the present invention initially grows the interlayer insulating film (silicon nitride film) at a high temperature between the lower metal wiring layer and the upper metal wiring layer. By changing the formation temperature to a low temperature during formation, a through hole is formed in the interlayer insulating film using an isotropic dry etching technique, thereby providing a taper in the through hole in the interlayer insulating film.
作用
上記の構成によって層間絶縁膜（シリコン窒化膜）のス
ルーホールにテーパーをもたせ，上部金属配線層のステ
ップカパレッジを良好にする事が可能である。Effect: With the above structure, it is possible to make the through hole of the interlayer insulating film (silicon nitride film) taper and to improve the step coverage of the upper metal wiring layer.
実施例
以下、本発明の一実施例について図面を参照しながら説
明する。第１図は本発明の下部金属配線層２と上部金属
配線層４とのスルーホール付近の断面図である。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of the vicinity of a through hole between a lower metal wiring layer 2 and an upper metal wiring layer 4 according to the present invention.
この図よクわかる様に層間絶縁膜３１ｋ形成する時、最
初は高温３８０℃で成長させ形成中に形成温度を低温２
８０℃に変化させる事により、同層間絶縁膜３の膜質に
厚さ方向の変化を生じさせ、膜質の違いから生じる低温
２８０℃成長ではドヲイエッチング時のエッチレートは
早く高温３８０℃成長ではドライエッチング時のエッチ
レートは遅いという特徴を利用し、下部金属配線層２上
のスルーホールにテーパーをつける事による上部金属配
線層４のスルーホール段差でのステップカバレッジを良
好にしている。As can be seen from this figure, when forming the interlayer insulating film 31k, it is initially grown at a high temperature of 380°C, and during the formation, the formation temperature is lowered to a lower temperature of 2.
By changing the temperature to 80°C, the film quality of the interlayer insulating film 3 changes in the thickness direction, and due to the difference in film quality, the etch rate during dry etching is faster in low-temperature 280°C growth, and the dry etching rate is faster in high-temperature 380°C growth. Utilizing the characteristic that the etch rate during etching is slow, the step coverage at the step of the through hole in the upper metal wiring layer 4 is improved by tapering the through hole on the lower metal wiring layer 2.
発明の効果
以上説明してきた様に、本発明は、半導体基板上の下部
金属配線層上の層間絶縁膜にテーパーをもたせ、上部金
属配線層のスルーホール段差部でのステップカバレッジ
を良好にし、スルーホール段差部での段切れを防止する
効果がある。Effects of the Invention As explained above, the present invention provides a tapered interlayer insulating film on a lower metal wiring layer on a semiconductor substrate, improves step coverage at the stepped portion of the through hole in the upper metal wiring layer, and improves the through hole. This has the effect of preventing step breakage at the step portion of the hole.
第１図は本発明の一実施例により形成された半導体装置
の断面図、第２図は従来の半導体装置の断面図である。
１．１１・・・・・・半導体基板、２，１２・・・・・
・下部金属配線層、３，１３・・・・・・層間絶縁膜（
シリコン窒化膜），４．１４・・・・・・上部金属配線
層。FIG. 1 is a sectional view of a semiconductor device formed according to an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. 1.11... Semiconductor substrate, 2,12...
・Lower metal wiring layer, 3, 13... interlayer insulating film (
silicon nitride film), 4.14... Upper metal wiring layer.
Claims (1)
て、第一温度から第二温度へ温度を変化させつつＣＶＤ
シリコン窒化膜を形成して層間絶縁膜とし、しかる後、
ドライエッチングによりスルーホールを形成することを
特徴とする半導体装置の製造方法。In the manufacturing process of semiconductor devices having multilayer metal wiring, CVD is performed while changing the temperature from a first temperature to a second temperature.
A silicon nitride film is formed as an interlayer insulating film, and then,
A method for manufacturing a semiconductor device, characterized by forming through holes by dry etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15344489A JPH0319223A (en) | 1989-06-15 | 1989-06-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15344489A JPH0319223A (en) | 1989-06-15 | 1989-06-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0319223A true JPH0319223A (en) | 1991-01-28 |
Family
ID=15562681
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15344489A Pending JPH0319223A (en) | 1989-06-15 | 1989-06-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0319223A (en) |
-
1989
- 1989-06-15 JP JP15344489A patent/JPH0319223A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH09139429A (en) | Manufacture of semiconductor device | |
| JPH02143527A (en) | Wiring formation | |
| JPH0319223A (en) | Manufacture of semiconductor device | |
| JPS6362107B2 (en) | ||
| JPH043455A (en) | Soi transistor laminated semiconductor device and manufacture thereof | |
| JPH0579165B2 (en) | ||
| JPH02205339A (en) | Manufacture of semiconductor device | |
| US5324536A (en) | Method of forming a multilayered structure | |
| JPS63133550A (en) | Manufacture of semiconductor device | |
| JPS6242522A (en) | Manufacture of semiconductor device | |
| JP2621287B2 (en) | Method of forming multilayer wiring layer | |
| JPS5951549A (en) | Manufacture of integrated circuit device | |
| JPH01214137A (en) | Manufacture of integrated circuit | |
| JP2782912B2 (en) | Method for manufacturing semiconductor device | |
| JPH0273652A (en) | Manufacture of semiconductor device | |
| JPS5885529A (en) | Manufacture of semiconductor device | |
| KR100273224B1 (en) | Method for forming planarization layer of semiconductor device | |
| JPS6249643A (en) | Semiconductor device and its manufacture | |
| JP2984383B2 (en) | Method for manufacturing semiconductor device | |
| JPH06124944A (en) | Semiconductor device | |
| JP2844641B2 (en) | Silicon planarization method | |
| JP2909077B2 (en) | Method for manufacturing semiconductor device | |
| JPH04127425A (en) | Manufacture of semiconductor integrated circuit | |
| JPS5893344A (en) | Semiconductor device and its manufacture | |
| JPH11274106A (en) | Single-wafer cvd apparatus and method therefor |