JPS63133550A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63133550A JPS63133550A JP27977186A JP27977186A JPS63133550A JP S63133550 A JPS63133550 A JP S63133550A JP 27977186 A JP27977186 A JP 27977186A JP 27977186 A JP27977186 A JP 27977186A JP S63133550 A JPS63133550 A JP S63133550A
- Authority
- JP
- Japan
- Prior art keywords
- metal material
- contact hole
- semiconductor device
- wiring
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000011248 coating agent Substances 0.000 claims abstract description 22
- 238000000576 coating method Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 16
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 12
- 239000010937 tungsten Substances 0.000 claims abstract description 12
- 238000002844 melting Methods 0.000 claims abstract description 9
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000001312 dry etching Methods 0.000 claims abstract description 6
- 239000007769 metal material Substances 0.000 claims description 37
- 230000008018 melting Effects 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 abstract description 10
- 229910052751 metal Inorganic materials 0.000 abstract description 9
- 239000002184 metal Substances 0.000 abstract description 9
- 239000010410 layer Substances 0.000 abstract description 6
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 229920001721 polyimide Polymers 0.000 abstract description 3
- 239000004642 Polyimide Substances 0.000 abstract 1
- 239000011347 resin Substances 0.000 abstract 1
- 229920005989 resin Polymers 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は半導体装置の製造方法の改良に関し、更に詳細
には半導体装置の電（至）配線工程において、特にアス
ペクト比の高い微細コンタクトホールへ金属材料を平坦
に埋め込み電極配線を形成する方法の改良に関するもの
である。[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to an improvement in a method for manufacturing a semiconductor device, and more specifically, in the electrical wiring process of a semiconductor device, especially for fine contact holes with a high aspect ratio. The present invention relates to an improvement in a method for forming a flat buried electrode wiring in a metal material.
〈従来の技術及びその問題点〉
従来、半導体装置の製造過程における半導体装置の電極
配線工程においては、層間絶縁膜にコンタクトホールを
形成した後、金属材料を被着して配線の形成を行なって
いる。<Prior art and its problems> Conventionally, in the electrode wiring process of a semiconductor device in the manufacturing process of a semiconductor device, a contact hole is formed in an interlayer insulating film, and then a metal material is deposited to form a wiring. There is.
第２図は従来法によシ形成された電極配線後のコンタク
トホール部の様子を示す基板断面図であり、同図におい
て、２１はｐ型シリコン基板、２２はフィールド酸化膜
、２３はゲート電極、２４はゲート酸化膜、２５はｎ＋
型ソーヌ領域、２６はｎ＋型ドレイン領域、２７は層間
絶縁膜、２８はタングステン７リサイド（ＷＳｉＸ）配
線である。FIG. 2 is a cross-sectional view of a substrate showing the state of a contact hole after electrode wiring formed by a conventional method. In the same figure, 21 is a p-type silicon substrate, 22 is a field oxide film, and 23 is a gate electrode. , 24 is a gate oxide film, 25 is an n+
26 is an n+ type drain region, 27 is an interlayer insulating film, and 28 is a tungsten 7 reside (WSiX) wiring.
上記第２図において層間絶縁膜２７に形成するコンタク
トホールが高アスベ゛クト比の微細コンタクトになると
、従来のスパッタ法あるいはＣＶＤ法による金属材料の
被着ではコンタクトホール内あるいは段差部で断線が発
生する可能性が高い。In FIG. 2 above, when the contact hole formed in the interlayer insulating film 27 becomes a fine contact with a high aspect ratio, when a metal material is deposited by conventional sputtering or CVD methods, disconnection occurs within the contact hole or at the stepped portion. There is a high possibility that it will.
このため最近コンタクトホールにのみ選択的にタングス
テン（Ｗ）を埋め込む技術の研究が活発に研究されてい
る。しかしながらタングステン（Ｗ）の選択成長ではエ
ンクロチメント等のない良質な膜を得るには成長膜厚に
限界があるため、更に金属材料を埋め込む必要があり、
また成長したタングステン（Ｗ）の結晶粒径が大きく、
これによる基板表面の凹凸を緩和しなければならないと
いう問題点があった。For this reason, research on techniques for selectively embedding tungsten (W) only in contact holes has recently been actively conducted. However, in the selective growth of tungsten (W), there is a limit to the thickness of the grown film in order to obtain a high-quality film without encroachments, so it is necessary to further embed a metal material.
In addition, the crystal grain size of the grown tungsten (W) is large,
There is a problem in that it is necessary to alleviate the unevenness of the substrate surface caused by this.
本発明は、上記の点に鑑みて創案されたものであす、ア
スペクト比の高い微細コンタクトホールへ金属材料を平
坦に埋め込み電極配線を形成する方法を提供することを
目的としている。The present invention was devised in view of the above points, and an object of the present invention is to provide a method for forming an electrode wiring by flatly filling a metal material into a fine contact hole having a high aspect ratio.
〈問題点を解決するための手段〉
上記の目的を達成するため、本発明の半導体装置の製造
方法は、半導体基板上もしくは配線上の絶縁膜にコンタ
クトホールを開孔する工程と、このコンタクトホールに
高融点金属材料を選択的に成長させる工程と、全面に金
属材料を被着する工程と、この被着した金属材料上に有
機塗布膜また順
より具体的には、本発明の実施態様として、半導体基板
もしくは配線上の絶縁膜の所定の場所にコンタクトホー
ルを開孔した後、このコンタクトホール内に高融点金属
材料として例えばタングステン（Ｗ）を選択成長させて
選択的に形成し、更に全面に金属材料として例えばタン
グステンシリサイド（ＷＳｉＸ）を被着させ、その後、
有機塗布材料として例えばフォトレジストもしはポリイ
ミド樹脂を回転塗布する。その後、この有機塗布膜と金
属膜のエツチング速度の等しい条件で反応性イオンエツ
チング等のドライエツチングを行なうことにより、コン
タクト部の金属膜を残し、有機塗布膜及び金属膜を平坦
に保って除去し、更に必要に応じて電極あるいは配線用
の金属材料を再度被着して電極配線を行なうように構成
しておシ、このような構成によシコンタクトホールへ金
属材料が平坦に埋め込まれることになる。<Means for Solving the Problems> In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention includes a step of forming a contact hole in an insulating film on a semiconductor substrate or a wiring, and forming a contact hole in an insulating film on a semiconductor substrate or a wiring. More specifically, as an embodiment of the present invention, a step of selectively growing a high melting point metal material on the surface, a step of depositing the metal material on the entire surface, and an organic coating film on the deposited metal material. After forming a contact hole at a predetermined location in an insulating film on a semiconductor substrate or wiring, a high melting point metal material such as tungsten (W) is selectively grown in the contact hole, and then the entire surface is For example, tungsten silicide (WSiX) is deposited on the metal material, and then
For example, photoresist or polyimide resin is spin-coated as an organic coating material. Thereafter, by performing dry etching such as reactive ion etching under conditions where the etching speed of the organic coating film and the metal film are equal, the organic coating film and the metal film are kept flat and removed while leaving the metal film in the contact area. Furthermore, if necessary, the metal material for electrodes or wiring is re-deposited for electrode wiring, and such a configuration allows the metal material to be flatly embedded in the contact hole. Become.
〈実施例〉
以下、図面を参照して本発明の一実施例を詳細に説明す
る。<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図（ａ）乃至（ｅ）はそれぞれ本発明の半導体装置
の製造方法の一実施例の各工程を示す基板断面を示す図
である。FIGS. 1(a) to 1(e) are diagrams each showing a cross section of a substrate showing each step of an embodiment of the method for manufacturing a semiconductor device of the present invention.
第１図（ａ）において、ｌはｐ型シリコン基板、２はフ
ィールド酸化膜、３はゲート電極、４はゲート酸化膜、
５はｎ＋型ソーヌ領域、６はｎ＋型ドレイン領域であシ
、ｐ型シリコン基板に半導体素子を作り込んだ後、層間
絶縁膜７を形成し、ソース及びドレイン領域５．６との
層間配線を行なうため、層間絶縁膜７の所定位置にアス
ペクト比の高い微細コンタクトホー／ｌｚ８を形成した
。次に第１図（ｂ）に示すように選択成長法により高融
点金属材料９としてタングステン（Ｗ）を選択的にコン
タクトホー７１／ ８内に形成した。この場合、層間絶
縁膜７の層厚によっても異なるが、コンタクトホー／Ｉ
／８内への高融点金属材料９の埋め込みは、第１図（ｂ
）に示すように完全に埋め込まない状態（Ｈａｌｆ −
ｆｉｌｌｉｎｇ ）でも良く、また完全に埋め込んだ状
態（Ｏｖｅｒ−ｆｉｌｌｉｎｇ）でも良い。次に第１図
（ｃ）に示すように金属材料１０としてタングステンシ
リサイド（ＷＳｉ）（）を１μｍの厚さに被着し、更に
有機塗布膜１１としてフォトレジストまたはポリイミド
系樹脂を全面に回転塗布によ多形成した。この有機塗布
膜１１の塗布工程においては、塗布する膜１１ｏ厚みは
コンタクト部の段差を充分に平坦化し得る厚みがあれば
良く、約ガス系による反応性イオンエツチング法によシ
、有機塗布膜１１及び金属材料（ＷＳｉＸ膜）１０を等
速エツチング条件によって除去した。第１図（ｄ）はコ
ンタクトホール部８のタングステン（Ｗ）［１２及びタ
ングステンシリサイド（Ｗ ５ｉＸ）膜１３を残し、他
部分の有機塗布膜１１及びタングステンシリサイド（Ｗ
Ｓ＋ｘ ）膜１０を完全に等速エツチングによシ除去
した状態を示しておシ、このような一連の工程によシ、
コンタクトホー／Ｌ／８に金属材料（Ｗ及びＷＳｉ）０
が平坦に埋め込まれることになる。In FIG. 1(a), l is a p-type silicon substrate, 2 is a field oxide film, 3 is a gate electrode, 4 is a gate oxide film,
5 is an n+ type Saone region, and 6 is an n+ type drain region. After forming a semiconductor element on a p type silicon substrate, an interlayer insulating film 7 is formed, and interlayer wiring with the source and drain regions 5.6 is formed. In order to do this, a fine contact hole /lz8 having a high aspect ratio was formed at a predetermined position of the interlayer insulating film 7. Next, as shown in FIG. 1(b), tungsten (W) was selectively formed in the contact hole 71/8 as a high melting point metal material 9 by a selective growth method. In this case, although it varies depending on the layer thickness of the interlayer insulating film 7, the contact hole/I
The embedding of the high melting point metal material 9 into /8 is shown in Figure 1 (b
) as shown in the state where it is not completely embedded (Half −
It may be in a completely buried state (Over-filling). Next, as shown in FIG. 1(c), tungsten silicide (WSi) () is coated to a thickness of 1 μm as a metal material 10, and then a photoresist or polyimide resin is coated by rotation on the entire surface as an organic coating film 11. A large number was formed. In the process of applying the organic coating film 11, the thickness of the film 11o to be coated is sufficient as long as it can sufficiently flatten the level difference in the contact portion, and the organic coating film 11 is coated using a reactive ion etching method using a gas system. and the metal material (WSiX film) 10 were removed under uniform etching conditions. In FIG. 1(d), tungsten (W) [12 and tungsten silicide (W5iX) film 13 in the contact hole portion 8 are left, and the organic coating film 11 and tungsten silicide (W5iX) film 13 are left in the other parts.
S+x) shows a state in which the film 10 has been completely removed by uniform etching;
Metal material (W and WSi) 0 for contact hole/L/8
will be embedded flatly.
なお、箸１図（ｂ）に示す工程において、高融点金属材
料９をコンタクトホー／Ｌ／８内に完全に埋め込んだ状
態（０ｖｅｒ −ｆｉｌｌｉｎｇ）であれば、第１図（
ｄ）に示す工程において、有機塗布膜１１、金属材料１
０及び９の等速エツチング条件によって処理するように
なせば良い。In addition, in the process shown in FIG. 1(b) of chopsticks 1, if the high melting point metal material 9 is completely buried in the contact hole/L/8 (0ver-filling), the process shown in FIG.
In the step shown in d), the organic coating film 11, the metal material 1
The process may be carried out under constant speed etching conditions of 0 and 9.
その後、残存する有機塗布膜を完全に除去し、再度、タ
ングステンシリサイド（Ｗ Ｓ ｌ）（）膜１４を被着
形成し、第１図（ｅ）に示すように所定の電極配線を形
成した。Thereafter, the remaining organic coating film was completely removed, and a tungsten silicide (WSI) ( ) film 14 was deposited again to form predetermined electrode wiring as shown in FIG. 1(e).
以上のようにして、アスペクト比の高い微細コンタクト
ホー／Ｉ／８に、タングステン（Ｗ）の選択成長及び金
属材料のエッチバック技術によって、平坦に金属材料を
埋め込み、コンタクトホール内あるいは段差部で断線を
生じないで電極配線を形成した。As described above, by selectively growing tungsten (W) and metal material etch-back technology, metal material is buried flatly in the fine contact hole /I/8 with a high aspect ratio, and disconnections are created within the contact hole or at the stepped portion. Electrode wiring was formed without causing any damage.
なお、本発明は上記実施例に限定されるものではなく、
その主旨を逸脱しない範囲で種々変形して実施すること
が出来、例えば半導体基板表面の平坦化を行なうための
有機塗布材料に代えて無機塗布材料を用いても良く、ま
た金属材料はタングステンシリサイド（Ｗ Ｓｔｘ ）
に代えてアルミニウム（Ａｎ ）等の他の金属材料を用
いても良いことは言うまでもない。Note that the present invention is not limited to the above embodiments,
Various modifications can be made without departing from the spirit of the invention. For example, an inorganic coating material may be used instead of an organic coating material for flattening the surface of a semiconductor substrate, and the metal material may be tungsten silicide ( W Stx)
It goes without saying that other metal materials such as aluminum (An) may be used instead.
また金属材料のエツチング除去は、その一部を残して電
極配線用の金属材料として用いるようになしても良いこ
とは言うまでもない。It goes without saying that when the metal material is removed by etching, a part of it may be left and used as the metal material for electrode wiring.
〈発明の効果〉
以上のように本発明によれば、アスペクト比が高い微細
コンタクトホールであっても平坦に金属材料を埋め込む
ことが出来、その結果、コンタクトホール内あるいは段
差部での断線を防止することが出来電極配線の品質及び
半導体装置の品質を著しく向上させることが出来る。<Effects of the Invention> As described above, according to the present invention, even a fine contact hole with a high aspect ratio can be filled with metal material evenly, and as a result, disconnection within the contact hole or at a stepped portion can be prevented. As a result, the quality of electrode wiring and the quality of semiconductor devices can be significantly improved.
また、本発明は多層配線工程においても、著しく品質を
向上させることが出来る。Further, the present invention can significantly improve quality even in a multilayer wiring process.
第１図（ａ）乃至（ｅ）はそれぞれ本発明の一実施例と
しての半導体装置の製造方法の各工程を示す基板断面を
示す図、第２図は従来法によ多形成された電極配線後の
コンタクトホール部の様子を示す基板断面図である。
ｌ・・・ｐ型シリコン基板、 ２・・・フィールド酸化
膜、 ３・・・ゲート電極、 ４・・・ゲート酸化膜、
５・・・１型ソース領域、 ６・・・ｎ＋型ドレイン領
域、 ７・・・層間絶縁膜、 ８・・・コンタクト
ホール、 ９・・・タングステン（Ｗ）、 １０・
・・タングステンシリサイド（ＷＳｉＸ）、 １１・
・・有機塗布膜、 １２・・・タングステン（Ｗ）、
１３・・・タングステンシリサイド（ＷＳｉ）０．１４
・・・電極配線（ＷＳｉＸ）。1(a) to 1(e) are diagrams each showing a cross section of a substrate showing each step of a method for manufacturing a semiconductor device as an embodiment of the present invention, and FIG. 2 is an electrode wiring formed by a conventional method. FIG. 7 is a cross-sectional view of the substrate showing the state of the contact hole portion afterward. l...p-type silicon substrate, 2... field oxide film, 3... gate electrode, 4... gate oxide film,
5... 1 type source region, 6... n+ type drain region, 7... interlayer insulating film, 8... contact hole, 9... tungsten (W), 10.
...Tungsten silicide (WSiX), 11.
...Organic coating film, 12...Tungsten (W),
13...Tungsten silicide (WSi) 0.14
... Electrode wiring (WSiX).
Claims (1)
ホールを開孔する工程と、 該コンタクトホールに高融点金属材料を選択成長させる
工程と、 全面に金属材料を被着する工程と、 該被着した金属材料上に有機塗布膜または無機塗布膜を
形成する工程と、 ドライエッチングにより、上記塗布膜及び少なくとも金
属材料の一部を除去する工程と、を備えてなることを特
徴とする半導体装置の製造方法。 ２、前記除去する工程は、ドライエッチングにより全面
が平坦になるまで上記塗布膜及び金属材料の一部を除去
して電極もしくは配線を形成するようになしたことを特
徴とする特許請求の範囲第１項記載の半導体装置の製造
方法。 ３、前記除去する工程は、ドライエッチングにより上記
コンタクトホール部の金属材料のみを残して上記金属材
料の全部を除去する工程を含み、更に電極あるいは配線
用の金属材料を再度被着し、電極配線を形成する工程を
備えてなることを特徴とする特許請求の範囲第１項記載
の半導体装置の製造方法。 ４、前記コンタクトホールへ選択的に埋め込む高融点金
属材料がタングステン（Ｗ）であり、金属材料がタング
ステンシリサイド（ＷＳｉ＿Ｘ）であることを特徴とす
る特許請求の範囲第１項記載の半導体装置の製造方法。 ５、前記ドライエッチングによる平坦化工程は前記塗布
膜と金属材料の等速エッチング条件で行ことを特徴とす
る特許請求の範囲第１項記載の半導体装置の製造方法。[Claims] 1. A step of opening a contact hole in an insulating film on a semiconductor substrate or wiring, a step of selectively growing a high melting point metal material in the contact hole, and a step of depositing a metal material on the entire surface. a step of forming an organic coating film or an inorganic coating film on the deposited metal material; and a step of removing the coating film and at least a part of the metal material by dry etching. A method for manufacturing a featured semiconductor device. 2. In the removing step, the coating film and part of the metal material are removed by dry etching until the entire surface becomes flat to form an electrode or wiring. A method for manufacturing a semiconductor device according to item 1. 3. The removing step includes a step of removing all of the metal material by dry etching, leaving only the metal material in the contact hole portion, and then re-depositing the metal material for the electrode or wiring to form the electrode wiring. 2. A method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming a semiconductor device. 4. Manufacturing the semiconductor device according to claim 1, wherein the high melting point metal material selectively filled into the contact hole is tungsten (W), and the metal material is tungsten silicide (WSi_X). Method. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the flattening step by dry etching is performed under conditions of uniform etching of the coating film and the metal material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27977186A JPS63133550A (en) | 1986-11-26 | 1986-11-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27977186A JPS63133550A (en) | 1986-11-26 | 1986-11-26 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63133550A true JPS63133550A (en) | 1988-06-06 |
| JPH0587133B2 JPH0587133B2 (en) | 1993-12-15 |
Family
ID=17615684
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27977186A Granted JPS63133550A (en) | 1986-11-26 | 1986-11-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63133550A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4933297A (en) * | 1989-10-12 | 1990-06-12 | At&T Bell Laboratories | Method for etching windows having different depths |
| JPH02203523A (en) * | 1989-02-02 | 1990-08-13 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPH0373531A (en) * | 1989-08-14 | 1991-03-28 | Nec Corp | Manufacture of semiconductor device provided with multilayer wiring structure |
| US5223455A (en) * | 1987-07-10 | 1993-06-29 | Kabushiki Kaisha Toshiba | Method of forming refractory metal film |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0589682U (en) * | 1992-01-13 | 1993-12-07 | フクビ化学工業株式会社 | Double floor panel auxiliary legs |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6197826A (en) * | 1984-10-18 | 1986-05-16 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS61154150A (en) * | 1984-12-27 | 1986-07-12 | Matsushita Electronics Corp | Manufacture of semiconductor device |
-
1986
- 1986-11-26 JP JP27977186A patent/JPS63133550A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6197826A (en) * | 1984-10-18 | 1986-05-16 | Matsushita Electronics Corp | Manufacture of semiconductor device |
| JPS61154150A (en) * | 1984-12-27 | 1986-07-12 | Matsushita Electronics Corp | Manufacture of semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5223455A (en) * | 1987-07-10 | 1993-06-29 | Kabushiki Kaisha Toshiba | Method of forming refractory metal film |
| JPH02203523A (en) * | 1989-02-02 | 1990-08-13 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
| JPH0373531A (en) * | 1989-08-14 | 1991-03-28 | Nec Corp | Manufacture of semiconductor device provided with multilayer wiring structure |
| US4933297A (en) * | 1989-10-12 | 1990-06-12 | At&T Bell Laboratories | Method for etching windows having different depths |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0587133B2 (en) | 1993-12-15 |
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| EXPY | Cancellation because of completion of term |