JPS63236317A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63236317A JPS63236317A JP62070769A JP7076987A JPS63236317A JP S63236317 A JPS63236317 A JP S63236317A JP 62070769 A JP62070769 A JP 62070769A JP 7076987 A JP7076987 A JP 7076987A JP S63236317 A JPS63236317 A JP S63236317A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- semiconductor device
- manufacturing
- contact hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000010410 layer Substances 0.000 claims abstract description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- 239000011574 phosphorus Substances 0.000 claims abstract description 8
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 4
- 239000012535 impurity Substances 0.000 claims description 27
- 238000009792 diffusion process Methods 0.000 claims description 19
- 238000010438 heat treatment Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 238000000605 extraction Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 10
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 abstract description 5
- -1 phosphorus ions Chemical class 0.000 abstract description 4
- 229910015900 BF3 Inorganic materials 0.000 abstract description 3
- 239000002019 doping agent Substances 0.000 abstract 3
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 230000001133 acceleration Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
この発明は、コンタクト孔の形成後の熱処理による層間
絶縁１１９（ｌＩｉｌｌえばＢＰＳＧ膜〉からコンタク
ト孔内への不純物のドーピングを防止するための半導体
装置の製造方法に関するもので、特に自己整合’ＪＡコ
ンタクト （３ｅＮ −Ａ １ｉｑｎｅｄＣｏｎｔａｃ
ｔ、以下ＳＡＣと略称する）技術に使用されるものであ
る。Detailed Description of the Invention [Objective of the Invention] (Industrial Field of Application) The present invention is directed to doping of impurities into the contact hole from the interlayer insulation 119 (for example, a BPSG film) by heat treatment after forming the contact hole. It relates to a semiconductor device manufacturing method to prevent self-aligned contact (3eN-A 1iqnedContac).
t, hereinafter abbreviated as SAC) technology.
（従来の技術）
近年、素子の微細化とともにコンタクト孔の部方向の寸
法の縮小が進み、合わせてコンタクト孔周りのアライメ
ント余裕のスケールダウンにも一段と拍車が掛かってき
たため、各方面で拡散層に対するＳＡＣ技術が検問され
ている。(Prior art) In recent years, with the miniaturization of elements, the dimensions of contact holes have been reduced in the direction of their parts, and at the same time, the scaling down of alignment margins around contact holes has also accelerated. SAC technology is under scrutiny.
ところで、拡散層上の層間絶縁膜としてはＣＶＤ−８ｉ
０２膀と共に、その上層膜として従来からＢ Ｐ Ｓ
Ｇ 模が広く用いられているが、低温リフローの要り＾
から最近（ユ特にＢＰＳＧＩ中の不純物濃度を増加させ
ている。このため、ＳＡＣ技Ｋｉの一つであるコンタク
ト孔の形成後に拡散層と同種のイオン注入を行なう方法
を取る場合には、コンタクト孔の形成後の熱処理工程が
必ず必要となる。 この際、上）ホしたようにＢ Ｐ
Ｓ Ｇ Ｉｇの不！Ｖ１１１７１ａ度を高く設定してい
ると、この高濃度Ｂ Ｐ Ｓ Ｇ １１９からコンタク
ト孔内の不純物層へ不純物がドーピングされ、配線層と
拡ｒＩｌ＠間の電流−電圧特性（コンタク１−特性）が
変化する欠点がある。By the way, the interlayer insulating film on the diffusion layer is CVD-8i.
02 Along with the bladder, BPS has traditionally been used as its upper layer membrane.
G model is widely used, but low temperature reflow is required ^
Recently, the impurity concentration in BPSGI has been increasing. Therefore, when using the method of implanting the same type of ion as the diffusion layer after forming the contact hole, which is one of the SAC techniques, it is necessary to A heat treatment step is always required after the formation of B P
S G Ig no fu! When the V11171a degree is set high, impurities are doped into the impurity layer in the contact hole from this high concentration BPS G 119, and the current-voltage characteristics (contact 1-characteristics) between the wiring layer and the extended rIl@ are changed. There are drawbacks that change.
第２図は、半導体装置における上述したコンタクト孔周
辺の構成を抽出して示しており、図において、１１は半
導体格板、１２は上記半導体基板１１の主表面に形成さ
れた素子間分離膜、１３は不純物拡散層、１４ｉ、ｔＣ
ＶＤ−８ｉ ０２ ｆｉｌ、１５はボ０：ｚ及Ｕリンを
高濃度に含有したシリカガラス（ＢＰＳＧｌｌＪ）、１
Ｇはコンタクト孔１７の形成後の熱処理時に上記ＢＰＳ
Ｇ！１１１５からの不ｌ１Ｔｉ物の導入によって形成さ
れた不純物ドーピング店である。FIG. 2 extracts and shows the structure around the above-mentioned contact hole in a semiconductor device. In the figure, 11 is a semiconductor lattice plate, 12 is an inter-element isolation film formed on the main surface of the semiconductor substrate 11, 13 is an impurity diffusion layer, 14i, tC
VD-8i 02 fil, 15 is silica glass containing a high concentration of Bo0:z and U phosphorus (BPSGllJ), 1
G is the BPS during the heat treatment after forming the contact hole 17.
G! 1115 is an impurity doping store formed by the introduction of an Ti1 substance from 1115.
第３図（ａ）、（ｂ）は、上記コンタクト孔１７の？を
流−電圧特性を示すもので、＜ａ＞図はコンタクト孔の
形成後に熱処理を行なわなかった場合、（ｂ）図はコン
タクト孔の形成後に熱処理を行なった場合の特性をそれ
ぞれ示しており、アルミ配線とＰ“型拡故層とのコンタ
クトを取る場合のものである。図示する如く熱処理を行
なわない場合には０形の電流−電圧特性を示すのに対し
、熱処理を（１なうと電圧の上昇に対する電流の上昇が
少ない、すなわちコンタクト抵抗が上昇する。これは、
上記ＢＰＳＧＩＩ（Ｊ１５中の不純物、特にリンがコン
タクト孔１７内の基板１１表面に導入され、不純物拡散
層１３がＰ＋型の場合にはこの拡散層１３の不純物濃度
が低下することによる。FIGS. 3(a) and 3(b) show the shape of the contact hole 17. Figure <a> shows the characteristics when heat treatment is not performed after forming the contact hole, and Figure (b) shows the characteristics when heat treatment is performed after forming the contact hole. This is when contact is made between the aluminum wiring and the P" type spreading layer. As shown in the figure, when heat treatment is not performed, the current-voltage characteristic is 0 type, but when heat treatment is performed (1), the voltage The increase in current is small with respect to the increase in , that is, the contact resistance increases.
This is because impurities in the BPSGII (J15), especially phosphorus, are introduced into the surface of the substrate 11 within the contact hole 17, and when the impurity diffusion layer 13 is of P+ type, the impurity concentration of the diffusion layer 13 is reduced.
（発明が解決しようとする問題点）
ト述したように、従来の半導体装置の製造方法では、コ
ンタクト孔内への層間絶縁膜中に含有される不純物の導
入によりコンタクト特性が変化する欠点がある。(Problems to be Solved by the Invention) As mentioned above, the conventional method for manufacturing semiconductor devices has the disadvantage that the contact characteristics change due to the introduction of impurities contained in the interlayer insulating film into the contact hole. .
この発明は上記のような事情に鑑みてなされたもので、
その目的とするところは、不純物の導入によるコンタク
ト特性の変動を防止できる半導体装置の製造方法を促供
することである。This invention was made in view of the above circumstances,
The purpose is to provide a method for manufacturing a semiconductor device that can prevent variations in contact characteristics due to the introduction of impurities.
［発明の構成］
（問題点を解決するための手段）
すなわち、この発明においては、上記の目的を達成する
ために、半導体基板上に素子量分１１！！ 摸を形成し
、この素子間分離躾で分離された素子領域における半導
体基板の表面領域に拡散層を形成した後、上記半導体基
板の全面に層間絶縁膜としてシリコン酸化膜及び不純物
を高濃度に含有するシリカガラス膜を順次堆積形成し、
第１の熱処理を行なう。次に全面に第１の絶縁膜を堆積
形成し、上記拡散層上の上記層間絶縁膜及び第１の絶縁
膜に電極取出し用のコンタクト孔を開孔した後、全面に
第２の絶縁膜を堆積形成する。そして、異方性エツチン
グを行なって上記第２の絶縁膜を除去し、上記コンタク
ト孔の側壁部のみに残存させた状態で第２の熱処理を行
なうようにしている。[Structure of the Invention] (Means for Solving the Problems) That is, in this invention, in order to achieve the above object, 11! ! After forming a diffusion layer on the surface region of the semiconductor substrate in the element region separated by this inter-element isolation process, a silicon oxide film and impurities are added at a high concentration as an interlayer insulating film over the entire surface of the semiconductor substrate. A silica glass film is sequentially deposited to form a
A first heat treatment is performed. Next, a first insulating film is deposited on the entire surface, and a contact hole for taking out an electrode is formed in the interlayer insulating film on the diffusion layer and in the first insulating film, and then a second insulating film is formed on the entire surface. Deposits form. Then, anisotropic etching is performed to remove the second insulating film, and a second heat treatment is performed with the second insulating film remaining only on the side wall of the contact hole.
（作用）
このような製造工程では、不純物が高濃度に含有された
シリカガラス膜をこの膜の下面に形成したシリコン酸化
膜、上面に形成した第１の絶縁膜、及びコンタクト孔の
側壁部に残存させた第２の絶縁膜で覆った状態で熱処理
（第２の熱処理）するので、上記シリカガラス膜中に含
有された不純物がコンタクト孔内の拡ｐｌＩ層に導入さ
れることがなく、不純物の導入によるコンタクト特性の
変動を防止できる。(Function) In such a manufacturing process, a silica glass film containing a high concentration of impurities is applied to the silicon oxide film formed on the bottom surface of this film, the first insulating film formed on the top surface, and the side wall of the contact hole. Since the heat treatment (second heat treatment) is performed while covered with the remaining second insulating film, the impurities contained in the silica glass film are not introduced into the expanded plI layer in the contact hole, and the impurities are It is possible to prevent fluctuations in contact characteristics due to the introduction of
（実施例）
以下、この発明の一実施例について図面を参照して説明
する。第１図（ａ）〜（Ｃ）は製造工程を順次示すもの
で、まず（ａ）図に示すようにＮ型またはＰ型（面方位
１００）の半導体基板１８上の主表面に例えばＬＯＣＯ
８法を用いて素子間分離膜１９を選択的に形成した後、
この素子間分離膜１９で分離された素子領域の半導体基
板１８中に不純物拡散層２０を選択的に形成する。上記
拡散層２０としてＮ＋型を形成する場合には、例えばヒ
素イオンＡｓ＋を加速電圧４０ＫｅＶ、ドーズ量５×１
０１’ｃｍ゛２の条件でイオン注入する。また、Ｐ１型
を形成する場合には、フッ化ホウ素イオンＢＦ２＋を加
速電圧５０ＫｅＶ、ドーズ量５×１０１’ｃｍ’２の条
件でイオン注入する。続いて、層間絶縁膜として全面に
ＣＶＤ−８ｉＯ２膜２１（厚さ４０００人程度１、及び
ボロンＢ及びリンＰ原子を２〜５ｘ １０２１ ｃｒｒ
ｒｚ程度含有する低温リフロー用ＢＰＳＧ膜２２（厚さ
６０００〜１００００人程度１を堆積形成した後、熱処
理（８００℃以上でＰＯＣλ３拡散）を行なう。その後
、全面に第１の絶縁膜２３を堆積形成する。この絶縁８
２３としては、例えばＣＶＤ−３ｉ０２膜であれば５０
０〜１５００人程度の厚さ、ＣｖＤ・３ｉ３Ｎ＋ｉｌな
ら５００〜１０００人程１の厚さに形成する。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIGS. 1(a) to (C) sequentially show the manufacturing process. First, as shown in FIG. 1(a), for example, a LOCO
After selectively forming the inter-element isolation film 19 using the 8 method,
An impurity diffusion layer 20 is selectively formed in the semiconductor substrate 18 in the element region separated by the element isolation film 19. When forming the N+ type diffusion layer 20, for example, arsenic ions As+ are applied at an acceleration voltage of 40 KeV and a dose of 5×1.
Ion implantation is performed under the condition of 01'cm2. Further, when forming a P1 type, boron fluoride ions BF2+ are implanted under conditions of an acceleration voltage of 50 KeV and a dose of 5 x 101'cm'2. Subsequently, a CVD-8iO2 film 21 (approximately 4000 crr thick) and 2 to 5 x 1021 crr boron B and phosphorus P atoms are deposited on the entire surface as an interlayer insulating film.
After depositing a BPSG film 22 for low-temperature reflow containing about rz (about 6,000 to 10,000 layers 1 in thickness), heat treatment (POC λ3 diffusion at 800° C. or higher) is performed. After that, a first insulating film 23 is deposited on the entire surface. This insulation 8
For example, in the case of CVD-3i02 film, 23 is 50
For CvD・3i3N+il, it is formed to a thickness of about 500 to 1000 people.
次に、上記絶縁膜２３．ＢＰＳＧ躾２２、及びＣＶＤ−
８ｉ ０２ 膜２１を異方性エツチングして上記拡散Ｗ
４２０上にコンタクト孔２４を開孔する。引続き、全面
に上記第１の絶縁１Ｉ２３と同材質、同模厚の第２の絶
縁膜２５を堆積形成し （（ｂ）図に図示）、異方性エ
ツチングを行なってこの絶縁ｉ！２５を除去すると、上
記コンタクト孔２４の側壁部のみに上記第２の絶縁１１
２５が残存され（Ｃ）図に示すようになる。ここまでの
工程によって、上記ＢＰＳＧ１２２１７）下面にはＣｖ
Ｄ−８ｉＯ２２１、上面には第１の絶縁膜２３、側面に
は残存された第２の絶縁ＩＩ＃２５が形成され、外部と
完全に分離される。Next, the insulating film 23. BPSG discipline 22, and CVD-
8i 02 The film 21 is anisotropically etched to remove the above diffusion W.
A contact hole 24 is drilled on 420. Subsequently, a second insulating film 25 made of the same material and having the same thickness as the first insulating film 1I23 is deposited on the entire surface (as shown in figure (b)), and anisotropic etching is performed to form this insulating film i! 25, the second insulation 11 is formed only on the side wall of the contact hole 24.
25 remains as shown in Figure (C). Through the steps up to this point, the Cv
A first insulating film 23 is formed on the top surface of the D-8iO 221, and a remaining second insulating film II#25 is formed on the side surface, completely separating it from the outside.
この後、ＳＡＣ技術の一例として上記拡散層２０と同種
のイオン注入、例えばＮ“型の拡散層を形成する場合に
は、リンイオンＰゝを加速電圧４０ＫｅＶ、ドーズＦ！
ｉ１〜５×１０工５ｃｍ′２の条件でイオン注入する。After this, as an example of the SAC technique, when ions of the same type as the diffusion layer 20 are implanted, for example, to form an N" type diffusion layer, phosphorus ions P are injected at an acceleration voltage of 40 KeV and a dose of F!
Ion implantation is performed under the conditions of i1~5×10×5 cm′2.
また、Ｐ＋型の不純物層を形成する場合にはフッ化ホウ
素イオンＢＦ２＋を加速電圧４０ＫｅＶ、ドーズｆｆ１
１〜５Ｘ１０”ｃｍ”２の条件でイオン注入する。次に
、８００℃以上の温度で熱処理を行なう。この時の熱工
程はファーネスアニールあるいはラビッドサーマルアニ
ールである。その後、配線層を形成して上記拡散層２０
とこの配線層とを接続する（図示せず）。In addition, when forming a P+ type impurity layer, boron fluoride ions BF2+ are applied at an acceleration voltage of 40 KeV and a dose of ff1.
Ion implantation is performed under conditions of 1 to 5 x 10"cm"2. Next, heat treatment is performed at a temperature of 800° C. or higher. The thermal process at this time is furnace annealing or rapid thermal annealing. After that, a wiring layer is formed to form the diffusion layer 20.
and this wiring layer (not shown).
このような製造方法によれば、コンタクト孔２４の形成
優に８００°Ｃ以上の高い温度で熱処理を行なッテも、
ＢＰＳＧＩＩＩ２２ハＣＶＤ−８ｉ ０２２１゜第１の
絶縁膜２３、及び第２の絶縁ＰＩＡ２５で覆われている
ので、こ１７）ＢＰＳＧｇ１２２からコンタクト孔２４
内の拡散層２０中に不純物が導入されるのを防止できる
。従って、コンタクト孔２４内の拡散ＩＦ！１２０に不
純物が導入されることによるコンタクト抵抗の上昇を防
止して安定なコンタクト特性が得られる。According to such a manufacturing method, the contact hole 24 can be formed by heat treatment at a high temperature of 800°C or higher.
BPSGIII22CVD-8i 0221°Since it is covered with the first insulating film 23 and the second insulating PIA25, this 17) contact hole 24 is formed from the BPSGg122.
It is possible to prevent impurities from being introduced into the diffusion layer 20 inside. Therefore, the diffusion IF in the contact hole 24! Stable contact characteristics can be obtained by preventing an increase in contact resistance due to the introduction of impurities into 120.
なお、上記実施例では不純物を高濃度に含有するシリカ
ガラス膜としてＢＰＳＧＩＩＱを例に取って説明したが
、ＰＳＧ膜であっても上記実施例と同様な効果が得られ
るのは勿論である。In the above embodiments, BPSGIIQ was used as an example of a silica glass film containing impurities at a high concentration, but it goes without saying that the same effects as in the above embodiments can also be obtained using a PSG film.
［発明の効果］
以上説明したように、この発明によれば、不純物の導入
によるコンタクト特性の変動を防止できる半導体装置の
製造方法が得られる。[Effects of the Invention] As described above, according to the present invention, a method for manufacturing a semiconductor device is provided that can prevent variations in contact characteristics due to the introduction of impurities.
第１図はこの発明の一実施例に係わる半導体装置の製造
方法について説明するための図、第２図は従来の半導体
装置の製造方法について説明するための図、第３図は従
来の製造方法で形成した場合のコンタクト特性について
説明するための図である。
１８・・・半導体基板、１９・・・素子間分離膜、２０
・・・不純物拡散層、２１・・・ＣＶＤ−８ｉＯｚ膜、
２２・・・ＢＰＳ、Ｇ膜、２３・・・第１の絶縁膜、
２４・・・コンタクト孔、２５・・・第２の絶縁膜。
出願人代理人 弁理士 鈴江武彦
第１図FIG. 1 is a diagram for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a diagram for explaining a conventional method for manufacturing a semiconductor device, and FIG. 3 is a diagram for explaining a conventional manufacturing method. FIG. 4 is a diagram for explaining the contact characteristics when formed with the above. 18... Semiconductor substrate, 19... Interelement isolation film, 20
... impurity diffusion layer, 21 ... CVD-8iOz film,
22... BPS, G film, 23... First insulating film,
24... Contact hole, 25... Second insulating film. Applicant's agent Patent attorney Takehiko Suzue Figure 1
Claims (4)
理を行なう半導体装置の製造方法において、半導体基板
上に素子間分離膜を形成する工程と、この素子間分離膜
で分離された素子領域における半導体基板の表面領域に
不純物拡散層を形成する工程と、上記半導体基板の全面
に層間絶縁膜としてシリコン酸化膜及び不純物を高濃度
に含有するシリカガラス膜を順次堆積形成する工程と、
第１の熱処理を行なう工程と、全面に第１の絶縁膜を堆
積形成する工程と、上記不純物拡散層上の上記層間絶縁
膜及び第１の絶縁膜に電極取出し用のコンタクト孔を開
孔する工程と、全面に第２の絶縁膜を堆積形成する工程
と、異方性エッチングを行なって上記第２の絶縁膜を除
去し上記コンタクト孔の側壁部のみに残存させる工程と
、第２の熱処理を行なう工程とを具備することを特徴と
する半導体装置の製造方法。(1) In a method for manufacturing a semiconductor device in which a heat treatment is performed after forming a contact hole in an electrode extraction port, a step of forming an isolation film on a semiconductor substrate and a step of forming an isolation film on an element region separated by this isolation film are performed. a step of forming an impurity diffusion layer in a surface region of a semiconductor substrate; a step of sequentially depositing a silicon oxide film and a silica glass film containing a high concentration of impurities as an interlayer insulating film over the entire surface of the semiconductor substrate;
A step of performing a first heat treatment, a step of depositing a first insulating film on the entire surface, and forming a contact hole for taking out an electrode in the interlayer insulating film and the first insulating film on the impurity diffusion layer. a step of depositing a second insulating film on the entire surface; a step of performing anisotropic etching to remove the second insulating film so that it remains only on the side wall of the contact hole; and a second heat treatment. A method for manufacturing a semiconductor device, comprising the steps of:
、リンであることを特徴とする特許請求の範囲第１項記
載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the impurity contained in the silica glass at a high concentration is phosphorus.
、ボロン及びリンであることを特徴とする特許請求の範
囲第１項記載の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1, wherein the impurities contained in the silica glass at a high concentration are boron and phosphorus.
ｉＯ＿２膜またはＣＶＤ・Ｓｉ＿３Ｎ＿４膜であること
を特徴とする特許請求の範囲第１項記載の半導体装置の
製造方法。（５）前記第２の熱処理工程は、前記シリカ
ガラスに含有されるリンの濃度が１０＾２＾１ｃｍ＾３
以上の時には８００℃以上の温度で行なうことを特徴と
する特許請求の範囲第２項または第３項記載の半導体装
置の製造方法。(4) The first and second insulating films are each formed by CVD/S.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the film is an iO_2 film or a CVD/Si_3N_4 film. (5) In the second heat treatment step, the concentration of phosphorus contained in the silica glass is 10^2^1 cm^3
The method for manufacturing a semiconductor device according to claim 2 or 3, wherein the above steps are carried out at a temperature of 800° C. or higher.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62070769A JPS63236317A (en) | 1987-03-25 | 1987-03-25 | Manufacture of semiconductor device |
| KR1019880003237A KR920001032B1 (en) | 1987-03-25 | 1988-03-25 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62070769A JPS63236317A (en) | 1987-03-25 | 1987-03-25 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63236317A true JPS63236317A (en) | 1988-10-03 |
Family
ID=13441057
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62070769A Withdrawn JPS63236317A (en) | 1987-03-25 | 1987-03-25 | Manufacture of semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS63236317A (en) |
| KR (1) | KR920001032B1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63253647A (en) * | 1987-04-10 | 1988-10-20 | Nec Corp | Semiconductor device |
| JPH04356944A (en) * | 1991-04-03 | 1992-12-10 | Matsushita Electron Corp | Semiconductor device and its manufacture |
| JPH06169021A (en) * | 1992-11-30 | 1994-06-14 | Nec Corp | Semiconductor device and manufacture thereof |
| KR100417645B1 (en) * | 1996-12-28 | 2004-04-13 | 주식회사 하이닉스반도체 | Method for forming interlayer dielectric of semiconductor device |
| JP2009004573A (en) * | 2007-06-21 | 2009-01-08 | Denso Corp | Silicon carbide semiconductor device and manufacturing method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52104087A (en) * | 1976-02-27 | 1977-09-01 | Hitachi Ltd | Preparation of inter-layer insulation film utilized in multi-layer wir ing of electronic parts |
| JPS58166766A (en) * | 1982-03-27 | 1983-10-01 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS59125620A (en) * | 1983-01-05 | 1984-07-20 | Nec Kyushu Ltd | Manufacture of semiconductor device |
| JPS60163446A (en) * | 1984-02-02 | 1985-08-26 | Pioneer Electronic Corp | Formation of through hole |
| JPS6222437A (en) * | 1985-07-22 | 1987-01-30 | Oki Electric Ind Co Ltd | Forming method of contact hole |
| JPS6245069A (en) * | 1985-08-22 | 1987-02-27 | Toshiba Corp | Manufacture of semiconductor device |
-
1987
- 1987-03-25 JP JP62070769A patent/JPS63236317A/en not_active Withdrawn
-
1988
- 1988-03-25 KR KR1019880003237A patent/KR920001032B1/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52104087A (en) * | 1976-02-27 | 1977-09-01 | Hitachi Ltd | Preparation of inter-layer insulation film utilized in multi-layer wir ing of electronic parts |
| JPS58166766A (en) * | 1982-03-27 | 1983-10-01 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS59125620A (en) * | 1983-01-05 | 1984-07-20 | Nec Kyushu Ltd | Manufacture of semiconductor device |
| JPS60163446A (en) * | 1984-02-02 | 1985-08-26 | Pioneer Electronic Corp | Formation of through hole |
| JPS6222437A (en) * | 1985-07-22 | 1987-01-30 | Oki Electric Ind Co Ltd | Forming method of contact hole |
| JPS6245069A (en) * | 1985-08-22 | 1987-02-27 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63253647A (en) * | 1987-04-10 | 1988-10-20 | Nec Corp | Semiconductor device |
| JPH04356944A (en) * | 1991-04-03 | 1992-12-10 | Matsushita Electron Corp | Semiconductor device and its manufacture |
| JPH06169021A (en) * | 1992-11-30 | 1994-06-14 | Nec Corp | Semiconductor device and manufacture thereof |
| KR100417645B1 (en) * | 1996-12-28 | 2004-04-13 | 주식회사 하이닉스반도체 | Method for forming interlayer dielectric of semiconductor device |
| JP2009004573A (en) * | 2007-06-21 | 2009-01-08 | Denso Corp | Silicon carbide semiconductor device and manufacturing method thereof |
| JP4539684B2 (en) * | 2007-06-21 | 2010-09-08 | 株式会社デンソー | Silicon carbide semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| KR880011888A (en) | 1988-10-31 |
| KR920001032B1 (en) | 1992-02-01 |
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Legal Events
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|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |