JPH04186729A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04186729A JPH04186729A JP31392590A JP31392590A JPH04186729A JP H04186729 A JPH04186729 A JP H04186729A JP 31392590 A JP31392590 A JP 31392590A JP 31392590 A JP31392590 A JP 31392590A JP H04186729 A JPH04186729 A JP H04186729A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- alloy
- tiw
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 18
- 239000000956 alloy Substances 0.000 claims abstract description 18
- 238000002844 melting Methods 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 238000004544 sputter deposition Methods 0.000 claims abstract description 11
- 230000008018 melting Effects 0.000 claims abstract description 9
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 3
- 229910017758 Cu-Si Inorganic materials 0.000 abstract description 14
- 229910017931 Cu—Si Inorganic materials 0.000 abstract description 14
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 229910000676 Si alloy Inorganic materials 0.000 abstract description 7
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 5
- 230000005012 migration Effects 0.000 abstract description 3
- 238000013508 migration Methods 0.000 abstract description 3
- 229910000881 Cu alloy Inorganic materials 0.000 abstract 1
- 150000001875 compounds Chemical class 0.000 description 9
- 238000000137 annealing Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000003353 gold alloy Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010406 interfacial reaction Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の配線材料、特に、高集積半導体装
置の高信頼性配線材料を用いた半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to wiring materials for semiconductor devices, and particularly to semiconductor devices using highly reliable wiring materials for highly integrated semiconductor devices.
半導体装置の集積度が増加することによって、Ａｆｌ配
線構造も複雑、多層化になり、エレクトロマイグレーシ
ョンやストレスマイグレーションに起因する配線の断線
が問題となっている。As the degree of integration of semiconductor devices increases, the Afl wiring structure becomes more complex and multilayered, and wire breakage due to electromigration or stress migration becomes a problem.
この問題を解決するため、特開昭６３−２９５４８号公
報に記載のように、Ａｌ−Ｃｕ−５ｉ合金と高融点金属
であるＴｉＷを積層した配線が考案されている。しかし
、この方法ではストレスマイグレーションによる断線は
防止できるが、エレクトロマイグレーションによる配線
の抵抗増加を防止することはできない。In order to solve this problem, a wiring layered with Al-Cu-5i alloy and TiW, which is a high melting point metal, has been devised as described in Japanese Patent Application Laid-open No. 63-29548. However, although this method can prevent wire breakage due to stress migration, it cannot prevent an increase in wiring resistance due to electromigration.
配線の抵抗増加は、Ａｌ配線と高融点金属との界面で両
者が反応するためである。従来の配線は。The increase in resistance of the wiring is due to the reaction between the Al wiring and the high melting point metal at the interface. Conventional wiring.
熱酸化によって形成した絶縁膜上にＴｉＷ膜をスパッタ
法で形成後、その上に、Ａｆｆ−Ｃｕ−’Ｓｉ合金膜を
スパッタにより堆積し、形成される。その後、４５０
’Ｃ近傍の温度でアニールする。このアニール時に、Ａ
１２合金膜とＴ ｉ Ｗ゛との界面で反応が起こり、高
抵抗のＡ、Ｑの化合物が形成される。A TiW film is formed by sputtering on an insulating film formed by thermal oxidation, and then an Aff-Cu-'Si alloy film is deposited thereon by sputtering. After that, 450
Anneal at a temperature near 'C. During this annealing, A
A reaction occurs at the interface between the 12 alloy film and T i W', and a high-resistance compound of A and Q is formed.
この配線に高い電流密度を与えると、Ａ Ｑ −Ｃｕ−
Ｓｉ合金膜がエレクトロマイグレーションにより断線す
るとＡ Ｑ、の化合物が露畠する。そのため、配線の抵
抗が増加するという問題がある。When a high current density is applied to this wiring, A Q -Cu-
When the Si alloy film is disconnected due to electromigration, compounds A and Q are exposed. Therefore, there is a problem that the resistance of the wiring increases.
従来例の積層配線構造は、Ａｌ金合金高融点金属との界
面反応については考慮がなされておらず、配線の抵抗増
加は必ずしも改善されないという問題がある。The conventional laminated wiring structure does not take into consideration the interfacial reaction with the Al-gold alloy high-melting point metal, and there is a problem in that the increase in resistance of the wiring cannot necessarily be improved.
本発明の目的は、Ａｌ金合金高融点金属との反応を防止
し、配線の抵抗増加を抑制した、高信頼のＡｌ配線を有
する半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device having highly reliable Al interconnects that prevents reactions with Al-gold alloy high-melting point metals and suppresses increases in interconnect resistance.
この発明はＴ ｉ Ｗ膜上の膜質の異なる二層のＡ Ｑ
−Ｃｕ −Ｓ ｉ合金膜を形成することにある。This invention consists of two layers of AQ with different film quality on a TiW film.
-Cu-Si alloy film is formed.
すなわち、ＴｉＷ膜上の第一層目に膜質の低いＡ Ｑ
−Ｃｕ −Ｓ ｉ合金膜をスパッタにより形成後、その
上に通常の膜質のＡｌ−Ｃｕ−Ｓｉ合金膜をスパッタに
よって形成して成るものである。ＴｉＷ膜と接している
Ａｌ２−Ｃｕ−Ｓｉ合金膜は、Ｔ 、ｉ’Ｊとの反応を
抑制するため、配線の抵抗増加の少ない、高信頼性のＡ
Ｑ配線を実現する技術である。In other words, the first layer on the TiW film is AQ with poor film quality.
-Cu-Si alloy film is formed by sputtering, and then an Al-Cu-Si alloy film of normal film quality is formed thereon by sputtering. The Al2-Cu-Si alloy film in contact with the TiW film suppresses the reaction with T and i'J, resulting in a highly reliable A with little increase in wiring resistance.
This is a technology that realizes Q wiring.
Ａｌ−Ｃｕ−Ｓｉ合金／ Ｔ ｉ Ｗ界面に形成する化
合物は、ＡｌとＷとの化合物であることを確認した。Ｔ
ｉＷ膜中のＷは、アニール時に界面に集中し、徐々にＡ
ｌＱ金膜中に拡散し、Ａｌと化合物を形成する。従って
、ＡｌＱ金膜中へのＷ′の拡散を抑制できれば化合物生
成を防止できることに着目した。It was confirmed that the compound formed at the Al-Cu-Si alloy/T i W interface was a compound of Al and W. T
W in the iW film concentrates at the interface during annealing, and gradually A
It diffuses into the IQ gold film and forms a compound with Al. Therefore, we focused on the fact that the formation of compounds could be prevented if the diffusion of W' into the AlQ gold film could be suppressed.
そこで、本発明はＴｉＷ膜上に膜質の低いＡｌ−Ｃｕ−
Ｓｉ合金膜を設けることによって、Ａｌ合合金へのＷの
拡散を抑制できることを見出した。Therefore, in the present invention, a film of low quality Al-Cu-
It has been found that by providing a Si alloy film, it is possible to suppress the diffusion of W into the Al alloy.
膜質の低い膜は、不純物、特にＮ２及びＡｒが通常の膜
質の場合より多く、このＮ２ がＷの拡散を抑制する効
果を持つことがわかった。It was found that a film of low quality contains more impurities, especially N2 and Ar, than a film of normal quality, and that this N2 has the effect of suppressing the diffusion of W.
第２図は、Ａ Ｑ −Ｃｕ −Ｓ ｉ ／ Ｔ ｉ Ｗ
積層膜におけるアニール後のＡｌ−Ｗ化合物生成量に及
ぼすＡｆｌ−Ｃｕ−Ｓｉ合金膜中のＮ２ ガス含有量の
影響を示したものである。Ｎ２がＩ Ｘ １０’−３ｍ
ｏｌ／ｇ以上になるとＡｌ−Ｗ化合物の生成が抑制され
るのがわかる。Figure 2 shows A Q -Cu -S i /T i W
This figure shows the influence of the N2 gas content in the Afl-Cu-Si alloy film on the amount of Al-W compound produced after annealing in the laminated film. N2 is I x 10'-3m
It can be seen that the production of Al-W compounds is suppressed when the concentration exceeds ol/g.
従って、ＴｉＷ膜に接しているＡｌ−Ｃｕ−Ｓｉ合金膜
は、Ｎ２ガスがＩ Ｘ １０−’ｉｏＱ／ ｇ以上含有
していればよい。しかし、上層のＡｌ−Ｃｕ−Ｓｉ合金
膜は、できるかぎりＮ２等の不純物は少ない方がよい。Therefore, the Al-Cu-Si alloy film in contact with the TiW film only needs to contain N2 gas of I x 10-'ioQ/g or more. However, it is preferable that the upper layer Al--Cu--Si alloy film contains as few impurities as possible, such as N2.
これは、不純物が多いとエレクトロマイグレーションに
よって断線し易くなるためである。This is because if there are a lot of impurities, it becomes easy to break the wire due to electromigration.
以下、本発明における積層配線を形成する場合の一実施
例を第１図の工程順断面図により詳述する。Hereinafter, one embodiment of forming a laminated wiring according to the present invention will be described in detail with reference to step-by-step sectional views shown in FIG.
まず、第１図（ａ）に示すように、シリコン基板１上に
形成した拡散層２と第一の配線との分離を行うために膜
厚約８０００人の絶縁膜３をウェハ全面にＣＶＤ法によ
り形成する。次に拡散ＷＩ２と第一の配線と接続するた
めの孔、つまり、コンタクトホール４を形成する。その
後、第１図（ｂ）に示すように、まず、ＴｉＷ膜５をス
パッタ法により形成する。次に、到達圧力が８ Ｘ Ｉ
Ｏ−７Ｔｏｒｒ以上のスパッタ条件で第−層のＡｌ−
Ｃｕ−Ｓｉ合金膜６をＴｉＷ膜上に形成し、さらにその
上に到達圧力が８ Ｘ １０−７Ｔｏｒｒ以上のスパッ
タ条件で第二層目のＡｌＣｕ−Ｓｉ合金膜７を形成する
。First, as shown in FIG. 1(a), in order to separate the first wiring from the diffusion layer 2 formed on the silicon substrate 1, an insulating film 3 with a thickness of approximately 8,000 yen is coated over the entire surface of the wafer using the CVD method. Formed by Next, a hole for connecting the diffusion WI2 and the first wiring, that is, a contact hole 4 is formed. Thereafter, as shown in FIG. 1(b), a TiW film 5 is first formed by sputtering. Next, the ultimate pressure is 8 X I
The Al-th layer is sputtered under sputtering conditions of O-7 Torr or more.
A Cu--Si alloy film 6 is formed on the TiW film, and a second layer of AlCu--Si alloy film 7 is further formed thereon under sputtering conditions such that the ultimate pressure is 8.times.10@-7 Torr or higher.
ＴｉＷ膜の厚さは２０００人、Ａｌ−Ｃｕ−Ｓｉ合金膜
の厚さは第−及び第二層を合わせて８０００人である。The thickness of the TiW film is 2000 mm, and the thickness of the Al-Cu-Si alloy film is 8000 mm including the first and second layers.
次に、配線として必要な領域のみ残し、他の領域を選択
的にエツチング除去する。その後、拡散層２と配線と良
好なコンタクトを形成するために、アニールを行なう。Next, only the areas necessary for wiring are left, and other areas are selectively etched away. Thereafter, annealing is performed to form good contact between the diffusion layer 2 and the wiring.
アニール温度は４５０ ’Ｃ程度である。次に、第一の
配線と第二の配線を電気的に分離するための絶縁膜８を
ＣＶＤ法により形成する。その後、第一の配線と第二の
配線とを接続するためのコンタクトホール９を絶縁膜８
の所定の位置に形成する。次に第１図（Ｃ）に示すよう
に、第２の配線１ｏを第一の配線の形成方法と同じ方法
で形成する。その後、第一の配線の場合と同様に配線と
して必要な領域のみ残し、他の領域は選択的にエツチン
グ除去する。最後に、配線を保護するために、保護膜１
１をＣＶＤ法にて形成する。ここで１．１１配線はＡ
１１− Ｃｕ −Ｓ ｉの他に、Ａｆｆ−Ｃｕでも、ま
た、Ｃｕの替りに他の元素でも良い。高融点金属として
Ｗでも良い。さらに、本発明の配線は、第−及び第二配
線のいずれか一方でもよい。The annealing temperature is about 450'C. Next, an insulating film 8 for electrically separating the first wiring and the second wiring is formed by CVD. After that, a contact hole 9 for connecting the first wiring and the second wiring is formed in the insulating film 8.
at a predetermined location. Next, as shown in FIG. 1C, a second wiring 1o is formed by the same method as the first wiring. Thereafter, as in the case of the first wiring, only the area necessary for the wiring is left, and other areas are selectively etched away. Finally, to protect the wiring, a protective film 1 is added.
1 is formed by CVD method. Here 1.11 wiring is A
In addition to 11-Cu-Si, Aff-Cu may be used, or other elements may be used instead of Cu. W may be used as the high melting point metal. Furthermore, the wiring of the present invention may be either the first wiring or the second wiring.
本発明は、シリコンを基板とする半導体装置すべての配
線材料として応用できることは明らかである。It is clear that the present invention can be applied as a wiring material for all semiconductor devices using silicon as a substrate.
第３図は、本発明の詳細な説明するためのグラフである
。従来のＡ Ｑ −Ｃｕ −Ｓ ｉ ／ Ｔ ｉ Ｗ積
層配線と本発明の２層Ａ Ｑ −Ｃｕ −Ｓ ｉ ／
Ｔ ｉ Ｗ積層配線に高電流を流した時の配線の抵抗増
加を測定した結果である。本発明の配線の方が、従来の
配線より抵抗の増加が少ないことがわかる。FIG. 3 is a graph for explaining the present invention in detail. Conventional AQ-Cu-S i/T i W laminated wiring and the two-layer A Q-Cu-S i/T iW of the present invention
These are the results of measuring the increase in resistance of the wiring when a high current is passed through the TiW laminated wiring. It can be seen that the wiring of the present invention has a smaller increase in resistance than the conventional wiring.
本発明によれば、ＴｉＷとの反応を抑制できるＡｌ配線
にしたため、配線の抵抗増加が少ない。According to the present invention, since the Al wiring is used which can suppress the reaction with TiW, the increase in resistance of the wiring is small.
第１図（ａ）〜（ｄ）は、本発明の一実施例における半
導体装置の製造工程を説明するための工程順の断面図、
第２図は、Ａｎ−Ｃｕ−３ｉ／ＴｉＷ積層膜をアニール
した時のＡｌ−Ｗ化合物生成量とＡｌ−Ｃｕ−５ｉ合金
膜中のＮ２ガス含有量との関係を示した説明図、第３図
は、本発明の効果を従来技術と比較して示した説明図で
ある。
１・・・シリコン基板、２・・拡散層、３・・・絶縁膜
、４・・・コンタクトホール、５・・ＴｉＷ膜、６・Ａ
ｌ−Ｃｕ−８ｉ合金膜、７＝＃ｋＱ−Ｃｕ−５ｉ合金膜
、８・・・絶縁膜、９・・・コンタクトホール、１０・
・・Ａｌ−Ｃｕ −Ｓ ｉ合金膜、１１・・・保護膜。
′・代理人 弁理士 小川勝馬＼ごッ
第１図
第２図FIGS. 1(a) to 1(d) are cross-sectional views in the order of steps for explaining the manufacturing process of a semiconductor device in an embodiment of the present invention;
Figure 2 is an explanatory diagram showing the relationship between the amount of Al-W compound produced when an An-Cu-3i/TiW laminated film is annealed and the N2 gas content in the Al-Cu-5i alloy film. The figure is an explanatory diagram showing the effects of the present invention in comparison with the prior art. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Diffusion layer, 3... Insulating film, 4... Contact hole, 5... TiW film, 6... A
l-Cu-8i alloy film, 7=#kQ-Cu-5i alloy film, 8... Insulating film, 9... Contact hole, 10.
...Al-Cu-Si alloy film, 11...protective film. '・Agent: Patent Attorney Katsuma Ogawa ＼ Figure 1 Figure 2
Claims (1)
属との積層配線をもつ半導体装置において、 前記高融点金属の膜上にそれぞれ異なる方法で形成され
た二層のＡｌ合金膜よりなることを特徴とする半導体装
置。 ２、請求項１において、前記高融点金属の膜に接してい
る下層のＡｌ合金膜は、Ｎ＿２ガスが１×１０＾−＾３
ｍｏｌ／ｇ以上含有する半導体装置。 ３、請求項１において、上層のＡｌ合金膜は、Ｎ＿２ガ
スが１×１０＾−＾３ｍｏｌ／ｇ以下である半導体装置
。 ４、請求項１において、前記高融点金属の膜はＴｉＷ及
びＷである半導体装置。 ５、請求項１において、前記高融点金属の膜に接してい
るＡｌ合金膜は、８×１０＾−＾７Ｔｏｒｒ以上の到達
圧力のスパッタ条件で形成している半導体装置。[Claims] 1. In a semiconductor device having laminated wiring of an Al alloy and a high melting point metal on a semiconductor or insulating substrate, two layers of Al formed by different methods on the film of the high melting point metal are provided. A semiconductor device comprising an alloy film. 2. In claim 1, the lower Al alloy film in contact with the high melting point metal film contains N_2 gas of 1×10^-^3
A semiconductor device containing mol/g or more. 3. The semiconductor device according to claim 1, wherein the upper Al alloy film contains N_2 gas at 1×10^-^3 mol/g or less. 4. The semiconductor device according to claim 1, wherein the high melting point metal film is TiW and W. 5. The semiconductor device according to claim 1, wherein the Al alloy film in contact with the high melting point metal film is formed under sputtering conditions at an ultimate pressure of 8×10^-^7 Torr or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31392590A JPH04186729A (en) | 1990-11-21 | 1990-11-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31392590A JPH04186729A (en) | 1990-11-21 | 1990-11-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04186729A true JPH04186729A (en) | 1992-07-03 |
Family
ID=18047176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31392590A Pending JPH04186729A (en) | 1990-11-21 | 1990-11-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04186729A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08181139A (en) * | 1994-12-26 | 1996-07-12 | Nec Corp | Semiconductor device and manufacture thereof |
-
1990
- 1990-11-21 JP JP31392590A patent/JPH04186729A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08181139A (en) * | 1994-12-26 | 1996-07-12 | Nec Corp | Semiconductor device and manufacture thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0751567B1 (en) | Copper alloys for chip interconnections and method of making | |
| EP0843895B1 (en) | Method of manufacturing a metal interconnect structure for an integrated circuit with improved electromigration reliability | |
| US6706629B1 (en) | Barrier-free copper interconnect | |
| JP3244058B2 (en) | Method for manufacturing semiconductor device | |
| JP2001203205A (en) | Semiconductor device and its manufacturing method | |
| US20070145600A1 (en) | Semiconductor device and manufacturing method thereof | |
| JPH09186103A (en) | Structure of metal interconnection and forming method thereof | |
| JP2600593B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS6364057B2 (en) | ||
| US7888263B2 (en) | Cladded silver and silver alloy metallization for improved adhesion electromigration resistance | |
| JPH06236878A (en) | Metal wiring | |
| JPH04186729A (en) | Semiconductor device | |
| JPH06204218A (en) | Manufacturing method of semiconductor device | |
| US20050136645A1 (en) | Semiconductor device and fabrication method thereof | |
| JPH0629294A (en) | Manufacture of semiconductor device | |
| JPH11186263A (en) | Semiconductor device and manufacture thereof | |
| JPH05102148A (en) | Semiconductor device | |
| JPH11283981A (en) | Semiconductor device and manufacture thereof | |
| JP3014887B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH05102154A (en) | Semiconductor device | |
| JP2723023B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH06275725A (en) | Manufacture of semiconductor device | |
| JPH06326105A (en) | Laminated interconnection structure of semiconductor device | |
| JPH0555296A (en) | Semiconductor device | |
| JPH02206122A (en) | Semiconductor device |