KR100316030B1 - Method for forming Al wire of semiconductor device - Google Patents
Method for forming Al wire of semiconductor device Download PDFInfo
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- KR100316030B1 KR100316030B1 KR1019970078028A KR19970078028A KR100316030B1 KR 100316030 B1 KR100316030 B1 KR 100316030B1 KR 1019970078028 A KR1019970078028 A KR 1019970078028A KR 19970078028 A KR19970078028 A KR 19970078028A KR 100316030 B1 KR100316030 B1 KR 100316030B1
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- titanium
- aluminum
- aluminum alloy
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000010936 titanium Substances 0.000 claims abstract description 58
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 43
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 40
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 39
- 239000010703 silicon Substances 0.000 claims abstract description 39
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229910017150 AlTi Inorganic materials 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 20
- 239000002184 metal Substances 0.000 abstract description 20
- 230000004888 barrier function Effects 0.000 abstract description 9
- 229910018594 Si-Cu Inorganic materials 0.000 abstract description 3
- 229910008465 Si—Cu Inorganic materials 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 3
- 239000006117 anti-reflective coating Substances 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 96
- 239000013078 crystal Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 230000005012 migration Effects 0.000 description 4
- 238000013508 migration Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- -1 aluminum ions Chemical class 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000001878 scanning electron micrograph Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 일반적으로 반도체 장치의 금속 배선 형성 방법에 관한 것으로 특히, 알루미늄막 내에 첨가된 실리콘으로 인한 식각잔여물의 생성을 억제할 수 있는 반도체 장치의 알루미늄 배선 형성 방법에 관한 것이다.BACKGROUND OF THE
금속화(metalization)는 반도체 장치에서 각 소자들을 작은 저항으로 연결시키는 것으로 칩(chip)과 패키지(package) 내부 회로를 연결하기 위한 접촉부를 만드는 공정이다. 금속화로 사용되어야 할 금속의 요건으로는 실리콘산화막(SiO2), 실리콘(Si) 등의 박막에 대하여 접착이 우수해야 하며 온도 및 스트레스(stress)에 대한 저항이 있어야 한다. 전기적으로는 옴콘택(Ohmic Contact) 저항이 작아야 하며, 실리콘과도 반응하여 내부 회로 소자들과 옴콘택 특성이 좋아야 하고 전도성이 높아야 한다. 이러한 조건을 만족하는 금속을 이용하여 금속화를 실시하였을 경우 부식 및 산화 그리고 전자이동 (electron migration), 스트레스 마이그레이션(stress migration)으로 인한 금속선의 단락에 대한 강한 내성을 가져야 한다.Metallization is the process of connecting each device with a small resistance in a semiconductor device to make contacts for connecting the chip and internal circuitry in the package. As metal requirements to be used for metallization, adhesion to thin films such as silicon oxide (SiO 2 ) and silicon (Si) should be excellent and should be resistant to temperature and stress. Electrically, ohmic contact resistance should be small, and it should also react with silicon to have good internal circuit elements and ohmic contact characteristics and high conductivity. When metallization is carried out using metals satisfying these conditions, it must have strong resistance to short circuit of metal wires due to corrosion, oxidation, electron migration and stress migration.
알루미늄은 실리콘(Si``), 실리콘산화막(SiO_2``) 등에 대한 접착력이 우수하고, 과도핑(Heavily Doping)된 n^+``, p^+`` 실리콘과 옴콘택 특성이 좋으며, 비저항 값이 2.7μΩ·㎝ 정도로 낮고, 값이 다른 귀금속에 비해 싸다는 특성으로 인해 반도체 재료의 금속 배선 재료로서 가장 널리 사용되는 재료이다.Aluminum has excellent adhesion to silicon (Si``) and silicon oxide film (SiO_2``), and has good ohmic contact properties with heavily doped n ^ + ``, p ^ + `` silicon and resistivity. It is a material that is most widely used as a metal wiring material of a semiconductor material because of its low value of about 2.7 µΩ · cm and its low value compared to other precious metals.
그러나, 디램(DRAM)을 비롯한 범용의 반도체 소자가 고집적화되어 감에 따라 금속 배선의 선폭이 가늘어져 전자가 알루미늄 배선을 통해 이동할 때 전자와 알루미늄 이온이 충돌하여 금속 배선의 단선이 일어나기 쉽다. 일반적으로 스퍼터링(sputtering) 방법으로 증착되는 알루미늄막은 힐락(hillock)이나 디스로케이션(dislocation) 같은 결함을 갖고 있어서 전자이동 등으로 인하여 전기적 특성을 저하시키고 있다.However, as general-purpose semiconductor devices such as DRAMs are highly integrated, the line width of the metal wiring becomes thinner, and electrons and aluminum ions collide with each other when electrons move through the aluminum wiring, thereby easily causing disconnection of the metal wiring. In general, an aluminum film deposited by a sputtering method has defects such as hillock or dislocation, thereby deteriorating electrical characteristics due to electron migration.
또한, 통상적으로 알루미늄-합금 증착 후, 400 내지 450 ℃의 온도 범위에서 실시하는 열처리(annealing) 과정 동안에 실리콘 기판과 알루미늄막의 접합면에서 실리콘이 알루미늄막으로 비균일적으로 확산(diffusion)된다. 결과적으로 실리콘이 소모되어 접합 면적이 작아지고, 비균일적으로 확산된 실리콘의 빈자리를 채우기 위하여 실리콘 기판으로 침투된 알루미늄막이 스파이크(spike) 모양을 형성한다. 상기와 같은 과정에서 형성된 스파이크 부분에 고전계가 걸려 접합이 깨지는 현상이 발생하는데 이는 누설 전류의 증가를 가져와 특성 저하를 유발한다.In addition, silicon is non-uniformly diffused into the aluminum film at the bonding surface of the silicon substrate and the aluminum film during an annealing process which is typically performed at a temperature range of 400 to 450 ° C. after aluminum-alloy deposition. As a result, silicon is consumed and the junction area is reduced, and the aluminum film penetrated into the silicon substrate forms a spike shape to fill in the voids of the non-uniformly diffused silicon. A phenomenon in which the junction is broken due to a high electric field is applied to the spike portion formed in the above process, which leads to an increase in leakage current, leading to deterioration of characteristics.
상기와 같은 문제점을 해결하기 위해 종래에는 알루미늄에 실리콘을 첨가하여 실리콘이 과포화된 알루미늄막을 증착하는 방법, 실리콘 기판 위에 알루미늄 전극을 부착시키는 방법 및 알루미늄과 실리콘 기판 사이에 장벽으로 되는 금속을 삽입 방법 등이 종래에 사용되고 있다. 이 장벽 역할을 하는 금속은 실리콘과 낮은 접촉 저항을 형성하며, 알루미늄과 반응하지 않아야 하는데, TiN과 같은 금속은 550 ℃, 30분의 열처리에는 안정하다는 것이 알려져 있다.In order to solve the above problems, a method of depositing an aluminum film supersaturated with silicon by adding silicon to aluminum, a method of attaching an aluminum electrode on a silicon substrate, and a method of inserting a metal as a barrier between the aluminum and silicon substrates, etc. This is conventionally used. Metals acting as a barrier form a low contact resistance with silicon and should not react with aluminum. Metals such as TiN are known to be stable to heat treatment at 550 ° C. for 30 minutes.
첨부된 도1과 도2a 및 도2b를 참조하여, 접합 스파이킹(junction spiking) 및 전자이동(electron migration)을 방지하기 위해 알루미늄에 1 %의 Si 및 0.5 %의 구리를 용해시킨 Al-Si-Cu 합금을 이용하는 경우의 문제점을 살펴본다.Referring to FIGS. 1, 2A, and 2B, Al-Si- in which 1% of Si and 0.5% of copper is dissolved in aluminum to prevent junction spiking and electron migration. The problem when using Cu alloy is examined.
도1에 도시한 바와 같이 실리콘 기판(10) 상부에 Ti 또는 Ti/TiN으로 장벽금속막(11)을 증착한다. 상기 장벽금속막(11) 중에서 Ti는 실리콘 기판에 형성된 접합(도시하지 않음)과 반응하여 TiSi2를 형성함으로써 콘택 저항을 낮추는 역할을 한다. 이어서, 실리콘 기판의 실리콘이 알루미늄막으로 확산되는 것을 방지하기 위하여 Al-Si-Cu로 이루어지는 알루미늄막(12)을 형성하고 TiN막으로 반사방지막(13)을 형성한 후, 식각방지막으로 감광막 패턴(15)을 형성한다.As shown in FIG. 1, the
다음으로, 소정의 전도막 패턴을 형성하기 위한 식각 공정을 실시하여 반사방지막(13) 및 알루미늄막(12)을 선택적으로 제거한다.Next, an
전술한 바와 같이 이루어지는 종래 기술은 알루미늄막 내에 과포화된 실리콘이 국부적으로 석출되어 실리콘 결정이 존재하게 되는데, 이것이 금속막 식각시 방해 물질로 작용한다.According to the prior art made as described above, the supersaturated silicon is locally precipitated in the aluminum film so that the silicon crystal is present, which acts as an interference material when the metal film is etched.
도2a 및 도2b는 각각 상기와 같이 이루어지는 종래 기술에 따른 알루미늄막 식각 결과를 보이는 평면 및 단면의 SEM 사진으로, 알루미늄 합금막(21) 패턴을 형성하기 위한 식각 과정에서 실리콘 결정으로 인하여 소정 부위의 알루미늄막이 완전하게 제거되지 않고 혹(nodule)(22)이 만들어져 브릿지(bridge)를 유발하게 된다.2A and 2B are SEM images of a plane and a cross-sectional view showing an aluminum film etching result according to the prior art, respectively, as described above. FIG. 2A and FIG. 2B show a predetermined area due to silicon crystals during the etching process for forming the
상기와 같은 문제점을 해결하기 위한 본 발명은 실리콘이 용해된 알루미늄 합금막 형성 방법에 있어서, 알루미늄 합금막에 석출된 실리콘 결정에 의한 식각잔여물의 생성을 방지할 수 있는 반도체 장치의 알루미늄 배선 형성 방법을 제공하는데 그 목적이 있다.The present invention for solving the above problems is an aluminum alloy film forming method in which silicon is dissolved, an aluminum wiring forming method of a semiconductor device capable of preventing the formation of etching residues by silicon crystals deposited on the aluminum alloy film. The purpose is to provide.
도1은 종래 기술에 따른 반도체 장치의 알루미늄 배선 형성 공정 단면도.1 is a cross-sectional view of an aluminum wiring formation process of a semiconductor device according to the prior art.
도2a 및 도2b는 종래 기술에 따른 반도체 장치의 알루미늄 금속 배선 형성 결과를 나타내는 SEM 사진.2A and 2B are SEM photographs showing the results of aluminum metal wiring formation of a semiconductor device according to the prior art;
도3은 본 발명의 일실시예에 따른 반도체 장치의 알루미늄 배선 형성 공정 단면도.Figure 3 is a cross-sectional view of the aluminum wiring formation process of the semiconductor device according to one embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
30: 반도체 기판 31: 장벽금속막30: semiconductor substrate 31: barrier metal film
32: 알루미늄 합금막 33: Ti막32: aluminum alloy film 33: Ti film
34: 반사방지막 35: 감광막 패턴34: antireflection film 35: photoresist pattern
31', 33': AlTi3막31 ', 33': AlTi 3 membrane
상기와 같은 목적을 달성하기 위한 본 발명은, 반도체 기판 상에 제1 티타늄(Ti)막을 형성하는 제1 단계; 상기 제1 티타늄막 상에 실리콘(Si)이 첨가된 알루미늄 합금막을 형성하는 제2 단계; 상기 알루미늄 합금막 상에 제2 티타늄막을 형성하는 제3 단계; 상기 제3 단계가 완료된 반도체 기판에 열을 가하여, 상기 제1 티타늄막과 상기 알루미늄 합금막의 계면에 제1 AlTi3막을 형성하고, 상기 알루미늄 합금막과 상기 제2 티타늄막의 계면에 제2 AlTi3막을 형성하는 제4 단계; 및 상기 제2 티타늄막, 상기 제2 AlTi3막, 상기 알루미늄 합금막, 상기 제1 AlTi3막 및 상기 제1 티타늄막을 선택적으로 식각하여 패턴을 형성하는 제5 단계를 포함하는 반도체 장치의 알루미늄 배선 형성 방법을 제공한다.The present invention for achieving the above object, a first step of forming a first titanium (Ti) film on a semiconductor substrate; A second step of forming an aluminum alloy film to which silicon (Si) is added on the first titanium film; A third step of forming a second titanium film on the aluminum alloy film; Heat is applied to the semiconductor substrate where the third step is completed to form a first AlTi 3 film at the interface between the first titanium film and the aluminum alloy film, and a second AlTi 3 film at the interface between the aluminum alloy film and the second titanium film. Forming a fourth step; And a fifth step of forming a pattern by selectively etching the second titanium film, the second AlTi 3 film, the aluminum alloy film, the first AlTi 3 film, and the first titanium film. It provides a formation method.
또한 상기 목적을 달성하기 위한 본 발명은, 반도체 기판 상에 제1 티타늄(Ti)막을 형성하는 제1 단계; 상기 제1 티타늄막 상에 실리콘(Si)이 첨가된 알루미늄 합금막을 형성하는 제2 단계; 상기 알루미늄 합금막 상에 제2 티타늄막을 형성하고, 상기 제2 티타늄막 상에 반사방지막을 형성하는 제3 단계; 상기 제3 단계가 완료된 반도체 기판에 열을 가하여, 상기 제1 티타늄막과 상기 알루미늄 합금막의 계면에 제1 AlTi3막을 형성하고, 상기 알루미늄 합금막과 상기 제2 티타늄막의계면에 제2 AlTi3막을 형성하는 제4 단계; 및 상기 반사방지막, 상기 제2 티타늄막, 상기 제2 AlTi3막, 상기 알루미늄 합금막, 상기 제1 AlTi3막 및 상기 제1 티타늄막을 선택적으로 식각하여 패턴을 형성하는 제5 단계를 포함하는 반도체 장치의 알루미늄 배선 형성 방법을 제공한다.In addition, the present invention for achieving the above object, a first step of forming a first titanium (Ti) film on a semiconductor substrate; A second step of forming an aluminum alloy film to which silicon (Si) is added on the first titanium film; Forming a second titanium film on the aluminum alloy film, and forming an anti-reflection film on the second titanium film; Heat is applied to the semiconductor substrate where the third step is completed to form a first AlTi 3 film at an interface between the first titanium film and the aluminum alloy film, and to form a second AlTi 3 film on the interface between the aluminum alloy film and the second titanium film. Forming a fourth step; And a fifth step of forming a pattern by selectively etching the anti-reflection film, the second titanium film, the second AlTi 3 film, the aluminum alloy film, the first AlTi 3 film, and the first titanium film. A method of forming aluminum wiring in a device is provided.
알루미늄막의 실리콘 용해도는 1% 미만인데 비하여 AlTi3막의 실리콘 용해도는 약 15% 정도이다. AlTi3막은 약간의 열공정으로 알루미늄과 실리콘의 경계면에서 형성된다. 본 발명은 알루미늄막 아래층에 장벽금속막으로 Ti막을 형성하고 알루미늄막 위층의 반사방지막으로 Ti/TiN을 형성하여 Ti/Al/Ti의 적층 구조를 형성하고 열처리하여 알루미늄과 Ti막 계면에 AlTi3막을 형성하는 것을 특징으로 한다.The silicon solubility of the aluminum film is less than 1%, whereas the silicon solubility of the AlTi 3 film is about 15%. AlTi 3 films are formed at the interface between aluminum and silicon with a slight thermal process. In the present invention, a Ti film is formed as a barrier metal film under the aluminum film, and Ti / TiN is formed as an anti-reflection film over the aluminum film to form a laminated structure of Ti / Al / Ti and heat treated to form an AlTi 3 film at the interface between the aluminum and Ti films. It is characterized by forming.
이하, 첨부된 도면을 참조하여 본 발명의 일실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도3에 도시한 바와 같이 실리콘 기판(30) 상부에 Ti 또는 TiN으로 장벽금속막(31)을 형성하고, 장벽금속막(31) 상에 Al-Si-Cu로 이루어지는 알루미늄막(32)을 차례로 형성한다. 다음으로, 상기 알루미늄막(32) 상에 50 Å 내지 300 Å 두께의 Ti막을 형성(33)한다, 이어서, TiN막으로 반사방지막(34)을 형성한 후, 400 ℃ 내지 500 ℃의 온도 범위에서 열처리(annealing) 공정을 실시하여 상기 알루미늄막과 Ti막의 경계면에 AlTi3막(21', 23')을 형성한다. 이어서, 소정의 전도막 패턴을 형성하기 위하여 식각방지막으로 역할하는 감광막 패턴(35)을 형성하고 식각 공정을 실시한다.As shown in FIG. 3, the barrier metal film 31 is formed on the silicon substrate 30 by Ti or TiN, and the aluminum film 32 made of Al-Si-Cu is sequentially formed on the barrier metal film 31. Form. Next, a Ti film having a thickness of 50 kPa to 300 kPa is formed 33 on the aluminum film 32, and then an antireflection film 34 is formed of a TiN film, and then in a temperature range of 400 ° C to 500 ° C. An annealing process is performed to form AlTi 3 films 21 'and 23' on the interface between the aluminum film and the Ti film. Subsequently, in order to form a predetermined conductive film pattern, a photosensitive film pattern 35 serving as an etching prevention film is formed and an etching process is performed.
상기 열처리 공정은 상기 반사방지막(34)을 형성하기 이전에 실시될 수도 있다. 또한, 상기 반사방지막(34)막을 400 ℃ 이상의 온도에서 형성하여 별도의 열처리 공정을 실시하지 않고 알루미늄막과 Ti막의 경계면에 AlTi3막(21', 23')을 형성하기도 한다.The heat treatment process may be performed before forming the anti-reflection film 34. In addition, the anti-reflection film 34 may be formed at a temperature of 400 ° C. or higher to form AlTi 3 films 21 ′ and 23 ′ at the interface between the aluminum film and the Ti film without performing a separate heat treatment process.
상기와 같이 알루미늄막 아래 및 위층에 형성된 AlTi3막으로 알루미늄막 내에 과포화되어 있는 실리콘이 이동한다. 따라서, 실리콘의 석출로 인한 실리콘 결정 생성을 억제할 수 있어 실리콘 결정으로 인한 식각잔여물의 생성을 방지할 수 있다.As described above, the silicon supersaturated in the aluminum film moves to the AlTi 3 film formed below and above the aluminum film. Therefore, it is possible to suppress the generation of silicon crystals due to the precipitation of silicon, it is possible to prevent the formation of etching residues due to the silicon crystals.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 알루미늄막의 아래 및 위층에 얇은 Ti막을 형성하고 열처리함으로써 알루미늄막 내부의 과포화된 실리콘 원자를 막 외부로 추출시킬 수 있어서, 실리콘 석출로 인한 실리콘 혹(silicon nodule)이 발생하는 현상을 억제할 수 있어서 식각 잔류물의 생성을 방지할 수 있다. 따라서, 금속 브릿지 형성으로 인한 수율 저하를 억제할 수 있으며, 금속 배선간의 간격을 줄일 수있어 소자의 고집적화에 기여할 수 있다.According to the present invention, a thin Ti film is formed below and over the aluminum film and heat-treated to extract supersaturated silicon atoms inside the aluminum film to the outside of the film, thereby generating silicon nodules due to silicon precipitation. The phenomenon can be suppressed to prevent the formation of etching residues. Therefore, a decrease in yield due to the formation of metal bridges can be suppressed, and the spacing between metal wires can be reduced, contributing to high integration of the device.
Claims (7)
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| JPH09115829A (en) * | 1995-10-17 | 1997-05-02 | Nissan Motor Co Ltd | Semiconductor device with aluminium wiring part and method of manufacturing |
| JPH09289212A (en) * | 1996-04-19 | 1997-11-04 | Ricoh Co Ltd | Laminated wiring of semiconductor device and its fabrication method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH09115829A (en) * | 1995-10-17 | 1997-05-02 | Nissan Motor Co Ltd | Semiconductor device with aluminium wiring part and method of manufacturing |
| JPH09289212A (en) * | 1996-04-19 | 1997-11-04 | Ricoh Co Ltd | Laminated wiring of semiconductor device and its fabrication method |
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