KR100470923B1 - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
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- KR100470923B1 KR100470923B1 KR1019970019057A KR19970019057A KR100470923B1 KR 100470923 B1 KR100470923 B1 KR 100470923B1 KR 1019970019057 A KR1019970019057 A KR 1019970019057A KR 19970019057 A KR19970019057 A KR 19970019057A KR 100470923 B1 KR100470923 B1 KR 100470923B1
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 45
- 239000002184 metal Substances 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 230000015572 biosynthetic process Effects 0.000 title claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 26
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 26
- 238000000151 deposition Methods 0.000 claims abstract description 22
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 19
- 238000005498 polishing Methods 0.000 claims abstract description 11
- 239000000126 substance Substances 0.000 claims abstract description 11
- 238000001465 metallisation Methods 0.000 claims abstract description 7
- 238000004544 sputter deposition Methods 0.000 claims abstract description 5
- 239000010949 copper Substances 0.000 claims description 29
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 23
- 229910052802 copper Inorganic materials 0.000 claims description 23
- 230000004888 barrier function Effects 0.000 claims description 19
- 239000011229 interlayer Substances 0.000 claims description 18
- 239000010410 layer Substances 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000008021 deposition Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- -1 aluminum ions Chemical class 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005289 physical deposition Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
반도체 장치 제조방법Semiconductor device manufacturing method
2. 발명이 해결하고자 하는 기술적 과제 2. Technical problem to be solved by the invention
반도체 소자의 집적도가 향상됨에 따라 금속 배선을 형성하기 위한 콘택홀 및 비아홀의 크기가 작아지므로 종래의 스퍼터링 방법을 사용한 홀 매립 방법으로는 좁은 영역에 알루미늄을 효과적으로 증착하지 못하는 단점이 있음. As the degree of integration of semiconductor devices is improved, the size of contact holes and via holes for forming metal wirings is reduced. Therefore, the hole filling method using the conventional sputtering method does not effectively deposit aluminum in a narrow area.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
작은 크기의 콘택홀 또는 비아홀에 전도막을 증착하는데 있어서 화학기상증착법과 화학 기계적 연마법을 사용한 효과적인 홀 매립 방법을 제공하고자 함. To provide an effective hole filling method using chemical vapor deposition and chemical mechanical polishing in depositing a conductive film in a small contact hole or via hole.
4. 발명의 중요한 용도4. Important uses of the invention
반도체 소자의 금속 배선 형성 공정에 이용됨Used for metallization process of semiconductor device
Description
본 발명은 일반적으로 반도체 장치의 금속 배선 형성 방법에 관한 것으로 특히, 알루미늄을 이용한 콘택홀 및 비아홀의 매립 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for filling contact holes and via holes using aluminum.
알루미늄은 실리콘(Si), 실리콘 산화막(SiO2) 등에 대한 접착력이 우수하고, 과도핑(Heavily Doping)된 n+ , p+ 실리콘과 옴 저항 특성을 지니며, 전기 비저항 값이 2.7μΩ·㎝ 정도로 낮고, 값이 다른 귀금속에 비해 싸다는 특성으로 인해 반도체 재료의 금속 배선 재료로서 가장 널리 사용되는 재료이다.Aluminum has excellent adhesion to silicon (Si), silicon oxide film (SiO 2 ), etc., and has a heavily doped n + , p + silicon and ohmic resistance, and has an electrical resistivity of about 2.7 μΩ · ㎝ It is a material that is most widely used as a metal wiring material of a semiconductor material because of its low and cheap value compared to other precious metals.
디램(DRAM)을 비롯한 반도체 소자가 고집적화 되어 감에 따라 금속배선의 선폭이 가늘어져 전자가 알루미늄 배선을 통해 이동할 때 전자와 알루미늄 이온이 충돌하여 금속 배선의 단선이 일어나기 쉽다(electro-migration). 더욱이 콘택홀(Contact Hole)이나 비아홀(Via Hole)의 크기가 감소함에 따라 스퍼터링 방법을 이용한 물리적 증착으로 알루미늄을 증착할 경우 홀을 완전히 채우기가 어려워 소자의 신뢰성을 저하시키는 단점이 있다. 한편, 텅스텐을 사용한 화학기상증착법으로 콘택홀이나 비아홀을 매립하여 콘택 플러그를 형성하는 방법도 있지만 알루미늄 사용의 경우보다 저항이 크고 생산 단가가 증가하는 단점이 있다.As semiconductor devices, such as DRAMs, become highly integrated, the line width of metal wirings becomes thinner, and electrons and aluminum ions collide when electrons move through aluminum wirings, which easily causes disconnection of metal wirings (electro-migration). In addition, as the size of the contact hole or via hole is reduced, when aluminum is deposited by physical deposition using a sputtering method, it is difficult to completely fill the hole, thereby degrading the reliability of the device. On the other hand, there is also a method of forming contact plugs by filling contact holes or via holes by chemical vapor deposition using tungsten, but has a disadvantage in that resistance is larger and production costs are increased than in the case of using aluminum.
본 발명은 상기와 같은 문제점을 해결하기 위하여 제안된 것으로, 텅스텐 플러그의 단점과 알루미늄 배선의 단점을 극복할 수 있는 반도체 장치의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems, and an object thereof is to provide a method for forming a metal wiring of a semiconductor device that can overcome the disadvantages of a tungsten plug and an aluminum wiring.
상기 목적을 달성하기 위한 본 발명의 일 측면에 따르면, 소정의 하부층이 형성된 반도체 기판 상에 층간절연막을 형성하는 단계; 상기 층간절연막을 선택적으로 식각하여 콘택홀을 형성하는 단계; 상기 콘택홀이 형성된 전체 구조 표면을 따라 제1 장벽금속막을 증착하는 단계; 상기 제1 장벽금속막이 형성된 전체 구조 상부에 화학기상증착법으로 알루미늄막을 증착하여 상기 콘택홀을 매립하는 단계; 화학 기계적 연마법으로 상기 알루미늄막을 평탄화시켜 콘택 플러그를 형성하는 단계; 상기 콘택 플러그가 형성된 전체 구조 상부에 제2 장벽금속막을 증착하는 단계; 및 상기 제2 장벽금속막이 형성된 전체구조 상부에 금속배선용 구리막을 증착하는 단계를 포함하는 반도체 장치의 금속 배선 형성 방법이 제공된다.According to an aspect of the present invention for achieving the above object, a step of forming an interlayer insulating film on a semiconductor substrate formed with a predetermined lower layer; Selectively etching the interlayer insulating film to form a contact hole; Depositing a first barrier metal film along the entire surface of the structure where the contact hole is formed; Filling the contact hole by depositing an aluminum film on the entire structure on which the first barrier metal film is formed by chemical vapor deposition; Planarizing the aluminum film by chemical mechanical polishing to form a contact plug; Depositing a second barrier metal film on the entire structure of the contact plug; And depositing a copper film for metal wiring on the entire structure on which the second barrier metal film is formed.
또한, 본 발명의 다른 측면에 따르면, 하부 금속 배선이 형성된 반도체 기판상에 층간절연막을 형성하는 단계; 상기 층간절연막을 선택적으로 식각하여 상기 하부 금속 배선을 노출시키는 비아홀 및 배선용 홈을 형성하는 단계; 화학기상증착법으로 알루미늄막을 상기 비아홀 내에만 선택적으로 증착하여 플러그를 형성하는 단계; 상기 플러그가 형성된 전체 구조 표면을 따라 장벽금속막을 증착하는 단계;상기 장벽금속막이 형성된 전체 구조 상부에 화학기상증착법으로 금속배선용 구리 막을 증착하는 단계; 및 화학 기계적 연마법으로 상기 층간절연막이 노출될 정도로 상기 구리막을 평탄화시키는 단계를 포함하는 반도체 장치의 금속 배선 형성 방법이 제공된다.In addition, according to another aspect of the invention, forming an interlayer insulating film on a semiconductor substrate formed with a lower metal wiring; Selectively etching the interlayer insulating layer to form a via hole and a wiring groove exposing the lower metal wiring; Selectively depositing an aluminum film in the via hole by chemical vapor deposition to form a plug; Depositing a barrier metal film along the entire structure surface of the plug; the deposition of a copper film for metallization by chemical vapor deposition on the entire structure of the barrier metal film; And planarizing the copper film to the extent that the interlayer insulating film is exposed by a chemical mechanical polishing method.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
먼저, 도1A 내지 도1C는 본 발명의 일실시예에 따른 반도체 장치의 금속 배선 형성 공정을 나타낸 단면도이다.First, FIGS. 1A to 1C are cross-sectional views illustrating a metal wiring forming process of a semiconductor device according to an embodiment of the present invention.
본 실시예에 따른 금속 배선 형성 공정은, 우선 도1A에 도시한 바와 같이 반도체 기판(11)에 대해 소정의 하부층 공정을 진행하여 도전층(예컨대, 소오스/드레인 접합)(12)과 층간절연막(13)이 형성된 상태에서, 층간절연막(13)에 대한 사진 및 식각공정을 진행하여 도전층(12)을 노출시키는 콘택홀을 형성하고, 실리콘과 알루미늄의 상호 확산으로 인한 접합 파괴(Junction Spiking)를 방지하기 위하여 용융점 높은 Ti막(14)과 TiN막(15)을 연이어 증착하고, 화학기상증착법(Chemical Vapor Deposition)으로 알루미늄막(16)을 증착한다. 이때 알루미늄막(16)의 증착은AIH(CH3)2를 소스(source)로 사용하여 300℃士100℃의 온도 범위와 20 Torr 미만의 압력에서 이루어진다In the metal wiring forming process according to the present embodiment, first, as shown in FIG. 1A, a predetermined lower layer process is performed on the
이어서, 도IB에 도시한 바와 같이 화학 기계적 연마(Chemical-Mechanical Polishing) 공정을 통해 TiN막(15)이 노출될 정도로 알루미늄막(16)을 평탄화시키고, 전체 구조 상부에 장벽금속막인 TiN막(17)을 증착한 후, 화학기상증착법 또는 스퍼터링법(Sputtering)으로 금속배선용 구리막(18)을 증착한다. 이때 화학기상증착법으로 구리막(18)을 증착할 경우 소스로(C5HO2F7)Cu[CH2CH(Si(CH3)3)] ((hfac)Cu(tmvs))를 사용하여 300℃士100℃ 온도 범위와 40 Torr 미만의 압력에서 증착한다.Subsequently, as shown in FIG. IB, the
다음으로, 도1C에 도시한 바와 같이 화학 기계적 연마법으로 구리막(18)을 일정 부분만큼 연마하여 평탄하게 만든 후, 그 상부에 반사방지막(19)을 증착한다. 이때 구리막(18) 증착 과정에서 스퍼터링법을 사용한 경우는 구리를 평탄화하는 과정이 생략된다.Next, as shown in FIG. 1C, the
이후, 금속배선 마스크를 사용한 사진 공정 및 식각 공정을 진행하여 금속배선 공정을 완료한다.Thereafter, the metallization process is completed by performing a photolithography process and an etching process using the metallization mask.
상기와 같은 공정을 진행하는 경우, 화학기상증착 방식으로 알루미늄을 증착하여 콘택 플러그를 형성하기 때문에 콘택홀 매립 특성이 우수하고, 텅스텐 플러그 사용시에 비해 생산 단가가 낮고 저항이 낮다는 장점이 있다. 또한, 금속배선 재료로서 기존의 알루미늄막을 대신하여 구리막을 적용하기 때문에 일렉트로 마이그레이션과 같은 문제점을 방지할 수 있다.In the case of proceeding as described above, since the contact plug is formed by depositing aluminum by chemical vapor deposition, the contact hole filling characteristics are excellent, and the production cost is low and the resistance is low compared to the use of tungsten plug. In addition, since a copper film is applied in place of the existing aluminum film as the metal wiring material, problems such as electromigration can be prevented.
도2A 내지 도2F는 본 발명에 다른 실시예에 따른 반도체 장치의 금속 배선 형성 공정을 나타낸 단면도이다.2A to 2F are cross-sectional views illustrating a metal wiring formation process of a semiconductor device according to another embodiment of the present invention.
본 실시예에 따른 금속 배선 형성 공정은, 우선 도2A에 도시한 바와 같이 반도체 기판(21)에 대해 소정의 하부층 공정을 진행하여 층간절연막(22)이 형성된 상태에서, 통상의 공정을 통해 하부 금속 배선(23) 및 층간절연막(24)을 형성한다.In the metal wiring forming process according to the present embodiment, first, as shown in FIG. 2A, a predetermined lower layer process is performed on the
이어서, 도2B에 도시한 바와 같이 층간절연막(24)을 화학 기계적 연마법으로평탄화시키고, 그 상부에 금속배선 형성 영역을 노출시키는 포토레지스트 패턴(25)을 형성한다.Subsequently, as shown in FIG. 2B, the
다음으로, 도2C에 도시한 바와 같이, 포토레지스트 패턴(25)을 식각 베리어로 사용하여 층간절연막(24)의 일부를 식각함으로서 배선용 홈(100)을 형성하고, 를 형성하고, 포토레지스트 패턴(25)을 제거한 다음, 다시 비아홀 영역을 노출시키는 포토레지스트 패턴(26)을 형성한다.Next, as shown in FIG. 2C, by using a photoresist pattern 25 as an etching barrier, a part of the
다음으로, 도2D에 도시한 바와 같이 포토레지스트 패턴(26)을 식각베리어로 사용하여 층간절연막(24)을 식각함으로써 하부 금속 배선(23)을 노출시키는 비아홀(200)을 형성한 다음, 포토레지스트 패턴(26)을 제거한다.Next, as shown in FIG. 2D, the
다음으로, 도2E에 도시한 바와 같이, 비아홀의 일부(200)에 알루미늄(27)을 화학기상증착법으로 증착하고, 장벽금속막으로 TiN막(28)을 증착하고 금속배선용 구리막(29)을 화학기상증착법으로 증착한다. 이때 알루미늄 소스로는 AlH(CH3)2를 사용하고 증착 온도는 300 ℃ ± 100℃, 압력은 20 토르(Torr) 미만으로 하여 노출된 하부 금속 배선(23) 상에서만 선택적으로 증착한다. 또한, 구리 소스로는 (C5HO2F7)Cu[CH2CH(Si(CH3)3)]((hfac)Cu(tmvs))를 사용하고, 증착 온도는 300 ℃±100℃ , 압력은 40 토르(Torr) 미만으로 한다.Next, as shown in FIG. 2E,
다음으로, 도2F에 도시한 바와 같이 층간절연막(24)이 노출될 정도로 구리막(29)을 화학 기계적 연마법으로 연마하고, 그 상부에 반사방지막(30)을 증착한다.Next, as shown in FIG. 2F, the
상기와 같이 대머신 금속배선 공정에 본 발명을 적용하는 경우, 화학기상증착 방식으로 알루미늄을 증착하여 플러그를 형성하기 때문에 비아홀 매립 특성이 우수하고, 텅스텐 플러그 사용시에 비해 생산 단가가 낮고 저항이 낮다는 장점이있다. 또한, 금속배선 재료로서 기존의 알루미늄막을 대신하여 구리막을 적용하기 때문에 일렉트로 마이그레이션과 같은 문제점을 방지할 수 있다.In the case of applying the present invention to the metallization process as described above, since the plug is formed by depositing aluminum by chemical vapor deposition, the via hole filling characteristics are excellent, and the production cost is lower and the resistance is lower than when using the tungsten plug. There is an advantage. In addition, since a copper film is applied in place of the existing aluminum film as the metal wiring material, problems such as electromigration can be prevented.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어서 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 직접도가 높은 반도체 장치의 전기적 연결을 위한 홀에 화학기상증착법과 화학 기계적 연마법으로 전도막을 매립함으로써 반도체 장치의 전기적 특성 및 내구성이 향상되어 소자의 신뢰성을 높일 수 있다.According to the present invention, the conductive film is embedded in the hole for electrical connection of the semiconductor device having high directivity by chemical vapor deposition and chemical mechanical polishing, thereby improving the electrical characteristics and durability of the semiconductor device, thereby increasing the reliability of the device. .
도1A 내지 도1C는 본 발명의 일실시예에 따른 반도체 장치의 금속 배선 형성 공정을 나타낸 단면도.1A to 1C are cross-sectional views illustrating a metal wiring formation process of a semiconductor device according to an embodiment of the present invention.
도2A 내지 도2F는 본 발명에 다른 실시예에 따른 반도체 장치의 금속 배선 형성 공정을 나타낸 단면도.2A to 2F are sectional views showing a metal wiring formation process of a semiconductor device according to another embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
11,21: 반도체 기판 12: 도전층11, 21: semiconductor substrate 12: conductive layer
13,22,24,30: 층간절연막 14: Ti막13,22,24,30: interlayer insulating film 14: Ti film
15,17,28: TiN막 16, 27: 알루미늄막15, 17, 28: TiN
18,29: 구리막 19: 반사방지막18,29: copper film 19: antireflection film
23: 하부 금속 배선 25,26:포토레지스트 패턴23: lower metal wiring 25, 26: photoresist pattern
Claims (11)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970019057A KR100470923B1 (en) | 1997-05-16 | 1997-05-16 | Metal wiring formation method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970019057A KR100470923B1 (en) | 1997-05-16 | 1997-05-16 | Metal wiring formation method of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR19980083676A KR19980083676A (en) | 1998-12-05 |
| KR100470923B1 true KR100470923B1 (en) | 2005-05-10 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4720908A (en) * | 1984-07-11 | 1988-01-26 | Texas Instruments Incorporated | Process for making contacts and interconnects for holes having vertical sidewalls |
| US5070391A (en) * | 1989-11-30 | 1991-12-03 | Sgs-Thomson Microelectronics, Inc. | Semiconductor contact via structure and method |
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1997
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4720908A (en) * | 1984-07-11 | 1988-01-26 | Texas Instruments Incorporated | Process for making contacts and interconnects for holes having vertical sidewalls |
| US5070391A (en) * | 1989-11-30 | 1991-12-03 | Sgs-Thomson Microelectronics, Inc. | Semiconductor contact via structure and method |
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