KR100203303B1 - Method of forming metal interconnection of semiconductor device - Google Patents
Method of forming metal interconnection of semiconductor device Download PDFInfo
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- KR100203303B1 KR100203303B1 KR1019960013443A KR19960013443A KR100203303B1 KR 100203303 B1 KR100203303 B1 KR 100203303B1 KR 1019960013443 A KR1019960013443 A KR 1019960013443A KR 19960013443 A KR19960013443 A KR 19960013443A KR 100203303 B1 KR100203303 B1 KR 100203303B1
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- film
- metal
- metal film
- semiconductor device
- wiring
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 64
- 239000002184 metal Substances 0.000 title claims abstract description 64
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 27
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 239000011229 interlayer Substances 0.000 claims description 12
- 229910045601 alloy Inorganic materials 0.000 claims description 9
- 239000000956 alloy Substances 0.000 claims description 9
- 239000010410 layer Substances 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 239000010936 titanium Substances 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 특히, 반도체 소자의 금속 배선 공정시, 반도체 기판과 금속 배선 사이에, 오믹특성 및 스텝 커버리지를 향상시킬 수 있는 반도체 소자의 금속 배선 형성방법에 관한 것으로, 반도체 소자의 소오스 드레인 전극에 실리사이드막을 형성하고, 그 상부에 금속막을 형성한다음, 열처리 공정을 진행하여, 실리사이드막과 금속막 사이의 계면에 형성되는 막을 베리어 금속막으로 하므로서, 적층막으로 인하여 발생되는 언더컷 현상과, 높은 스텝 커버리지가 감소시키고, 더불어 금속막과 반도체 기판간의 접촉 특성을 향상시키어, 배선 특성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device, and more particularly, to a method for forming metal wirings in a semiconductor device that can improve ohmic characteristics and step coverage between a semiconductor substrate and a metal wiring during a metal wiring process of a semiconductor device. A silicide film is formed on a source drain electrode of a semiconductor element, a metal film is formed thereon, and then a heat treatment step is performed to make a film formed at the interface between the silicide film and the metal film as a barrier metal film. The undercut phenomenon caused by this, and high step coverage are reduced, and also the contact characteristic between a metal film and a semiconductor substrate can be improved, and wiring characteristic can be improved.
Description
제1도는 종래의 반도체 소자의 금속 배선 형성방법에 따라 제조된 반도체 소자의 단면도.1 is a cross-sectional view of a semiconductor device manufactured according to a metal wiring forming method of a conventional semiconductor device.
제2a도 내지 제2c도는 본 발명의 일실시예를 설명하기 위한 각 제조 공정별 단면도.2a to 2c is a cross-sectional view of each manufacturing process for explaining an embodiment of the present invention.
제3a도 및 제3b도는 본 발명의 제2실시예를 설명하기 위한 각 제조 공정별 단면도..3a and 3b are cross-sectional views for each manufacturing process for explaining the second embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11,21 : 반도체 기판 12,22 : 필드 산화막11,21: semiconductor substrate 12,22: field oxide film
13,23 : 게이트 전극 14,24 : 소오스, 드레인13,23: gate electrode 14,24: source, drain
15 : 텅스텐막 16,26 : 실리사이드막15: tungsten film 16, 26 silicide film
17,25 : 층간 절연막 18,27 : 금속막17,25 interlayer insulation film 18,27 metal film
160,260 : 베리어 금속막160,260: Barrier Metal Film
[발명의 기술분야]Technical Field of the Invention
본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 특히, 반도체 소자의 금속 배선 공정시, 반도체 기판과 금속 배선 사이에, 오믹(ohmic) 특성 및 스텝 커버리지를 향상시킬 수 있는 반도체 소자의 금속 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices. In particular, metal wirings in semiconductor devices capable of improving ohmic characteristics and step coverage between semiconductor substrates and metal wirings in the metal wiring process of semiconductor devices. It relates to a formation method.
[종래 기술][Prior art]
최근 반도체 소자의 집적도가 증가함에 따라 배선 설계가 자유롭고 용이하며 배선저항 및 전류용량등의 설정을 여유있게 할 수 있는 금속 배선 기술에 관한 연구가 활발히 진행되고 있다.Recently, as the degree of integration of semiconductor devices increases, research on metallization technologies that can freely and easily design wirings and allow setting of wiring resistance and current capacity, etc., has been actively conducted.
일반적으로 반도체 금속 배선의 재료로는 저저항을 가지고 있는 알루미늄이 널리 이용되고 있는데, 소자의 집적도가 증가함으로 인하여 배선의 폭이 미세화되고, 전류 밀도가 증가되어, 전자 이동, 난반사 및 스트레스의 이동이 발생된다. 이로 인하여, 금속 배선 공정시 불량이 발생되고, 반도체 소자의 신뢰성을 저하된다. 이러한 문제점을 보완하기 위하여 알루미늄 배선막상에 구리(Cu) 또는 티타늄(Ti)등을 적층하여 전자이동 및 스트레스의 이동으로 인한 일루미늄의 단선은 방지할 수 있었지만, 힐록(hillock) 및 휘스커(whisker)등의 현상이 발생하여 쇼트 및 절연막 파괴등의 문제가 발생되었다.In general, aluminum having low resistance is widely used as a material for semiconductor metal wiring. As the degree of integration of devices increases, the width of the wiring becomes finer and the current density increases, so that electron transfer, diffuse reflection, and stress transfer occur. Is generated. For this reason, a defect arises in a metal wiring process, and the reliability of a semiconductor element falls. In order to compensate for this problem, the aluminum wires were laminated with copper (Cu) or titanium (Ti) to prevent the disconnection of the aluminum due to electron movement and stress movement. However, hillock and whiskers were prevented. And other phenomena occurred, such as short circuits and breakdown of the insulating layer.
종래에는 제1도에 도시되어 있는 바와 같이, 필드 산화막(2), 게이트(3), 소오스/드레인 전극(4)가 형성된 반도체 기판 상부에 층간 절연막(5)이 형성되고, 층간 절연막(5)은 금속 배선이 이루어질 소오스/드레인 전극(4)이 노출되도록 식각된다. 그런다음, 전자 및 스트레스의 이동을 방지하기 위하여, 베리어 금속막으로 Ti/TiN막(6)이 약 1000Å 두께로 형성된다음, 그 상부에 전도 특성이 우수한 알루미늄 금속막(7)이 증착되고, 배선의 형태로 식각된다.Conventionally, as shown in FIG. 1, an interlayer insulating film 5 is formed on a semiconductor substrate on which a field oxide film 2, a gate 3, and a source / drain electrode 4 are formed, and an interlayer insulating film 5 It is etched so that the source / drain electrodes 4 on which the metal wirings will be made are exposed. Then, in order to prevent the movement of electrons and stress, the Ti / TiN film 6 is formed to a thickness of about 1000 kPa with a barrier metal film, and then an aluminum metal film 7 having excellent conductivity is deposited thereon, and the wiring Etched in the form of.
[발명이 이루고자 하는 기술적 과제][Technical problem to be achieved]
그러나, 종래의 금속 배선 형성방법은, 베리어 금속막으로 Ti/TiN막으로 형성되므로 인하여, 배선이 형성되기 위한 식각 공정시, Ti막과 TiN막간에 언더컷이 발생되는 문제점이 발생되었으며, 베리어 금속막의 두께가 약 1000Å 정도이므로, 스텝 커버리지가 증가되는 문제점 또한 발생되었다.However, in the conventional metal wiring forming method, since the barrier metal film is formed of a Ti / TiN film, there is a problem that an undercut occurs between the Ti film and the TiN film during the etching process for forming the wiring. Since the thickness is about 1000 GPa, there is a problem that the step coverage is increased.
따라서, 본 발명은, 상술된 종래의 문제점을 해결하기 위한 것으로, 배리어 금속막을 실리사이드막과 금속막의 합금막으로 하여, 적층막으로 인하여 발생되는 언더컷 현상과, 높은 스텝 커버리지가 감소시키고, 더불어 금속막과 반도체 기판간의 접촉 특성을 향상시키어, 배선 특성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성방법을 제공하는 것을 목적으로 한다.Accordingly, the present invention is to solve the above-mentioned conventional problems, and by using the barrier metal film as an alloy film of the silicide film and the metal film, the undercut phenomenon caused by the laminated film and the high step coverage are reduced, and the metal film An object of the present invention is to provide a method for forming a metal wiring of a semiconductor element which can improve the contact characteristics between the semiconductor substrate and the semiconductor substrate and thereby improve the wiring characteristics.
[발명의 구성 및 작용][Configuration and Function of Invention]
상기한 종래의 문제점을 해결하기 위한 것으로, 본 발명은, 게이트 전극 및 소오스, 드레인 전극이 형성된 반도체 기판상부에 층간 절연막을 형성하고, 소오스, 드레인 전극이 노출되도록 층간절연막의 일부분을 식각한다음, 베리어 금속막을 형성하고, 금속 배선막을 형성하는 반도체 소자의 금속 배선 형성방법에 있어서, 상기 베리어 금속막은 실리사이드막과 금속막의 합금막인 것을 특징으로 한다.In order to solve the above problems, the present invention provides an interlayer insulating film on a semiconductor substrate on which a gate electrode, a source and a drain electrode are formed, and etching a portion of the interlayer insulating film to expose the source and drain electrodes. In the metal wiring forming method of the semiconductor element which forms a barrier metal film and forms a metal wiring film, The said barrier metal film is an alloy film of a silicide film and a metal film.
이로써, 금속 배선의 접촉 특성 및 스텝 커버리지가 향상된다.This improves the contact characteristics and step coverage of the metal wiring.
[실시예 1]Example 1
이하, 첨부된 도면에 의하여 본발명의 양호한 실시예들을 자세히 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 제2a도 내지 제2c도는 본 발명의 제1실시예를 설명하기 위한 각 제조 공정별 단면도이다.2A to 2C are cross-sectional views of respective manufacturing processes for explaining the first embodiment of the present invention.
먼저, 제2a도에 도시된 바와 같이, 반도체 기판(11)에 국부 산화방식에 의하여, 필드 산화막(12)이 형성되고, 공지된 방식에 의하여 게이트(13), 소오스/드레인 전극(14)이 형성된다. 이어서, 전체 구조물 상부에 전이 금속막 예를들어, 텅스텐막(15)이 소정 두께로 증착된다.First, as shown in FIG. 2A, the field oxide film 12 is formed on the semiconductor substrate 11 by a local oxidation method, and the gate 13 and the source / drain electrodes 14 are formed by a known method. Is formed. Subsequently, a transition metal film, for example, a tungsten film 15, is deposited on the entire structure to a predetermined thickness.
제2b도에 도시된 바와 같이, 제2a도의 결과물은 소정 온도에서, 열처리 공정이 진행된다. 그러면, 실리콘 부위와 접합된 텅스텐 금속막(15) 즉, 게이트(13), 소오스/드레인 전극(14) 상부의 텅스텐 금속막(15)은 게이트(13), 소오스/드레인 전극(14)으로 부터 실리콘이 제공되어, 실리사이드막(16)이 형성된다.As shown in FIG. 2B, the resultant of FIG. 2A is subjected to a heat treatment process at a predetermined temperature. Then, the tungsten metal film 15 bonded to the silicon portion, that is, the tungsten metal film 15 on the gate 13 and the source / drain electrodes 14, is transferred from the gate 13 and the source / drain electrodes 14. Silicon is provided to form the silicide film 16.
그 다음으로, 제2c도에 도시된 바와 같이, 반응되지 않은 텅스텐 금속막(15)은 통상의 제거 방식에 의하여 제거되고, 전체 구조물 상부에 층간 절연막(17)이 형성된다. 이어서, 층간 절연막(17)은 소오스/드레인 전극(14)이 노출되도록 소정 부분 식각되고, 금속 배선(18)이 형성된다. 그런다음, 소정 온도에서 열처리 공정이 진행된다. 그러면, 실리사이드막(16)과 금속 배선(18)계면에는 실리사이드막(16)과 금속막(18)의 합금막(160)이 형성된다. 여기서, 실리사이드막(16)과 금속막(18)의 합금막(160)은 본 실시예에서 베리어 금속막으로 이용된다. 이로써, 소오스/드레인 전극(14) 상부에만 실리사이드막(16)이 형성되어, 실리사이드막에 의한 오믹 접촉 특성이 향상되는 것과 동시에, 금속 베선과의 열처리에 의하여 베리어 금속막(160)이 형성되어, 스텝 커버리지가 향상된다.Next, as shown in FIG. 2C, the unreacted tungsten metal film 15 is removed by a conventional removal method, and an interlayer insulating film 17 is formed over the entire structure. Subsequently, the interlayer insulating layer 17 is partially etched to expose the source / drain electrodes 14, and metal wirings 18 are formed. Then, the heat treatment process proceeds at a predetermined temperature. Then, the alloy film 160 of the silicide film 16 and the metal film 18 is formed on the silicide film 16 and the metal wiring 18 interface. Here, the alloy film 160 of the silicide film 16 and the metal film 18 is used as the barrier metal film in this embodiment. As a result, the silicide film 16 is formed only on the source / drain electrodes 14, thereby improving ohmic contact characteristics by the silicide film, and forming the barrier metal film 160 by heat treatment with the metal wire. Step coverage is improved.
[실시예 2]Example 2
첨부한 도면 제3a도 및 제3b도는 본 발명의 제2실시예를 설명하기 위한 각 제조 공정별 단면도이다. 또한, 본 실시예는 상술된 제1실시예의 층간 절연막이 소오스/드레인 전극이 노출되도록 식각되는 일련의 공정은 동일하고, 그 다음 공정에 대하여만 설명하기로 한다.3A and 3B are cross-sectional views of respective manufacturing processes for explaining a second embodiment of the present invention. In this embodiment, the series of processes in which the interlayer insulating film of the first embodiment described above is etched to expose the source / drain electrodes are the same, and only the following processes will be described.
먼저, 제3a도에 도시되어 있는 바와 같이, 노출된 소오스/드레인 전극(24)과 접촉되도록 전체 구조물 상부에 실리사이드막(26)이 450 내지 550Å의 두께로 화학 기상 증착법에 의하여 증착되고, 그 상부에 알루미늄 금속이 포함된 금속막(27)이 형성된다.First, as shown in FIG. 3A, a silicide film 26 is deposited by chemical vapor deposition to a thickness of 450 to 550 kPa over the entire structure so as to contact the exposed source / drain electrodes 24. A metal film 27 containing aluminum metal is formed on the substrate.
그 다음으로, 제3b도에 도시된 바와 같이, 결과물은 300 내지 500℃의 온도에서 열처리 공정이 진행된다. 그러면, 실리사이드막(26)과 알루미늄 금속이 포함된 금속막(27)의 계면에는 실리사이드막과 금속막과의 합금막(26)이 형성되고, 여기서, 합금막(26)은 본 실시예에서의 베리어 금속막의 역할을 하며, 다음과 같은 공식에 의하여 형성된다.Next, as shown in Figure 3b, the resultant is subjected to a heat treatment process at a temperature of 300 to 500 ℃. Then, at the interface between the silicide film 26 and the metal film 27 containing aluminum metal, an alloy film 26 of the silicide film and the metal film is formed, where the alloy film 26 is formed according to the present embodiment. It acts as a barrier metal film and is formed by the following formula:
이때, 합금막으로 이루어진 베리어 금속막(260)의 두께는 열처리 시간과 비례하므로, 베리어 금속막(260)의 두께가 800 내지 900Å두께가 되도록 열처리된다. 그후, 실리사이드막(26)과 알루미늄 금속이 포함된 금속막(27) 및 실리사이드막과 금속막사이의 합금막인 베리어 금속막(260)이 배선의 형태로 식각된다.At this time, since the thickness of the barrier metal film 260 made of an alloy film is proportional to the heat treatment time, the barrier metal film 260 is heat-treated so that the thickness of the barrier metal film 260 is 800 to 900 kPa. Thereafter, the silicide film 26 and the metal film 27 containing aluminum metal and the barrier metal film 260 which is an alloy film between the silicide film and the metal film are etched in the form of wiring.
[발명의 효과][Effects of the Invention]
이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 반도체 소자의 소오스 드레인 전극에 실리사이드막을 형성하고, 그 상부에 금속막을 형성한 다음, 열처리 공정을 진행하여, 실리사이드막과 금속막 사이의 계면에 형성되는 막을 베리어 금속막으로 하므로서, 적층막으로 인하여 발생되는 언더컷현상과, 높은 스텝 커버리지가 감소시키고, 더불어 금속막과 반도체 기판간의 접촉 특성을 향상시키어, 배선 특성을 향상시킬 수 있다.As described in detail above, according to the present invention, a silicide film is formed on a source drain electrode of a semiconductor device, a metal film is formed thereon, and a heat treatment process is performed to form at the interface between the silicide film and the metal film. By using the barrier film as a barrier metal film, the undercut phenomenon caused by the laminated film and the high step coverage can be reduced, and the contact characteristics between the metal film and the semiconductor substrate can be improved to improve the wiring characteristics.
Claims (5)
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| KR1019960013443A KR100203303B1 (en) | 1996-04-29 | 1996-04-29 | Method of forming metal interconnection of semiconductor device |
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| KR1019960013443A KR100203303B1 (en) | 1996-04-29 | 1996-04-29 | Method of forming metal interconnection of semiconductor device |
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| KR100203303B1 true KR100203303B1 (en) | 1999-06-15 |
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