KR100259098B1 - Method for forming metal line of semiconductor device - Google Patents
Method for forming metal line of semiconductor device Download PDFInfo
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- KR100259098B1 KR100259098B1 KR1019980004642A KR19980004642A KR100259098B1 KR 100259098 B1 KR100259098 B1 KR 100259098B1 KR 1019980004642 A KR1019980004642 A KR 1019980004642A KR 19980004642 A KR19980004642 A KR 19980004642A KR 100259098 B1 KR100259098 B1 KR 100259098B1
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- South Korea
- Prior art keywords
- barrier layer
- upper barrier
- metal wiring
- semiconductor device
- aluminum
- Prior art date
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 37
- 239000002184 metal Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 45
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 25
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 25
- 230000007547 defect Effects 0.000 claims abstract description 9
- 239000013078 crystal Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000004411 aluminium Substances 0.000 abstract 3
- 238000004380 ashing Methods 0.000 abstract 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910016006 MoSi Inorganic materials 0.000 description 1
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PYLLWONICXJARP-UHFFFAOYSA-N manganese silicon Chemical compound [Si].[Mn] PYLLWONICXJARP-UHFFFAOYSA-N 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조공정에 관한 것으로, 특히 금속배선의 결함을 방지하여 배선의 신뢰성을 향상시키는데 적당한 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device suitable for preventing defects in the metal wiring and improving the reliability of the wiring.
일반적으로 반도체 제조공정시 가장 많이 사용하는 금속재료는 알루미늄과 알루미늄 합금이다. 그 이유는 전기전도성이 좋고, 산화막과의 접착력이 뛰어날 뿐만 아니라 성형하기 쉽기 때문이다.In general, the most used metal materials in the semiconductor manufacturing process are aluminum and aluminum alloys. The reason for this is that the electrical conductivity is good, the adhesion to the oxide film is excellent, and the molding is easy.
그러나 전기적 물질이동, 힐록(Hillock) 및 스파이크(Spike) 등의 문제점을 가지고 있다.However, there are problems such as electrical mass transfer, hillock, and spike.
상기 배선금속용 알루미늄에 전류를 흐르게 하면, 실리콘과의 접촉지역이나 계단 지역 등의 고전류밀도지역에서 알루미늄 원자의 확산이 일어나, 그 부위의 금속선이 얇아지고 결국은 단락 되는데 이런 현상을 전기적 물질이동이라 하며, 이러한 전기적 물질이동은 서서히 소량으로 확산되어 일어나므로 작동후, 상당한 시간이 경과한 후에 유발된다.When a current flows through the aluminum for the wiring metal, aluminum atoms diffuse in a high current density region such as a contact region with a silicon or a step region, and a metal wire becomes thinner and eventually short-circuited. In addition, the electrical movement is caused by a small amount of diffusion gradually occurs after the operation, a considerable time has elapsed.
상기와 같은 문제점을 해결하기 위해서는 알루미늄에 소량의 구리(Cu)를 첨가한 알루미늄-구리 합금을 사용하던가 스텝커버레이지(Stepcoverage)를 향상시키고, 접촉지역을 충분히 넓게 설계함으로써 해결할 수 있다.In order to solve the above problems, it is possible to solve the problem by using an aluminum-copper alloy in which a small amount of copper (Cu) is added to aluminum or by improving step coverage and designing a sufficiently wide contact area.
이하, 첨부된 도면을 참고하여 종래 기술의 반도체 소자의 금속배선 형성방법을 설명하면 다음과 같다.Hereinafter, a metal wiring forming method of a semiconductor device of the prior art will be described with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래 기술의 반도체 소자의 금속배선 형성방법을 나타낸 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device of the prior art.
도 1a에 도시한 바와같이 반도체 기판(11)상에 하부 베리어층(12)을 형성하고, 상기 하부 베리어층(12)상에 알루미늄막(13)을 증착하고, 상기 알루미늄막(13)상에 300Å 두께로 상부 베리어층(14)을 증착한다.As shown in FIG. 1A, a lower barrier layer 12 is formed on a semiconductor substrate 11, an aluminum film 13 is deposited on the lower barrier layer 12, and an upper barrier layer 12 is deposited on the aluminum film 13. The upper barrier layer 14 is deposited to a thickness of 300 mm 3.
여기서 상기 상부 베리어층(14)은 텅스텐 티타늄(TiW), 질화 티타늄(TiN) 등을 사용한다.Here, the upper barrier layer 14 uses tungsten titanium (TiW), titanium nitride (TiN), or the like.
한편, 상기 알루미늄막(13)은 빛의 반사율이 우수하여 포토작업시 패턴형성에 어려움이 있기 때문에 상기 알루미늄막(13)상에 상부 베리어층(14)을 형성하여 포토공정의 공정마진을 확보한다.On the other hand, since the aluminum film 13 has excellent reflectance of the light, it is difficult to form a pattern during photo work, thereby forming an upper barrier layer 14 on the aluminum film 13 to secure a process margin of the photo process. .
그러나 상기 상부 베리어층(14)의 형성시 상부 베리어층(14)의 두께 및 결정구조 결함 등으로 인해 상기 상부 베리어층(14)에 틈(A)이 발생한다.However, when the upper barrier layer 14 is formed, a gap A occurs in the upper barrier layer 14 due to the thickness of the upper barrier layer 14 and defects in crystal structure.
도 1b에 도시한 바와같이 상기 상부 베리어층(14)과 알루미늄막(13)과 하부 베리어층(12)에 포토공정을 실시하여 선택적으로 제거함으로써 금속배선(13a)을 형성한다.As shown in FIG. 1B, the upper barrier layer 14, the aluminum layer 13, and the lower barrier layer 12 are subjected to a photo process to selectively remove the metal wiring 13a.
도 1c에 도시한 바와같이 상기 금속배선(13a)을 형성한 후, 후처리공정을 실시하여 금속배선(13a)에 발생된 이물질(예를 들면 폴리머 등)을 제거한다.After forming the metal wiring 13a as shown in FIG. 1C, a post-treatment process is performed to remove foreign substances (eg, polymers) generated in the metal wiring 13a.
이때, 상기 상부 베리어층(14)에 발생한 틈(A)에 의해 후처리공정시 Cl_기가 틈(A)새로 침투하여 금속배선(13a)이 부분적으로 식각되고, 상기 Cl_기가 금속배선(13a)의 알루미늄과 반응하여 코로우죤(Corrosion) 발생 및 금속배선(13a)이 식각된다.In this case, during the post-treatment process, the Cl _ group penetrates into the gap A by the gap A generated in the upper barrier layer 14, thereby partially etching the metal wiring 13a, and the Cl _ metal wiring 13a. Corrosion is generated and the metallization 13a is etched by reacting with aluminum.
여기서 미설명 부호인 B는 금속배선(13a)의 식각된 부분이고, 상기 코로우죤은 알루미늄과 Cl_기의 반응으로 인해 부피팽창된 현상을 말한다.Here, reference numeral B denotes an etched portion of the metal wiring 13a, and the co-row zone refers to a volume expanded phenomenon due to the reaction between aluminum and Cl _ group.
그러나 상기와 같은 종래 기술의 반도체 소자의 금속배선 형성방법에 있어서 다음과 같은 문제점이 있었다.However, the metal wiring formation method of the conventional semiconductor device as described above has the following problems.
즉, 상부 베리어층의 형성 두께 및 결정구조의 결함으로 인해 상부 베리어층에 틈이 발생하여 후처리공정시 금속배선에 결함이 발생함으로써 금속배선의 신뢰성을 저하시킨다.That is, a gap occurs in the upper barrier layer due to the formation thickness of the upper barrier layer and defects in the crystal structure, thereby deteriorating the reliability of the metal wiring by causing defects in the metal wiring during the post-treatment process.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 상부 베리어층의 구조 변경을 통하여 금속배선의 결함을 방지하여 금속배선의 신뢰성을 향상시키도록 한 반도체 소자의 금속배선 형성방법을 제공하는 데 그 목적이 있다.The present invention has been made to solve the above problems to provide a method for forming a metal wiring of the semiconductor device to improve the reliability of the metal wiring by preventing the defect of the metal wiring by changing the structure of the upper barrier layer. There is a purpose.
도 1a 내지 도 1c는 종래 기술의 반도체 소자의 금속배선 형성방법을 나타낸 공정단면도1A to 1C are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device of the related art.
도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 금속배선 형성방법을 나타낸 공정단면도2A to 2C are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
21 : 반도체 기판 22 : 하부 베리어층21 semiconductor substrate 22 lower barrier layer
23 : 알루미늄막 23a : 금속배선23: aluminum film 23a: metal wiring
24 : 상부 베리어층24: upper barrier layer
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 금속배선 형성방법은 반도체 기판상에 하부 베리어층을 형성하는 단계와, 상기 하부 베리어층상에 알루미늄막을 증착하는 단계와, 상기 알루미늄막상에 600Å이상의 두께로 상부 베리어층을 형성하는 단계와, 상기 상부 베리어층을 포함한 전면에 UVAS 처리를 실시하는 단계와, 그리고 상기 상부 베리어층과 알루미늄막과 하부 베리어층을 선택적으로 제거하여 금속배선을 형성하는 단계를 포함하여 형성함을 특징으로 한다.According to an aspect of the present invention, there is provided a method for forming a metal wiring of a semiconductor device, the method comprising: forming a lower barrier layer on a semiconductor substrate, depositing an aluminum film on the lower barrier layer, and forming a 600 Å film on the aluminum layer. Forming an upper barrier layer with a thickness above, performing a UVAS treatment on the entire surface including the upper barrier layer, and selectively removing the upper barrier layer, the aluminum layer, and the lower barrier layer to form a metal wiring; Characterized in that it comprises a step.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 금속배선 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a metal wiring forming method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2c는 본 발명에 의한 반도체 소자의 금속배선 형성방법을 나타낸 공정단면도이다.2A through 2C are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to the present invention.
도 2a에 도시한 바와같이 반도체 기판(21)상에 하부 베리어층(22)을 형성하고, 상기 하부 베리어층(22)상에 알루미늄막(23)을 스퍼터링 방법으로 증착한다.As shown in FIG. 2A, a lower barrier layer 22 is formed on the semiconductor substrate 21, and an aluminum film 23 is deposited on the lower barrier layer 22 by a sputtering method.
이어, 상기 알루미늄막(23)상에 600Å이상의 두께로 상부 베리어층(24)을 형성한다.Subsequently, the upper barrier layer 24 is formed on the aluminum film 23 to a thickness of 600 GPa or more.
여기서 상기 상부 베리어층(24)은 텅스텐 티타늄(TiW), 질화 티타늄(TiN), 실리콘 망간(MoSi) 등을 사용한다.Here, the upper barrier layer 24 uses tungsten titanium (TiW), titanium nitride (TiN), silicon manganese (MoSi), or the like.
한편, 상기 상부 베리어층(24) 형성후, 상기 알루미늄막(23)과 접착 및 결정결함을 해소하기 위해 300℃의 온도에서 3분 정도 UVAS(Ultra Vacuum Asing) 처리를 실시하여 접착 및 결정결함을 해결한다.Meanwhile, after the upper barrier layer 24 is formed, UVAS (Ultra Vacuum Asing) treatment is performed at a temperature of 300 ° C. for about 3 minutes to eliminate adhesion and crystal defects with the aluminum layer 23. Solve.
도 2b에 도시한 바와같이 상기 상부 베리어층(24)과 알루미늄막(23)과 하부 베리어층(22)에 포토공정을 실시하여 선택적으로 제거함으로써 금속배선(23a)을 형성한다.As shown in FIG. 2B, the upper barrier layer 24, the aluminum layer 23, and the lower barrier layer 22 are subjected to a photo process to selectively remove the metal wiring 23a.
도 2c에 도시한 바와같이 상기 금속배선(23a)을 형성한 후, 후처리공정을 실시하여 금속배선(23a)에 발생된 이물질(예를 들면 폴리머 등)을 제거한다.As shown in FIG. 2C, after the metal wiring 23a is formed, a post-treatment step is performed to remove foreign substances (for example, polymers) generated in the metal wiring 23a.
이상에서 설명한 바와같이 본 발명에 의한 반도체 소자의 금속배선 형성방법에 있어서 상부 베리어층의 두께 및 UVAS 처리를 통해 결정구조의 안정화를 통해 금속배선의 결함을 방지하여 금속배선의 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, in the method of forming the metal wiring of the semiconductor device according to the present invention, the reliability of the metal wiring can be improved by preventing the defect of the metal wiring by stabilizing the crystal structure through the thickness of the upper barrier layer and the UVAS treatment. It works.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980004642A KR100259098B1 (en) | 1998-02-16 | 1998-02-16 | Method for forming metal line of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980004642A KR100259098B1 (en) | 1998-02-16 | 1998-02-16 | Method for forming metal line of semiconductor device |
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| Publication Number | Publication Date |
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| KR19990070032A KR19990070032A (en) | 1999-09-06 |
| KR100259098B1 true KR100259098B1 (en) | 2000-06-15 |
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| KR1019980004642A KR100259098B1 (en) | 1998-02-16 | 1998-02-16 | Method for forming metal line of semiconductor device |
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- 1998-02-16 KR KR1019980004642A patent/KR100259098B1/en not_active IP Right Cessation
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