JP2001160590A - Method of forming wiring and method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the yield of a low-resistance multilayered wiring while the wiring is formed in forming the wiring through a short-time manufacturing process by applying the plating method to the damascene method, and to improve the reliability of the wiring when the wiring is in use. SOLUTION: In forming wiring 36 on wiring 23 formed by filling up wiring grooves 19 with plated Cu films 22 by filling up via holes 30 and wiring grooves 33 with plated Cu films 35 through the via holes 30, low-temperature annealing is performed immediately after the Cu films 22 and 35 which become the material films of the wiring 23 and 36 are formed. At the same time, the processing temperatures in various processes including the H2 plasma treatment performed after the wiring 23 and 36 are formed by CMP, and the continuous formation of interlayer insulating films 25 and 38 are controlled to a prescribed low temperature or lower.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of filling a wiring in a groove of an insulating film by a so-called damascene method and a method of manufacturing a semiconductor device provided with the wiring, and more particularly to a method of forming a multilayer wiring formed by a dual damascene method. It is suitable for application.

[0002]

2. Description of the Related Art In a conventional wiring technology of a semiconductor device, an Al alloy is used as a wiring material and a pattern is formed by a dry etching method. However, in recent years, further miniaturization and high-speed driving of semiconductor devices have been demanded, and wiring materials with lower resistance and higher current density have been demanded.
In addition, it is required to reduce the total processing time during formation. In order to respond to this, for example, Cu is used instead of an Al alloy as a wiring material, and application of a damascene method is being studied as a processing method. That is, in the case of forming a Cu wiring, the etching method causes corrosion due to the effect of the etchant and moisture and makes the formation difficult. Therefore, a metal is embedded in the groove of the insulating film and polished by polishing. It is necessary to form a wiring by using a so-called damascene method, in which metal is left only in a semiconductor device. This method is described in "PLANER COPPER-POLYIMIDE BACK END THE LINE IN" by B. Luther and others.
TER CONNECTIONS FOR ULSI DEVICES ”, Proceedings of
10 ^th International VMIC, have been reported in P15-21,1993.

In particular, in order to further reduce the number of steps, a lower wiring for filling a lower wiring groove is formed by a so-called damascene method, and then a via hole for connecting upper and lower adjacent wirings and an upper wiring are formed. After forming the upper wiring groove of
It is necessary to form a multilayer wiring by a so-called dual damascene method in which metal is simultaneously buried in the upper wiring groove and the via hole and polished. This method is disclosed by International Business Machine Corporation (IBM) in JP-A-10-143914.
In the case of using the dual damascene method, it is difficult to embed the metal into the wiring groove of the insulating film by the metal deposition by the sputtering method having the poor embedding performance as conventionally used, and the plating method is used instead of the conventional sputtering method. Therefore, it is necessary to deposit a wiring material.

[0004]

The metal deposited by the plating method has a more amorphous state immediately after the deposition than the metal deposited by the sputtering method and contains many voids. When a multilayer wiring of two or more layers is formed as a wiring of a semiconductor device, it is necessary to perform an annealing treatment in a hydrogen-containing atmosphere for reducing oxidation on the Cu surface during the formation process. Because of the change, agglomeration of voids in the metal and reduction in the volume of the metal itself occur in the wiring and the via hole. Due to this, there is a problem that a disconnection occurs in a forming process, which leads to a decrease in yield, and a stress failure occurs during actual use, thereby causing a serious failure.

More specifically, when a two-layer wiring made of Cu is formed on a test basis by the dual damascene method and connected by 2000 chain contact patterns,
Before performing passivation on the Cu surface, the yield of the pattern was examined when H ₂ annealing (350 ° C., 30 minutes) was used for surface purification after Cu polishing. The result is shown in FIG. Chain body shape is 0.3 (width: W)
In the case of × 20 (length: L) μm, the contact yield is 99% or more, but the chain body shape is 10%.
In the case of (width) × 20 (length) μm, it can be seen that the contact yield is reduced to 95% or less. This change is significant in reliability tests. FIG. 1 shows the result of a standing test at a temperature of 200 ° C. in the reliability test of the same pattern.
It is shown in FIG. In the former pattern, no deterioration was observed in the former pattern (not shown in the figure because plotting was not possible, whereas in the latter pattern, almost 100% wear failure was observed in 1000 hours or less. ing.

In this regard, in order to improve the filling of the wiring groove, a process of capping the upper layer by a CVD method or a method disclosed in
No. 30391 discloses a process for improving burying by high-pressure reflow, etc., all of which are intended to improve burying and electromigration during the process, and to improve defective via holes and via holes during the process. There is no report on stress migration.

As described above, conventionally, by forming a multilayer wiring by plating using a dual damascene method, a multilayer wiring having a low resistance can be formed in a short manufacturing process. However, serious problems such as a decrease in yield due to the above and a decrease in reliability due to stress migration during actual use are still unsolved.

Accordingly, the present invention greatly improves the yield in the formation process and the reliability during actual use when forming a low-resistance multilayer wiring in a short manufacturing process by applying a plating method to a damascene method. An object is to provide a method for forming a wiring and a method for manufacturing a semiconductor device including the wiring.

[0009]

The present invention has the following aspects to solve the above-mentioned problems.

A first aspect is a method for forming a wiring,
Forming a predetermined wiring groove in a first insulating film formed on an upper layer of a semiconductor substrate; forming a metal film by plating so as to fill the wiring groove; polishing the metal film to form the wiring groove; Forming a wiring while leaving the metal film so as to fill only the inside of the wiring, and forming a second insulating film on at least the wiring, and forming a predetermined film on the metal film immediately after the formation of the metal film. The method is characterized in that a heat treatment is performed at a temperature, and processing temperatures in various steps after the formation of the wiring, including a formation temperature of the second insulating film, are controlled to a predetermined low temperature or lower.

[0011] In the first aspect, the predetermined temperature of the heat treatment immediately after the formation of the metal film is set to 80 ° C to 2 ° C.
Preferably, the temperature is in the range of 00 ° C.

In the first aspect, it is preferable that the processing temperature in the various steps after the formation of the wiring is 400 ° C. or less.

In the first aspect, when forming the wiring as a multi-layer wiring, after forming the wiring through a series of processes including at least the above-described steps, the wiring is electrically connected to the formed wiring through an opening. It is preferable that the above-described series of processes is repeated a predetermined number of times so as to form a multi-layer wiring.

According to a second aspect, there is provided a method of forming a semiconductor device, wherein a wiring formed on a semiconductor element is formed according to the first aspect.

[0015]

According to the present invention, when a wiring is formed by applying a plating method to a damascene method, a low-temperature heat treatment is performed immediately after the formation of a metal film as a wiring material, and in addition, a metal film is left only in the wiring groove. Various steps including a step of forming an interlayer insulating film after polishing for forming wiring are performed at a predetermined low temperature. Here, when the various steps after the formation of the wiring are performed at a predetermined low temperature by omitting the low-temperature heat treatment step,
Although the yield of wiring during manufacturing is improved, relaxation of stress migration and the like during actual use is not observed. Therefore, by using the low-temperature heat treatment step and the low-temperature control in the various steps after the formation of the wiring as described above, the amount of stress caused by the various heat treatments is alleviated, and the formation of voids and a decrease in volume in the wiring are reduced. It is suppressed and a great improvement in reliability is realized.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings.

(Functions According to Main Configuration of the Present Embodiment) First, among the steps constituting the wiring forming method of the present invention,
A description will be given of a function of a process which is a main feature of the present invention.

In the present embodiment, a method of forming a multilayer wiring by applying a plating method to a so-called dual damascene method is disclosed as a main configuration. In this example, for example, referring to FIGS. 2 to 8, the via hole 30 is formed on the first wiring 23 formed by filling the first wiring groove 19 with the plated Cu film 22 via the via hole 30. Plating Cu film 35 in second wiring groove 33
Is formed to form a second wiring 36.

Here, the main configuration of the present embodiment is that a low-temperature annealing treatment is performed immediately after the plating metal films (Cu films 22 and 35) to be the material films of the first and second wirings 23 and 36 are formed. (Hereinafter referred to as condition 1), and the processing temperature of the H ₂ plasma processing after forming the first and second wirings 23 and 36 by CMP and the subsequent processing temperature of various processes including the interlayer insulating films 25 and 38 are set to predetermined values. (Hereinafter referred to as condition 2).

-Function of Condition 1- The function of Condition 1 will be described below with quantitative consideration. FIG. 1 is a characteristic diagram showing a stress change measured by changing a heating temperature of a plated Cu film. Temperature on x-axis, y
The axis shows stress. The directions of temperature rise and temperature decrease are indicated by arrows.

FIG. 1A shows a change in stress when the temperature is raised to 120 ° C. and returned to room temperature after Cu plating, and FIG. 1B shows the maximum temperature during the process. The change in stress when the temperature was changed to ° C. and returned to room temperature is shown. The figure shows the presence / absence of condition 1 (anneal after plating) shown in this example. In the process of raising the temperature from room temperature to 420 ° C., stress changes are observed up to 200 ° C. due to diffusion creep in accordance with thermal expansion.
There is a decrease where stress is relieved due to the rapid diffusion of u. Here, the generated relaxation is maintained even when the temperature is returned to room temperature, and the opposite stress occurs at room temperature.

The Cu wiring is subjected to thermal stress as shown in FIG. 1B due to the heat treatment required for growing the insulating film. The change in the Cu structure due to thermal stress and the occurrence of voids and volume reduction inside the Cu wiring are driving forces for forming voids in the wiring and via holes.

As shown in FIG. 1 (a), when heat treatment is performed at a temperature of 200 ° C. or less at which rapid diffusion of Cu into the Cu film occurs immediately after the deposition of the plated Cu film, the inside of the wiring groove by the damascene method is formed. While Cu expands, Cu grain growth and void precipitation are promoted. Thereafter, when the temperature returns to room temperature, densification of Cu and relaxation of stress have occurred.
Here, the portion of the CMP margin shrinks, but the volume inside the wiring groove after the polishing is maintained.

As shown in FIG. 1A, the Cu film after Cu plating is -4.0 × 10 ⁹ dyn / cm by heat treatment.
^The stress increases in the negative direction (thermal expansion) up to about ² or more, but the stress increases (shrinks in volume) in the positive direction by about 1.0 × 10 ⁹ dyn / cm ^{2 in the} process of lowering the temperature. This change suggests that: At the stage where void precipitation and crystal grain growth are performed while Cu is expanded at 120 ° C., Cu
The adhesion between the metal and the barrier metal is well maintained. Thereafter, in the process of returning to room temperature, a stress change occurs due to the contraction of the volume.

In the actual multi-layer wiring formation process, it is necessary to consider the influence of the heat treatment during the growth of the insulating film and the like thereafter. 200 immediately after Cu plating under condition 1
If the heat treatment is not performed at a temperature of 400 ° C. or less, the stress changes to about −5.0 × 10 ⁹ dyn / cm ² during the process of raising the temperature to 400 ° C. When the temperature rises to 200 ° C, Cu
The rapid diffusion causes stress relief. In this process, disconnection occurs inside the via hole due to precipitation of voids. By performing the heat treatment immediately after the plating Cu at a low temperature, the change in the amount of stress due to the subsequent heat treatment is reduced, as shown in FIG. It can be seen that shrinkage hardly occurs.

Even when left at room temperature after Cu plating,
It is known that grain growth is observed, but in this case, no effect of suppressing void formation is observed. This is considered to be due to the fact that densification that causes a stress change when heat treatment is performed at 120 ° C. does not occur as described above.

From the above considerations, it is understood that the change in the amount of stress is reduced by the heat treatment immediately after the formation of the Cu plating film under the condition 1, and the reliability in actual use can be improved. In this case, as the appropriate temperature range for the heat treatment, a change in stress due to shrinkage when returning to room temperature is observed.
The temperature is preferably not lower than 200 ° C. and not higher than 200 ° C. at which rapid diffusion does not occur, and is preferably performed in a short time of about 1 minute in consideration of suppression of stress change.

-Function of Condition 2- Condition 2 complements the function of Condition 1 so to speak.
From the consideration of the condition 1, if various processing temperatures are controlled to 400 ° C. or less in various heat treatments typified by annealing necessary for forming an interlayer insulating film after forming a wiring by CMP of a Cu plating film, a change in the amount of stress is reduced. It is suggested to be mitigated. In addition, in this example, for example, in FIGS. 2 to 8, the process for purifying the Cu surface of the first and second wirings 23 and 36 is effective when a process having a large thermal budget such as furnace annealing is performed. It is desirable to avoid it as it will decrease. However, it is desirable that the final annealing for removing the etching damage be performed at an appropriate temperature and time at the end of the process to reduce the thermal budget in each step of forming the multilayer wiring.

-Relationship between Condition 1 and Condition 2- An experiment was conducted in which only the condition 2 was added to the method of forming a Cu multilayer wiring in which plating was applied to the conventional dual damascene method. That is, the annealing temperature after the formation of the interlayer insulating film is lowered without performing the annealing after the wiring formation by CMP (all 400
When the multilayer wiring was formed and the yield at the time of formation and the reliability at the time of actual use were examined, the yield was improved, but the reliability was not recovered.

Then, when an experiment was conducted in which both the condition 1 and the condition 2 were added to the conventional method of forming a Cu multilayer wiring, it was found that the reliability was greatly recovered in addition to the improvement of the yield.

From these facts, it can be understood that both of the conditions 1 and 2 make it possible to form a low-resistance multilayer wiring in a short manufacturing process while securing high yield and reliability.

(Method of Forming Multilayer Wiring) Next, a method of forming a multilayer wiring forming the main structure of the present invention satisfying the above conditions 1 and 2 will be described. 2 to 8 show multilayer wiring (here, two layers) by applying a plating method to a dual damascene method.
FIG. 4 is a schematic cross-sectional view sequentially showing a step of forming a substrate.

First, as shown in FIG. 2A, after an interlayer insulating film 11 is deposited and formed so as to cover a semiconductor substrate (not shown), a via hole 12 communicating with a lower wiring is formed in the interlayer insulating film 11. Form. Next, T is applied to cover the inner wall of the via hole 12.
A base film 13 of iN or the like is formed, and a W film is deposited to a thickness to fill the via hole 12, and this W film is subjected to chemical mechanical polishing (C
MP) to form a W plug 14 in which only the via hole 12 is filled with W.

Subsequently, as shown in FIG.
Si on the edge film 11 and the W plug 14 _ThreeN_FourThe thickness of the film 15
It is formed to about 30 nm. Next, Si_ThreeN_FourOn the membrane 15
Interlayer insulation film made of FSG (fluoro-silicate glass)
16 is deposited to a film thickness of about 500 nm,
Forming an anti-reflection film 17 for lithographic exposure
You.

Subsequently, as shown in FIG. 2C, a photoresist 18 is applied, and the photoresist 18 is processed by photolithography to form a wiring groove pattern 18a opened on each W plug 14. Next, using the photoresist 18 as a mask and the Si ₃ N ₄ film 15 as an etching stopper, the anti-reflection film 17 and the interlayer insulating film 1 are used.
6 is dry-etched.

Subsequently, as shown in FIG. 2D, after the photoresist 18 is removed by an ashing process or the like, the photoresist 18 is further removed.
The ₃ N ₄ film 15 is dry-etched to expose the surface of the interlayer insulating film 11 and the W plug 14, a first wiring groove 19 following the wiring trench pattern.

Subsequently, as shown in FIG. 3A, the semiconductor substrate is subjected to a plasma treatment containing H ₂ , here an NH ₃ plasma treatment, to clean the inside of the first wiring groove 19. Here, as the plasma treatment, H ₃ gas is used instead of NH ₃ gas.
₂ gas, N ₂ -H ₂ mixture gas, may be used H ₂ -Ar mixed gas.

Subsequently, as shown in FIG. 3B, reverse sputtering is performed as RF processing to a thickness of about 10 nm in terms of the thickness of the thermal oxide film to wash the interlayer insulating film 11, and then the barrier metal film 20 made of TaN is formed. And a Cu film 21 as a seed metal film is continuously deposited and formed in a vacuum by a clustering apparatus having a thickness of about 200 nm. Here, it is desirable that the RF treatment and the formation of the barrier metal film 20 and the Cu film 21 be performed continuously in a vacuum.

Subsequently, as shown in FIG. 3C, the Cu film 2 is buried in the first wiring groove 19 by plating using the barrier metal 20 as an electrode.
Form 2

Subsequently, as shown in FIG. 3D, immediately after the plating of the Cu film 22, a low temperature of 80 ° C. to 200 ° C., here 150 ° C., on a hot plate filled with a nitrogen atmosphere.
Heat treatment at 1 ° C. for 1 minute. This process promotes a change in stress of the Cu film 22 and the growth of Cu grains as described later. Here, as the heat treatment, in addition to the baking method using a hot plate, a CVD apparatus, a lamp, a laser, or the like may be used.

Subsequently, as shown in FIG.
To separate the Cu film 22 by the CMP method,
The u film 22 (21) and the barrier metal film 20 are polished to
After leaving the Cu film 22 only in the wiring groove 19 of FIG.
Then, the first wiring 23 is formed by cleaning by a heat treatment. Next
And H_TwoPlasma treatment, here NH 3_Threeplasma
The treatment is performed at a low temperature of 400 ° C. or less for a short time, here, 350 ° C.
For 30 seconds to clean the exposed surface of the first wiring 23
-Reduction to remove the surface oxide film. Where the plasm
NH treatment_ThreeH instead of gas_TwoGas, N_Two−
H_TwoMixed gas, H _Two-Ar mixed gas or the like may be used.

Subsequently, as shown in FIG. 4 (b), NH ₃
The Si ₃ N ₄ film 2 serving as a diffusion barrier (passivation) on the surface of the first wiring 23 at a low temperature of 400 ° C. or lower continuous with the plasma processing in the same chamber as the plasma processing.
4 is deposited to a thickness of about 70 nm. Next, Si ₃ N
₄ Interlayer insulating film 25 made of FSG on film 24, Si ₃ N
₄ film 26, an interlayer insulating film 27 of FSG having a thickness of 700
In this order, an anti-reflection film 28 is formed.

Subsequently, as shown in FIG. 4C, a photoresist 29 is applied, and the photoresist 29 is processed by photolithography to form an opening pattern 29a opened on each first wiring 23. I do.

Subsequently, as shown in FIG. 5A, using the photoresist 29 as a mask, the Si ₃ N ₄ film 24 as an etching stopper, the anti-reflection film 28 and the interlayer insulating film 2.
7. Dry etching is performed on the Si ₃ N ₄ film 26 and the interlayer insulating film 25 to form a via hole 30 following the shape of the opening pattern 29a. Next, the photoresist 29 is removed by an ashing process or the like.

Subsequently, as shown in FIG. 5B, a protective material 3 made of a resist or the like is provided below the formed via hole 30 as a treatment for preventing surface oxidation of the first wiring 23.
Embed 1

Subsequently, as shown in FIG.
A resist 32 is applied, and photolithography is performed.
The photoresist 32 is processed and an opening is formed on each via hole 30.
The wiring layer pattern 32a is formed. Next, the photo cashier
With the strike 32 as a mask, Si _ThreeN_FourEtch film 26
Anti-reflection film 28 and interlayer insulating film 27 as stoppers
Is dry-etched to obtain the shape of the wiring layer pattern 32a.
A second wiring groove 33 is formed according to the above.

Subsequently, as shown in FIG. 6A, after the photoresist 32 and the protective material 31 are removed by ashing, etc., the Si ₃ N ₄ film 24 remaining at the bottom of the via hole 30 and the second The Si ₃ N ₄ film 26 remaining at the bottom of the wiring groove 33 is entirely removed by dry etching. At this time, the second wiring groove 33 and the via hole 30 are integrated.

Subsequently, as shown in FIG._TwoTo
Including plasma treatment, here NH_Three40 plasma treatments
Short time at a low temperature of 0 ° C or less, here at 350 ° C for 30 seconds
Of the first wiring 23 exposed at the bottom of the via hole 30.
Wash the surface. Here, NH3 is used as the plasma processing.
_ThreeH instead of gas_TwoGas, N_Two-H_TwoMixed gas, H _Two
-Ar mixed gas or the like may be used.

Subsequently, as shown in FIG.
A barrier metal film 34 of about 25 nm in thickness, and a Cu film (not shown) as a seed metal film having a thickness of 200 n.
It is continuously deposited and formed in a vacuum of about m by a sputtering apparatus. Next, using the barrier metal 34 as an electrode, a Cu film 35 is formed by plating so as to fill the second wiring groove 33 and the via hole 30 to a thickness of about 1 μm here. Next, a heat treatment is performed at a low temperature of 200 ° C. or less, here 150 ° C., for 1 minute on a hot plate filled with a nitrogen atmosphere immediately after the formation of the plating of the Cu film 35. With this process,
As described later, the change in stress of the Cu film 35 and the growth of Cu grains are promoted.

Subsequently, as shown in FIG. 7B, in order to separate the Cu film 22 by the damascene method, the C
After polishing the u film 35 and the barrier metal film 34 to leave the Cu film 35 only in the second wiring groove 35 and the via hole 30,
The second wiring 36 is formed by cleaning by wet processing.

Subsequently, as shown in FIG. 8A, a plasma process including H ₂ , here, an NH ₃ plasma process is performed for 40 hours.
The process is performed at a low temperature of 0 ° C. or less for a short time, here at 350 ° C. for 30 seconds, and the exposed surface of the second wiring 36 is washed to remove the surface oxide film. Here, as the plasma processing, N
H ₂ gas in place of H ₃ gas, N ₂ -H ₂ mixture gas, H
_{A 2-} Ar mixed gas may be used. Next, the Si ₃ N ₄ film 37 serving as a diffusion barrier (passivation) on the surface of the second wiring 36 is formed to a thickness of 70 nm in the same chamber as the NH ₃ plasma treatment at a low temperature of 400 ° C. or lower, which is continuous with the treatment. Deposits are formed to an extent. Further, a silicon oxide film (SiO film) 38 and a Si ₃ N ₄ film 39 are sequentially formed to have a thickness of about 400 nm and a thickness of about 300 nm as a cover film.

Subsequently, as shown in FIG.
Perform photolithography to form electrodes and
Si with photoresist as mask_ThreeN_FourFilm 37 and silicon
The oxide film 38 is dry-etched. Next, the photo cashier
After removing the strike, the Si_ThreeN _FourDry etchin for membrane 37
To expose the surface of the second wiring 36,_TwoN including
_TwoIn the atmosphere at a low temperature of 400 ° C or less, the final
An annealing process is performed. Thereby, the opening 4 of the pad electrode is formed.
0 is formed.

Thereafter, a multilayer wiring is completed through formation of a pad electrode for the opening 40 and other post-processes.

According to the method of forming a multilayer wiring of this embodiment, it is possible to suppress a decrease in yield due to disconnection of wiring after the completion of the multilayer process, to suppress the occurrence rate of defects due to stress migration and the like, and to significantly improve reliability. Contribute to improvement. The structure of the chain contact pattern (L
/ W = 10/20 μm, via hole diameter = 0.28 μm) In a monitor with 2000 chains, the yield of via holes after completion of the multilayer process is almost 100% between this embodiment and the conventional forming method. Yield. In addition, according to the evaluation result of stress migration performed under the acceleration condition of 200 ° C. using the same pattern, the one without heating after plating has a life of one year or less, but the method of this example has a sufficient life ( At least 10 under actual use conditions
Years).

As described above, according to this example, it is possible to form a low-resistance multilayer wiring by a short-time manufacturing process while securing high yield and reliability.

(Semiconductor Device with Multi-Layer Wiring) Specifically, FIG. 9 shows an example in which a semiconductor element, here a MOS transistor, is formed on a semiconductor substrate, and then a multi-layer wiring is formed by the above-described steps.

In the MOS transistor, a thin silicon oxide film and a polycrystalline silicon film having a predetermined thickness are formed on the silicon semiconductor substrate 1 and are patterned by photolithography and subsequent dry etching to form a gate. An insulating film 2 and a gate electrode 3 are formed. Subsequently, using the gate electrode 3 (or a photoresist or the like) as a mask, an impurity of a conductivity type opposite to that of the semiconductor substrate 1 is ion-implanted, and an annealing process is performed to form the source / drain 4. Then, a W plug 14 is formed so as to be connected to each source / drain 4, and a multilayer wiring is formed by the above-described steps.

According to this example, a high-resistance semiconductor device, which could not be obtained conventionally, can be formed because a low-resistance multilayer wiring can be formed in a short manufacturing process while securing a high yield and reliability. It can be realized.

The following embodiments also constitute the present invention.

Embodiment 1 is a method for forming a wiring, wherein at least a part of the wiring surface, which is exposed, is subjected to a plasma treatment with a mixed gas containing H ₂ to purify the wiring.

A second aspect is the method for forming a wiring according to the first aspect, wherein a silicon nitride film and the interlayer insulating film are sequentially formed on the wiring by plasma treatment following the purification. .

Embodiment 3 is a method of manufacturing a semiconductor device, in which the wiring is formed through a series of processes including at least the above-described steps, and is electrically connected to the formed wiring through an opening. As described above, the series of processes is repeated a predetermined number of times to form a multilayer wiring.

[0063]

According to the present invention, it is possible to form low-resistance wirings, particularly multilayer wirings, in a short manufacturing process while securing high yield and reliability. A high-performance semiconductor device can be realized.

[Brief description of the drawings]

FIG. 1 is a characteristic diagram showing a stress change due to a heat treatment after a Cu plating film is formed.

FIG. 2 is a schematic cross-sectional view showing a method for forming a multilayer wiring according to the present embodiment in the order of steps;

FIG. 3 is a schematic cross-sectional view showing a method for forming the multilayer wiring according to the present embodiment in the order of steps, following FIG. 2;

FIG. 4 is a schematic cross-sectional view showing the method for forming the multilayer wiring according to the present embodiment in the order of steps, following FIG. 3;

FIG. 5 is a schematic cross-sectional view showing the method for forming the multilayer wiring according to the present embodiment in the order of steps, following FIG. 4;

FIG. 6 is a schematic cross-sectional view showing a method for forming the multilayer wiring according to the present embodiment in the order of steps, following FIG. 5;

FIG. 7 is a schematic cross-sectional view showing the method for forming the multilayer wiring according to the present embodiment in the order of steps, following FIG. 6;

8 is a schematic sectional view, following FIG. 7, showing the method for forming the multilayer wiring according to the present embodiment in the order of steps; FIG.

FIG. 9 is a schematic sectional view showing a MOS transistor manufactured according to the present embodiment.

FIG. 10 is a characteristic diagram showing a yield of chain contacts by a conventional wiring forming method.

FIG. 11 is a characteristic diagram showing a Weibull plot of a chain contact according to a conventional wiring forming method.

[Explanation of symbols]

Reference Signs List 1 silicon semiconductor substrate 2 gate insulating film 3 gate electrode 4 source / drain 11, 16, 25, 27, 38 interlayer insulating film 14 W plug 15, 24, 26, 37, 39 Si ₃ N ₄ film 19 first wiring groove 20, 34 Barrier metal film 21 Seed Cu film 22, 35 Cu film 23 First wiring 30 Via hole 31 Protective material 33 Second wiring groove 36 Second wiring

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Tsutomu Hosoda 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa F-term within Fujitsu Limited (reference) 5F033 HH11 HH32 JJ19 JJ33 KK01 KK11 KK32 MM02 MM12 MM13 NN06 NN07 PP15 PP27 PP33 QQ09 QQ10 QQ11 QQ21 QQ25 QQ37 QQ48 QQ73 QQ92 QQ98 RR06 RR11 TT02 VV16 WW03 XX02 XX06

Claims (5)

[Claims] A step of forming a predetermined wiring groove in a first insulating film formed on an upper layer of a semiconductor substrate; a step of plating a metal film so as to fill the wiring groove; and a step of polishing the metal film. And forming a wiring while leaving the metal film so as to fill only the wiring groove; and at least forming a second insulating film on the wiring, Performing a heat treatment at a predetermined temperature on the metal film and controlling processing temperatures of various steps after forming the wiring including a formation temperature of the second insulating film to a predetermined low temperature or less. Method. 2. The method according to claim 1, wherein the predetermined temperature of the heat treatment immediately after the formation of the metal film is set to a temperature in a range of 80 ° C. to 200 ° C. 3. The processing temperature of each step after forming the wiring is set at 4
2. The method for forming a wiring according to claim 1, wherein the temperature is set to not more than 00.degree. 4. After forming the wiring through a series of processes including at least the above steps, the series of processes is repeated a predetermined number of times so as to be electrically connected to the formed wiring through an opening. 2. The method according to claim 1, wherein a multilayer wiring is formed. 5. A method for manufacturing a semiconductor device, comprising: forming a predetermined semiconductor element on a semiconductor substrate; and forming a wiring on an upper layer of the semiconductor element so as to be electrically connected to the semiconductor element. A step of forming a predetermined wiring groove in a first insulating film formed on an upper layer of the semiconductor element; a step of plating and forming a low-resistance metal film so as to fill the wiring groove; Polishing a film to form a wiring while leaving the metal film so as to fill only the wiring groove; and forming at least a second insulating film on the wiring, Immediately after the formation, the metal film is subjected to a heat treatment at a predetermined temperature, and the processing temperatures of various steps after the formation of the wiring, including the formation temperature of the second insulating film, are controlled to a predetermined low temperature or lower. Manufacturing of semiconductor devices Construction method.