JP2010165983A - Light-emitting chip integrated device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent generation of a cavity in an inside when forming an electrode for connecting light-emitting chips in series. <P>SOLUTION: A plurality of thin light-emitting chips 13 each of which is configured by laminating an n-type compound semiconductor layer 16, an active layer 17 and a p-type compound semiconductor layer 18 are bonded on a wafer 11 through lower surface wiring 12 by using the p-type compound semiconductor layers 18 as bonding surfaces. The n-type compound semiconductor layer 16 of either one of the light-emitting chips which are adjacent to each other and the p-type compound semiconductor layer 18 of the other light-emitting chip 13 are electrically connected to each other in series through upper surface wiring 15, vertical wiring 14 and the lower surface wiring 12. At this time, the vertical wiring 14 is configured so as to include the n-type compound semiconductor layer 16 existing between the adjacent light-emitting chips 13. Thus, when forming the vertical wiring 14 for connecting the adjacent light-emitting chips 13 in series, depth for burying a metal is made small to prevent the generation of a cavity in the inside. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a light-emitting chip integrated device in which a plurality of light-emitting chips are integrated on a wafer, and the light-emitting chips are connected in series and parallel, and can be used for illumination, for example, based on a 100V commercial AC power supply. The present invention relates to a light emitting chip integrated device and a method for manufacturing the same.

  In recent years, with the advent of long-life blue light emitting diode (LED) chips, LED chips have begun to be used in place of light sources for liquid crystal displays or electric lamps and fluorescent tubes. In these applications, since the light output of a single LED chip is small, it is common to provide a plurality of LED chips. In that case, these LED chips are connected in series to form an LED chip array, and the plurality of LED chip arrays are connected in parallel, so-called series-parallel connection.

  A semiconductor light emitting device disclosed in Japanese Patent Application Laid-Open No. 2007-157969 (Patent Document 1) is an example in which a plurality of light emitting chips are formed on a wafer. FIG. 8 shows a cross-sectional structure of the conventional semiconductor light emitting device disclosed in Patent Document 1.

  In FIG. 8, 1 is an insulating substrate made of sapphire, on which an n-type layer 2c, an active layer 2d, and a barrier layer composed of a low-temperature buffer layer 2a, a high-temperature buffer layer 2b, a contact layer, a barrier layer, and the like. In addition, a semiconductor multilayer portion 2 is formed which is formed of an epitaxially grown layer (hereinafter, abbreviated as an epi layer) formed by sequentially laminating a p-type layer 2e composed of a contact layer and the like. A translucent conductive layer 3 is formed on the entire surface of the p-type layer 2e and is in ohmic contact with the p-type layer 2e.

  The translucent conductive layer 3 and the epi layer 2 are etched up to a part of the n-type layer 2 c to form electrode grooves 4. An insulator is formed on the side surfaces of the electrode grooves 4 and the translucent conductive layer 3. An insulating electrode groove is formed in the insulator layer 5 formed on the side surface of the electrode groove 4, and an n-side electrode 6a is formed of metal in the insulating electrode groove. A p-side electrode 6 b is formed on a part of the translucent conductive layer 3. In addition, in order to isolate | separate each light emitting chip formed in this way, the isolation | separation groove | channel 2f is formed and the insulator layer 5 is embedded.

  Then, the n-side electrode 6a in the light-emitting chip A located between the arbitrary separation groove 2f and the separation groove 2f adjacent thereto and the p-side electrode 6b in the light-emitting chip B adjacent to the light-emitting chip A are wiring films. 7 are connected in series.

  However, the conventional semiconductor light emitting device disclosed in Patent Document 1 has the following problems.

  That is, generally, there are a sputtering method, a vapor deposition method, and the like as a metal deposition method for forming an electrode of a light emitting chip. When the n-side electrode 6a is formed in the insulating electrode groove in the electrode groove 4 by using these methods, metal deposition proceeds excessively on the edge portion of the insulating electrode groove, and the insulating electrode There arises a problem that the n-side electrode 6a is blocked while leaving a cavity inside the groove. In order to promote the metal intrusion into the insulating electrode groove, it is necessary to reduce the aspect ratio (vertical / lateral ratio) of the insulating electrode groove. However, when the aspect ratio is reduced, there is a problem that the light emitting area in the light emitting chip A becomes relatively small, and the light emission intensity of the entire light emitting device is lowered.

  Further, as shown in FIG. 8, when the outermost layer of the epi layer 2 in the light emitting chip A is the p-type layer 2e, the light emitted from the light emitting chip A accounts for half of the light emitted from the side surface. The reason is that most of the light incident on the insulating substrate 1 from the active layer 2d is totally reflected at the interface between the insulating substrate 1 and the low-temperature buffer layer 2a, proceeds in the lateral direction, and is emitted from the side surface of the light emitting chip A. Because. Then, the light emitted from the light emitting chip A is absorbed mainly by the active layer 2d of the adjacent light emitting chip B, and there is a problem that the light extraction efficiency of the light emitting device is greatly reduced.

  Furthermore, in general, a sapphire substrate is used as the insulating substrate 1 in order to obtain an epi layer with good crystallinity. However, since the sapphire substrate has a high thermal resistance, there is a problem that the heat dissipation of the entire light emitting device to be obtained is not excellent.

JP 2007-157969 A

  Accordingly, an object of the present invention is to provide a light emitting chip integrated device capable of preventing the electrode from being blocked by an electrode while leaving a cavity in the groove when the electrode is formed in the groove for forming the electrode, and a method for manufacturing the same. Is to provide.

In order to solve the above problems, a light-emitting chip integrated device of the present invention includes:
a light-emitting chip configured by sequentially stacking a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer;
A plurality of the light emitting chips are bonded using the surface of the p-type compound semiconductor layer of each light emitting chip as a bonding surface;
A lower surface wiring interposed between the wafer and the plurality of light emitting chips bonded to each other;
A conductive path that electrically connects the n-type compound semiconductor layer in any one of the two light emitting chips adjacent to each other and the p-type compound semiconductor layer in the other;
The conductive path is
A top surface wiring connected to the n-type compound semiconductor layer in the one light emitting chip;
The lower surface wiring connected to the p-type compound semiconductor layer in the other light emitting chip;
An n-type compound semiconductor layer that is connected to the upper surface wiring and the lower surface wiring and is formed at the same time as the n-type compound semiconductor layer of the light emitting chip in a region between the two adjacent light emitting chips; It is configured to include upper and lower wiring including conductor metal,
A plurality of the light emitting chips bonded to the wafer via the lower surface wirings are electrically connected in series through the conductive path.

  Here, first, main terms will be described.

  The “wafer” means a bonded substrate used for supporting the light emitting chip and the lower surface wiring, unlike the growth substrate used for growing the light emitting chip and the lower surface wiring.

  The “light-emitting chip” means a light-emitting chip having a thickness of about 10 μm obtained by peeling only the epitaxial growth layer from the growth substrate. Note that the types of the light emitting chip include a light emitting diode (LED).

  The “conductive path” is connected to one of the two light emitting chips adjacent to each other and is connected to one of the light emitting chips, and is an upper surface wiring made of a conductive metal, and n is one component of the epitaxial growth layer. The upper and lower wirings including the type compound semiconductor layer and the lower surface wiring made of a metal material and connected to the other light emitting chip mean a continuous structure.

  According to the above configuration, the upper and lower wirings constituting the conductive path that electrically connects the two light emitting chips adjacent to each other bonded to the wafer via the lower surface wiring are the upper surface wiring and the lower surface wiring. And an n-type compound semiconductor layer formed in the region between the two adjacent light-emitting chips and the n-type compound semiconductor layer of the light-emitting chip, and a conductive metal. Has been. Therefore, when the upper and lower wirings are formed through the p-type compound semiconductor layer, the active layer, and the n-type compound semiconductor layer in the region between the two adjacent light-emitting chips, n of the light-emitting chip is formed. The conductive metal can be embedded in a shallower depth by using the n-type compound semiconductor layer formed at the same time as the n-type compound semiconductor layer, and is formed through the p-type compound semiconductor layer and the active layer. When the conductor metal is introduced into the groove for forming the conductor metal by sputtering or vapor deposition, the groove is not blocked by the conductor metal while leaving a cavity inside the groove. it can.

  Further, each of the plurality of light emitting chips electrically connected in series by the conductive path is configured by sequentially stacking a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer, The n-type compound semiconductor layer that does not become the bonding surface is located in the outermost layer. Therefore, most of the light incident on the n-type compound semiconductor layer side from the active layer is emitted from the surface of the n-type compound semiconductor layer. As a result, it is possible to prevent the light extraction efficiency from being reduced due to light absorption by the adjacent light emitting chip.

In the light emitting chip integrated device according to the embodiment,
The upper and lower wiring is
Regarding a stacked structure of the n-type compound semiconductor layer, the active layer, and the p-type compound semiconductor layer, which are in a region between the light-emitting chips adjacent to each other and separated from each light-emitting chip by an insulator,
The n-type compound semiconductor layer;
The active metal layer laminated below the n-type compound semiconductor layer, and the conductive metal embedded so as to penetrate the p-type compound semiconductor layer and reach the n-type compound semiconductor layer. ing.

  According to this embodiment, the upper and lower wirings are in a region between the light emitting chips, and are constituted by the n-type compound semiconductor layer and the conductor metal formed when the light emitting chips are formed. ing. Therefore, the depth of the groove for forming the conductive metal can be reduced by the thickness of the n-type compound semiconductor layer, and when the conductive metal is introduced into the groove by sputtering or vapor deposition, It is possible to promote the wrapping of the metal into the groove. As a result, it is possible to prevent the groove from being blocked by the conductor metal while leaving a cavity inside the groove.

In the light emitting chip integrated device according to the embodiment,
The upper and lower wiring is
The n-type compound semiconductor layer in a region between the light emitting chips adjacent to each other and separated from each light emitting chip by an insulator;
In the region between the light emitting chips adjacent to each other, stacked below the n-type compound semiconductor layer and electrically connected to the n-type compound semiconductor layer, and each light-emitting chip is an insulator. And the above-mentioned conductor metal separated by.

  According to this embodiment, the upper and lower wirings are in a region between the light emitting chips, and are constituted by the n-type compound semiconductor layer and the conductor metal formed when the light emitting chips are formed. ing. Therefore, the depth of the groove for forming the conductive metal can be reduced by the thickness of the n-type compound semiconductor layer, and when the conductive metal is introduced into the groove by sputtering or vapor deposition, It is possible to promote the wrapping of the metal into the groove. As a result, it is possible to prevent the groove from being blocked by the conductor metal while leaving a cavity inside the groove.

In the light emitting chip integrated device according to the embodiment,
The conductive metal is composed of a metal containing titanium and aluminum,
The conductive metal is laminated in the order of the titanium, the aluminum, and other metals from the n-type compound semiconductor layer side.

  According to this embodiment, the conductor metal constituting the upper and lower wirings is constituted by a laminated film in which titanium, aluminum and other metals are laminated in this order from the n-type compound semiconductor layer side. Therefore, when the titanium of the titanium layer diffuses into the n-type compound semiconductor layer, the thickness of the Schottky barrier can be reduced and the ohmic resistance can be lowered. As a result, the ohmic resistance between the n-type compound semiconductor layer and the conductive metal can be reduced, the electrical resistance of the conductive path can be reduced, and the power consumption of the light emitting chip integrated device can be reduced.

In the light emitting chip integrated device according to the embodiment,
The length of the conductive metal in the direction of the conductive path is 10 nm or more and 500 nm or less.

  According to this embodiment, the length of the conductor metal in the direction of the conductive path is set to 10 nm or more. Therefore, the conductor metal can be formed with high accuracy, good ohmic characteristics with the n-type compound semiconductor layer can be obtained, and the upper and lower wirings exhibiting good characteristics can be obtained. Furthermore, the length of the conductor metal in the direction of the conductive path is set to 500 nm or less. Therefore, in the region between the light emitting chips adjacent to each other, good embedding property in the active layer and the p-type compound semiconductor layer can be obtained.

In the light emitting chip integrated device according to the embodiment,
A translucent insulator is embedded between the upper and lower wirings and the light emitting chip adjacent to the upper and lower wirings.

  According to this embodiment, a translucent insulator is embedded between the upper and lower wirings and the light emitting chip. Therefore, the light emitted from the light emitting chip is not absorbed by the adjacent light emitting chip, and the light extraction efficiency of the light emitting chip integrated device can be maximized.

In addition, the method for manufacturing the light-emitting chip integrated device of the present invention includes:
A method of manufacturing the light emitting chip integrated device,
Sequentially forming an n-type compound semiconductor layer, an active layer, and a p-type compound semiconductor layer on a first substrate;
Removing a part of the p-type compound semiconductor layer and the active layer formed on the first substrate to form a plurality of recesses, and exposing the n-type compound semiconductor layer;
A conductor metal is formed on the p-type compound semiconductor layer on the first substrate, the insides of the plurality of recesses are filled with the conductor metal, and the conductor metal is electrically connected to the n-type compound semiconductor layer. Connecting to
Forming a lower surface wiring layer on the entire surface including the p-type compound semiconductor layer on the first substrate;
The first substrate on which the n-type compound semiconductor layer, the active layer, the p-type compound semiconductor layer, the conductor metal, and the lower surface wiring layer are formed on a second substrate is formed on the surface of the lower surface wiring layer. As a bonding surface, a step of bonding via a bonding layer;
Peeling the first substrate from the n-type compound semiconductor layer;
One side of each recess embedded with the conductor metal is removed until the lower surface wiring layer is exposed to form a first separation groove, while the other side is removed until the second substrate is exposed. Forming a second separation groove and separating into a plurality of light emitting chips including the n-type compound semiconductor layer, the active layer, and the p-type compound semiconductor layer;
Embedding an insulator in the first separation groove and the second separation groove;
The n-type compound semiconductor layer between the first separation groove and the second separation groove, and the light-emitting chip adjacent to the n-type compound semiconductor layer with the second separation groove interposed therebetween. forming an upper surface wiring for electrically connecting the n-type compound semiconductor layer,
The adjacent light emitting chips formed on the second substrate are electrically connected to the upper surface wiring between the upper surface wiring, the first separation groove, and the second separation groove. The n-type compound semiconductor layer connected, the conductor metal, and the lower wiring layer in contact with the conductor metal are electrically connected in series.

  According to the above configuration, the conductive path that electrically connects the adjacent light emitting chips formed on the second substrate in series is provided between the first separation groove and the second separation groove. And the p-type in the region between the n-type compound semiconductor layer formed when the light-emitting chip is formed, and the first separation groove and the second separation groove. A plurality of recesses formed by removing a part of the compound semiconductor layer and the active layer are embedded flat, and the conductive metal electrically connected to the n-type compound semiconductor layer, and the n-type compound The upper surface wiring electrically connected to the semiconductor layer and the lower surface wiring layer in contact with the conductor metal are included.

  Therefore, the depth of the recess can be reduced by the thickness of the n-type compound semiconductor layer, and when the conductor metal is introduced into the recess by a sputtering method, a vapor deposition method, or the like, Metal wrapping can be promoted. As a result, it is possible to prevent the groove from being blocked by the conductor metal while leaving a cavity inside the recess.

  Further, the first substrate for growing the light emitting chip and the second substrate for supporting the light emitting chip integrated device are different substrates. Therefore, by making the second substrate a substrate having a lower thermal resistance than the first substrate for obtaining an epitaxial layer with good crystallinity, the heat dissipation of the resulting light-emitting chip integrated device can be improved. It becomes possible.

  As is clear from the above, the light emitting chip integrated device of the present invention is configured by electrically connecting two light emitting chips adjacent to each other bonded to the wafer through the lower surface wiring by a conductive path. N is formed simultaneously with the n-type compound semiconductor layer of the light emitting chip in the region between the two light emitting chips adjacent to each other. Since the type compound semiconductor layer and the conductor metal are included, the upper and lower wirings are connected to the p-type compound semiconductor layer, the active layer, and the n-type compound semiconductor layer in a region between the two adjacent light emitting chips. When forming the conductive metal through the n-type compound semiconductor layer, the depth of embedding the conductor metal is increased by using the n-type compound semiconductor layer formed simultaneously with the n-type compound semiconductor layer of the light emitting chip. Can Kusuru. Therefore, in that case, when the conductor metal is introduced into the groove for forming the conductor metal formed through the p-type compound semiconductor layer and the active layer by sputtering, vapor deposition or the like, It is possible to prevent the groove from being blocked by the conductive metal while leaving a cavity inside.

  In the method for manufacturing a light-emitting chip integrated device according to the present invention, the conductive path for electrically connecting adjacent light-emitting chips formed on the second substrate in series is provided with the first separation groove and the second separation. An n-type compound semiconductor layer formed when forming the light emitting chip, and a region between the first separation groove and the second separation groove. A plurality of recesses formed by removing a part of the p-type compound semiconductor layer and the active layer are embedded flatly, and a conductive metal electrically connected to the n-type compound semiconductor layer, and the n-type compound Since the upper surface wiring electrically connected to the semiconductor layer and the lower surface wiring layer in contact with the conductor metal are included, the depth of the recess is set to the thickness of the n-type compound semiconductor layer. It can be made shallower. Therefore, when introducing the conductor metal into the recess by sputtering or vapor deposition, it is possible to promote the wrapping of the metal into the groove, and leave the cavity inside the recess. It is possible to prevent the groove from being blocked by metal.

  Further, the first substrate for growing the light emitting chip and the second substrate for supporting the light emitting chip integrated device are different substrates. Therefore, by making the second substrate a substrate having a lower thermal resistance than the first substrate for obtaining an epitaxial layer with good crystallinity, the heat dissipation of the resulting light-emitting chip integrated device can be improved. It becomes possible.

It is sectional drawing of the light emitting chip in the light emitting chip integrated device of this invention. 2 is a flowchart showing a method of manufacturing a light emitting chip integrated device having the light emitting chip shown in FIG. It is sectional drawing in each manufacturing process in the light emitting chip integrated device shown in FIG. FIG. 4 is a cross-sectional view in each manufacturing process following FIG. 3. It is sectional drawing in each manufacturing process following FIG. It is sectional drawing of the light emitting chip different from the light emitting chip shown in FIG. FIG. 7 is a cross-sectional view in each manufacturing process of the light-emitting chip integrated device shown in FIG. 6. It is sectional drawing in the conventional semiconductor light-emitting device.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

First Embodiment FIG. 1 is a cross-sectional view of a light emitting chip in a light emitting chip integrated device according to the present embodiment.

  The embodiment described below is the best mode for carrying out the present invention, and it is possible to take alternative forms by adding changes to the present embodiment. Further, the present invention is not intended to be limited to the present embodiment, and the present invention includes all modifications, equivalents, and alternatives included in the scope defined by the claims.

  In FIG. 1, reference numeral 11 denotes a wafer. For example, aluminum nitride (AlN) is used as a nonconductive substrate. A lower surface wiring 12 is formed on the wafer 11, and a GaN-based thin light emitting chip 13 is further provided thereon. The light emitting chips 13 adjacent to each other are electrically connected in series by a conductive path in which the lower surface wiring 12, the upper and lower wirings 14, and the upper surface wiring 15 are connected.

The wafer 11 that can be used in the present invention preferably has a low thermal resistance and a thermal expansion coefficient close to that of GaN, which is the base material of the light-emitting chip 13. Therefore, in addition to the above aluminum nitride (AlN), for example, gallium phosphide (GaP), germanium (Ge), gallium nitride (GaN), silicon (Si), silicon carbide (SiC), indium phosphide (InP), sapphire (Al ₂ O ₃ ) and zinc oxide (ZnO) can be used.

  The thickness of the wafer 11 may be 50 μm to 2 mm from the viewpoint of supporting the sample, and more preferably 50 μm to 500 μm from the viewpoint of heat dissipation.

  The wafer 11 is not particularly limited to the non-conductive material as long as the outermost surface is an insulating layer. For example, a substrate having an insulating film formed on the outermost surface may be used. That is, when Si, SiC, or the like is used for the substrate, the Si, SiC oxide or the like may be formed on the outermost surface.

  As the base material of the light emitting chip 13, AlGaInP, GaP, GaN, SiC, ZnO, and other compound semiconductors can be used.

  The light emitting chip 13 is a thin film having a thickness of several tens of μm formed by peeling an epitaxial growth layer (epi layer) crystal-grown on a growth substrate, which will be described in detail later, from the growth substrate. The light emitting chip 13 is formed by sequentially laminating an n-type compound semiconductor layer 16, an active layer 17, and a p-type compound semiconductor layer 18 on the growth substrate.

  Among them, the n-type compound semiconductor layer 16 includes, for example, a plurality of layers having different compositions and dopant concentrations, such as an n-type region designed to improve the optical characteristics and electrical characteristics of the light emitting region in the active layer 17. Contains. Here, as the base material of the n-type compound semiconductor layer 16, GaN, AlGaN, InGaN, or the like can be used.

  On the n-type compound semiconductor layer 16 formed on the growth substrate, an active layer 17 having the light emitting region is formed. The light emitting region may include one or more light emitting layers. When the light emitting region is a quantum well light emitting region, the light emitting region generally includes a plurality of quantum well light emitting layers separated by a barrier layer. It is out. Note that GaN, AlGaN, InGaN, or the like can be used as the base material of the active layer 17, and Si or the like can be used as the dopant.

  A p-type compound semiconductor layer 18 is formed on the active layer 17. Similar to the n-type compound semiconductor layer 16, the p-type compound semiconductor layer 18 includes a plurality of layers having different compositions and dopant concentrations. As the base material, GaN, AlGaN, InGaN, or the like can be used, and Mg or the like can be used as the dopant.

  As described above, the growth substrate on which the epi layer formed by sequentially stacking the n-type compound semiconductor layer 16, the active layer 17, and the p-type compound semiconductor layer 18 is separated and removed by laser separation or the like, and exposed. The n-type compound semiconductor layer 16 is thinned by inductively coupled plasma (IPC) or the like. Thereafter, the surface of the epi layer (that is, the surface on which the thinning process of the n-type compound semiconductor layer 16 has been performed) is processed into an uneven shape by treating with an alkaline solution.

  Here, the reason for separating the growth substrate from the epi layer is that the light emitted from the active layer 17 is totally reflected at the interface between the growth substrate and the epi layer, and the light extraction efficiency is greatly reduced. Because. For example, when the growth substrate is sapphire and the epi layer is GaN, the respective refractive indexes are greatly different from 1.8 and 2.4. Therefore, when the growth substrate is not separated, the growth is performed. Most of the light is totally reflected at the interface between the substrate and the epi layer.

  Further, the reason for processing the surface of the epilayer into irregularities is to prevent total reflection from occurring between the epilayer and the material covering the periphery of the epilayer, thereby reducing the light extraction efficiency. .

  Both sides of the formation area of the upper and lower wirings 14 in the epi layer are selectively removed, and the upper and lower wirings 14 and the thin light emitting chip 13 are separated from each other. A conductive metal 19 having a length of about 500 nm is formed so as to penetrate the active layer 17 and the p-type compound semiconductor layer 18 in the intermediate portion from which both sides are selectively removed to reach the n-type compound semiconductor layer 16. Thus, the upper and lower wirings 14 are constituted by the conductor metal 19 and the n-type compound semiconductor layer 16 that are in contact with each other. As the material of the conductor metal 19, Al, Ni, Ag, Au, ITO (Indium Tin Oxide), etc., which can obtain ohmic characteristics with the n-type compound semiconductor layer 16, can be used. However, from the viewpoint of embedding in the active layer 17 and the p-type compound semiconductor layer 18, the length of the conductor metal 19 is desirably 500 nm or less, and 10 nm or more is desirable for obtaining ohmic characteristics.

  The surface on the conductor metal 19 side in the upper and lower wirings 14 having the above-described structure and the surface on the p-type compound semiconductor layer 18 side in the light emitting chip 13 are joined to the wafer 11 via the lower surface wiring 12.

  The lower surface wiring 12 is composed of two or more metal layers including a reflective layer 20, a first diffusion prevention layer 21, a bonding layer 22, and a second diffusion prevention layer 23. The reflective layer 20, the first diffusion preventing layer 21, the bonding layer 22, and the second diffusion preventing layer 23 are selectively formed as shown in FIG.

  As the material of the reflective layer 20, nickel (Ni) / silver (Ag) and ITO / aluminum (Al) are used. In addition, titanium (Ti) and tungsten (W) are used as materials for the first diffusion prevention layer 21 and the second diffusion prevention layer 23. Further, as the material of the bonding layer 22, a material containing gold (Au) and tin (Sn) is used.

  An insulator 24 is embedded in a groove between the light emitting chip 13 provided on both sides of the upper and lower wirings 14. As a material of the insulator 24, for example, polyimide (PI), SOG (Spin on Glass), or the like can be used.

  The upper surface wiring 15 electrically connects the surface of the upper and lower wirings 14 on the n-type compound semiconductor layer 16 side and the surface of the light emitting chip 13 on the n-type compound semiconductor layer 16 side. The material of the upper surface wiring 15 is not particularly limited as long as it can obtain ohmic characteristics with the n-type compound semiconductor layer 16, and for example, a metal such as ITO, Ni, Au, Al, and Ag can be used. .

  Next, a method for manufacturing the light-emitting chip integrated device in the present embodiment will be described. The light emitting chip integrated device is manufactured according to the flowchart shown in FIG. 3 to 5 schematically show cross-sectional structures for each manufacturing process of the light-emitting chip integrated device in the present embodiment. Hereinafter, each manufacturing process will be described using schematic diagrams of cross-sectional structures.

(1) Epi layer growth step (step S1 in the flowchart shown in FIG. 2)
In this step, as shown in FIG. 3A, first, a GaN-based epi layer is grown on the growth substrate 25 by metal organic vapor phase epitaxy (hereinafter abbreviated as “MOVPE”). In this case, as the growth substrate 25, sapphire (PSS: Patterned Sapphire Substrate) whose a-plane is the main surface and whose surface is processed into irregularities at a pitch of 30 μm is used.

  The epilayer is grown as follows. 3 (a) to 3 (c), the epi layer is depicted as being grown downward with respect to the growth substrate 25. The epi layer is grown.

First, the growth substrate 25 is baked at a temperature of 1100 ° C. while flowing H ₂ into the reaction chamber at normal pressure. After that, the temperature of the growth substrate 25 is lowered to 400 ° C., and H ₂ , NH ₃ and trimethyl aluminum (TMA) are supplied to form an AlN layer having a film thickness of about 25 nm as a buffer layer. Further, while maintaining the temperature of the growth substrate 25 at 1150 ° C., H ₂ , NH ₃ , trimethyl gallium (TMG) and silane are supplied, and the n-type compound semiconductor layer 16 has a film thickness of about 4.0 μm. Then, a highly doped n-type GaN layer having an electron concentration of 2 × 10 ¹⁸ / cm ³ is formed. Next, N ₂ or H ₂ , NH ₃ and TMG are supplied to form a barrier layer made of undoped GaN having a thickness of about 35 mm. Next, N ₂ or H ₂ , NH ₃ , TMG and trimethyl indium (TMI) are supplied to form a well layer made of Ga _0.8 In _0.2 N having a thickness of about 35 mm. Further, the barrier layer and the well layer are alternately formed four times under the same conditions, and a barrier layer made of undoped GaN is formed thereon. Thus, the active layer 17 having a five-layer MQW (multiple quantum well) structure is formed.

Next, the temperature of the growth substrate 25 on which the highly doped n-type GaN layer (n-type compound semiconductor layer) 16 and the active layer 17 are formed is maintained at 1100 ° C., and N ₂ or H ₂ , NH ₃ , TMG and Mg As a p-type compound semiconductor layer 18, a p-type GaN layer having a film thickness of about 70 nm and using Mg as a dopant is formed.

  Next, an etching mask is formed on the p-type GaN layer (p-type compound semiconductor layer) 18, and the portions of the p-type GaN layer 18 and the active layer 17 and the highly doped n-type GaN layer 16 that are not covered with the mask are formed. A part is removed by a thickness of 150 nm by reactive ion etching with a chlorine-based gas to expose the n-type GaN layer 16. This etching location becomes a location where the upper and lower wirings 14 will be formed later.

  As described above, the n-type GaN layer (n-type compound semiconductor layer) 16, the active layer 17 and the p-type GaN layer (p-type compound semiconductor layer) 18 are sequentially stacked on the growth substrate 25 by this step. A thin light emitting chip 13 is formed.

(2) p-electrode formation step (step S2 in the flowchart shown in FIG. 2)
Next, using the etching mask formed in the previous epilayer growth step, a conductor metal 19 is formed by a lift-off method as shown in FIG. The conductor metal 19 is a laminated film in which a Ti layer having a film thickness of about 50 nm and an Al layer having a film thickness of about 50 nm are laminated in this order from the n-type GaN layer (n-type compound semiconductor layer) 16 side. Then, an Al layer and any other metal of Ag, Bi, and Nd having a film thickness of about 50 nm are formed by sputtering. In this case, as described above, the etching depth by the chlorine-based gas with respect to a part of the p-type GaN layer 18, the active layer 17, and the highly doped n-type GaN layer 16 is about 150 nm. Therefore, it is sufficiently possible to fill the etching portion by sputtering with the Ti layer and the Al layer and the other metal, and to maintain flatness. After forming the conductor metal 19 in this way, the etching mask is removed using a resist stripping material.

Next, a photoresist is applied to the entire surface of the light emitting chip 13 by photolithography, and a window is formed in the lower surface wiring formation region of the light emitting chip 13 in the photoresist. Then, after evacuating to a high vacuum of the order of 10 ⁻⁶ Torr or less, as shown in FIG. 3 (b), a stack of a Ni layer having a film thickness of about 3 nm and an Ag layer having a film thickness of about 200 nm are formed. A film and a TiW layer having a thickness of 1 μm as the first diffusion preventing layer 21 are formed by sputtering.

  Next, the photoresist is removed by an existing technique. In this way, a laminated structure having the cross-sectional structure shown in FIG.

(3) Wafer bonding step (step S3 in the flowchart shown in FIG. 2)
Next, the wafer 11 is bonded to the growth substrate 25 on which the epi layer (the light emitting chip 13 and a part of the lower surface wiring 12) is grown.

The wafer 11 that can be used in the present invention preferably has a low thermal resistance and a thermal expansion coefficient close to that of the GaN-based material that is a constituent material of the light-emitting chip 13. Aluminum nitride (AlN) most suitable from the viewpoint is used. It should be noted that other materials can be used as the wafer 11 and, for example, gallium phosphide (GaP), germanium (Ge), gallium nitride (GaN), silicon (Si), silicon carbide (SiC), indium phosphide. (InP), sapphire (Al ₂ O ₃ ) or zinc oxide (ZnO) may be used.

  The wafer 11 is not limited to a non-conductive material as long as the outermost surface is an insulating layer. For example, a structure in which an insulating film is formed on the outermost surface may be used. That is, when Si, SiC, or the like is used as the wafer 11, the Si, SiC oxide or the like may be formed on the outermost surface. Further, the thickness of the wafer 11 may be 50 μm to 2 mm from the viewpoint of holding the sample, and more preferably 50 μm to 500 μm from the viewpoint of heat dissipation.

  Ti, W, or the like is selectively deposited as the second diffusion prevention layer 23 in the region where the first diffusion prevention layer 21 on the growth substrate 25 side on the surface of the wafer 11 is attached. The thickness of the second diffusion preventing layer 23 is about 1 μm.

  After that, as shown in FIG. 3C, the surface of the first diffusion prevention layer 21 on the growth substrate 25 side and the surface of the second diffusion prevention layer 23 on the wafer 11 side are interposed through the bonding layer 22. Pasted together. As the material of the bonding layer 22, a metal having a relatively low melting point such as Au—Sn eutectic is used.

  In this way, a laminated structure having the cross-sectional structure shown in FIG.

(4) Lift-off process (step S4 in the flowchart shown in FIG. 2)
As shown in FIG. 3D, after the growth substrate 25 on which the light emitting chip 13, the reflective layer 20, and the first diffusion preventing layer 21 are grown is attached to the wafer 11, as shown in FIG. Then, the growth substrate 25 is removed.

  In this case, the growth substrate 25 can be lifted off by thermal decomposition of the n-type compound semiconductor layer (highly doped n-type GaN layer) 16 constituting the light-emitting chip 13 with an excimer laser. Here, the photon energy of the excimer laser exceeds the band gap of the crystal layer adjacent to sapphire constituting the growth substrate 25 (in many cases, GaN or AlGaN; n-type GaN layer 16 in this embodiment). Selected. Therefore, the pulse energy is applied from the junction surface between the growth substrate (sapphire) 25 and the epi layer (that is, the interface position with the buffer layer) to the epi layer side (that is, the n-type GaN layer (n-type compound semiconductor layer) In the region of the n-type GaN layer (n-type compound semiconductor layer) 16 within 100 nm (on the 16 side), it is effectively converted into thermal energy.

  That is, it is above the band gap of the crystal layer (n-type GaN layer 16) adjacent to the sapphire (growth substrate 25) and below the absorption edge of the sapphire (that is, about 3.44 eV and about 6 eV). For sufficiently high photon energies (between), the temperature in the region rises to over 1000 ° C. on a nanosecond scale. This temperature is high enough to separate the n-type GaN layer 16 into gallium gas and nitrogen gas and to peel the epi layer including the n-type GaN layer 16 from the growth substrate 25. . As a result, the growth substrate 25, the AlN buffer layer, and the low crystal quality n-type GaN region which is the n-type GaN layer 16 existing in the region in contact with the AlN buffer layer are peeled off and removed. Note that the lift-off can be achieved by a single laser line scanning irradiation of the entire surface of the growth substrate 25.

  On the other hand, the removal of the silicon-based (for example, SiC, SiC-on-insulator, SiC-on-quartz, Si, etc.) growth substrate 25 is performed using a conventional etching technique such as reactive ion etching. It can be carried out. For example, the growth substrate 25 of the SiC-on-insulator can be lifted off by forming a peeling layer between the growth substrate 25 and the epi layer and removing the peeling layer by etching. . By using this technique, an undercut etch layer as the release layer is grown between the sapphire growth substrate 25 and the n-type GaN layer 16 (that is, under the epilayer), thereby growing sapphire. The substrate 25 can be removed by removing the undercut etch layer by etching.

  In this way, a laminated structure having the cross-sectional structure shown in FIG.

(5) Surface treatment process (step S5 in the flowchart shown in FIG. 2)
As described above, after the growth substrate 25 is removed, the gallium metal generated in the laser separation and remaining on the surface of the n-type GaN layer 16 is washed with an aqueous hydrochloric acid solution. Thereafter, the epi layer (light emitting chip 13) is thinned by dry etching. The epitaxial layer thus thinned is roughened by, for example, photoelectrochemical etching using molten potassium hydroxide (KOH) or sodium hydroxide (NaOH). Thus, by roughening the outermost surface of the epi layer, the light extraction efficiency from the light emitting region (active layer 17) can be increased. In the present embodiment, treatment is performed with potassium hydroxide heated to 400 ° C. and melted, and the outermost surface of the epi layer is formed into an uneven shape.

(6) Epi layer separation step (step S6 in the flowchart shown in FIG. 2)
Next, after an etching mask is formed on the n-type GaN layer 16, the mask in a predetermined region is removed, and portions of the n-type GaN layer (n-type compound semiconductor layer) 16 and the active layer 17 that are not covered with the mask are removed. Then, the p-type GaN layer (p-type compound semiconductor layer) 18 and the reflective layer 20 are subjected to reactive ion etching treatment using a chlorine-based gas. Thus, as shown in FIG. 4 (f), the surface of the first diffusion prevention layer 21 and the surface of the bonding layer 22 between the region to be the upper and lower wirings 14 and the light emitting chips 13 located on both sides of this region are formed. Expose. As a result, the n-type GaN layer (n-type compound semiconductor layer) 16, the active layer 17, and the p-type compound semiconductor layer 18 are disposed between the exposed surface of the first diffusion prevention layer 21 and the exposed surface of the bonding layer 22. The conductive metal (Ti / Al) 19 embedded in the n-type and in ohmic contact with the n-type compound semiconductor layer 16 becomes the upper and lower wirings 14.

(7) Bonding layer removing step (step S7 in the flowchart shown in FIG. 2)
Next, the bonding layer (Au—Sn eutectic) 22 remaining between one side of each light emitting chip 13 and the upper and lower wirings 14 adjacent to the one side is removed by wet etching using an acidic solution. . As the acidic solution, nitric acid, sulfuric acid, hydrochloric acid or potassium iodide solution can be used. In the present embodiment, the treatment was performed for 10 minutes using 50% sulfuric acid diluted with pure water. As a result, the first region between the first diffusion prevention layer 21 and the first diffusion prevention layer 21 adjacent to each other, and the second region between the second diffusion prevention layer 23 and the second diffusion prevention layer 23 adjacent to each other. And the bonding layer 22 existing in the third region sandwiched between the first and second regions and the first and second regions are completely removed. At that time, the bonding layer (Au-Sn eutectic) 22 constituting the lower surface wiring 12 sandwiched between the other first diffusion prevention layer 21 and the second diffusion prevention layer 23 remains without being etched. Yes. This was confirmed by observation with a scanning microscope after cutting the cross section.

  In this way, a laminated structure having the cross-sectional structure shown in FIG.

(8) Insulator embedding step (step S8 in the flowchart shown in FIG. 2)
Next, an insulator 24 is embedded in the gap between each light emitting chip 13 and each upper and lower wiring 14 as follows.

That is, first, a light-transmitting polyimide varnish is used as the insulator 24, and the entire surface including the light-emitting chip 13 and the upper and lower wirings 14 is applied by spin coating, and then the polyimide varnish is cured. Let The varnish was cured under conditions of 200 ° C. and 2 hours in an N ₂ atmosphere.

  Next, the insulator (polyimide) 24 is etched by ICP (inductively coupled plasma) until the surfaces of the light emitting chip 13 and the upper and lower wirings 14 are exposed. In this way, the insulator 24 is embedded in the gap between the light emitting chip 13 and the upper and lower wirings 14.

  Thus, by embedding the light-transmitting insulator 24 having a refractive index of about 1.5 between the light-emitting chips 13 having a refractive index of about 2.4, the inside of the insulator 24 once from the light-emitting chip 13. Can be prevented from being absorbed in the adjacent light emitting chip 13. Therefore, the light extraction efficiency can be increased.

  As described above, a laminated structure having the cross-sectional structure shown in FIG.

(9) Upper surface wiring formation step (step S9 in the flowchart shown in FIG. 2)
Next, the upper surface wiring 15 is made up of an n-type GaN layer (n-type compound semiconductor layer) 16 of the light emitting chip 13 and an n-type GaN layer (n-type compound semiconductor layer) 16 of the upper and lower wirings 14 as follows. Form to connect. That is, a photoresist is applied to the entire surface of the upper surface wiring formation region of the light emitting chip 13 by photolithography, and a window is formed in the formation region of the upper surface wiring 15 in the photoresist by photolithography. Then, after evacuation to a high vacuum of the order of 10 ⁻⁶ Torr or less, a 2 μm thick Ni / Au laminated film as an electrode material is formed by sputtering. After that, the photoresist is removed.

  In this way, a laminated structure having the cross-sectional structure shown in FIG.

(10) Packaging process (step S10 in the flowchart shown in FIG. 2)
Next, each light emitting chip integrated device is divided by dicing. Here, the light emitting chips 13 arranged in a vertical 6 × horizontal 6 are electrically connected in series to form a light emitting chip array, and two or more of the light emitting chip arrays are electrically connected in parallel or anti-parallel. Thus, the light emitting chip integrated device is configured. Therefore, about 300 light-emitting chip integrated devices are divided from the 2-inch wafer. Each light emitting chip integrated device and an external terminal for connecting the light emitting chip integrated device to an AC power source are connected by two gold wires.

  Thereafter, the light-emitting chip integrated device is packaged by phosphor sealing resin or the like using an existing packaging technique.

  As described above, in the present embodiment, a plurality of light emitting chips 13 having a thickness of several tens of μm formed by sequentially laminating the n-type compound semiconductor layer 16, the active layer 17, and the p-type compound semiconductor layer 18 are provided. The p-type compound semiconductor layer 18 is bonded to the wafer 11 via the lower surface wiring 12 as an attachment surface. Of the two light emitting chips 13 adjacent to each other, the n-type compound semiconductor layer 16 of one light-emitting chip 13 and the p-type compound semiconductor layer 18 of the other light-emitting chip 13 include the upper surface wiring 15, the upper and lower wirings 14, and the lower surface. The wirings 12 are electrically connected in series via a conductive path that is continuous. Thus, a plurality of thin light emitting chips 13 formed on the wafer 11 are connected in series.

  At this time, the n-type compound semiconductor layer 16, the active layer 17, and the p-type compound semiconductor layer are arranged between the light emitting chips 13 adjacent to each other, and are separated from each light emitting chip 13 by an insulator 24. 18, the n-type compound semiconductor layer 16 penetrates through the n-type compound semiconductor layer 16 and the active layer 17 and the p-type compound semiconductor layer 18 stacked below the n-type compound semiconductor layer 16. And a conductive metal 19 embedded so as to reach the end.

  Therefore, according to the present embodiment, the n-type compound semiconductor formed simultaneously with the n-type compound semiconductor layer 16 of the light-emitting chip 13 when forming the upper and lower wirings 14 for connecting the light-emitting chips 13 adjacent to each other in series. The depth of embedding the conductor metal 19 becomes shallower as much as the layer 16 is used, and the metal wrapping into the groove for embedding the conductor metal can be promoted. Therefore, as in the semiconductor light emitting device disclosed in Patent Document 1 shown in FIG. 8, metal deposition proceeds excessively with respect to the edge portion of the electrode groove, leaving a cavity inside the electrode groove. The problem of being blocked by metal does not occur. Therefore, the formation of the upper and lower wirings 14 is easy, and the necessity for fearing disconnection of the upper and lower wirings 14 is low. Furthermore, the time spent for forming the upper and lower wirings 14 can be greatly reduced.

Second Embodiment In the first embodiment, as described above, the upper and lower wirings 14 are stacked on the n-type compound semiconductor layer 16 and on the lower side of the n-type compound semiconductor layer 16. And a conductive metal 19 embedded through the layer 17 and the p-type compound semiconductor layer 18 so as to reach the n-type compound semiconductor layer 16. However, the present invention is not limited to this, and as shown in FIG. 6, the upper and lower wirings 14 are provided with an n-type compound semiconductor layer 16 and an n-type compound semiconductor layer below the n-type compound semiconductor layer 16. It is also possible to configure with a conductive metal 19 formed in contact with 16. This embodiment relates to a light-emitting chip integrated device shown in FIG.

  FIG. 7 schematically shows a cross-sectional structure for each manufacturing process different from the manufacturing process of the first embodiment in the light-emitting chip integrated device of the present embodiment. Hereinafter, each manufacturing process will be described using schematic diagrams of cross-sectional structures. The light emitting chip integrated device is manufactured according to the flowchart shown in FIG.

  In this embodiment, (1) epi layer growth step, (2) p-electrode formation step, (3) wafer bonding step, and (4) lift-off step are the same as those in the first embodiment. It is. However, in the (2) p-electrode forming step, a laminated film of ITO and Al is used as the reflective layer 20. The cross-sectional structure diagrams in each process from (1) epilayer growth step to (4) lift-off step are the same as those in FIGS. 3 (a) to 3 (d) and FIG. 4 (e) in the first embodiment. Therefore, the same members are assigned the same numbers, and detailed description is omitted.

(5) Surface treatment step After the growth substrate 25 is removed by the (4) lift-off step, photoelectrochemical etching is performed using an alkaline solution to roughen the surface of the epi layer. As the alkaline solution, potassium hydroxide (KOH) or sodium hydroxide (NaOH) can be used. In the present embodiment, the outermost surface of the epi layer was formed into a concavo-convex shape by treatment with potassium hydroxide heated to 400 ° C. and melted.

(6) Epi layer separation step Next, after forming an etching mask on the n-type GaN layer 16, the mask in a predetermined region is removed, and a portion of the n-type GaN layer (n-type compound semiconductor layer not covered with the mask) is removed. ) 16, the active layer 17, the p-type GaN layer (p-type compound semiconductor layer) 18, and the reflective layer 20 are subjected to a reactive ion etching process using a chlorine-based gas. Thus, as shown in FIG. 7A, the surface of the first diffusion prevention layer 21 and the surface of the bonding layer 22 between the region to be the upper and lower wirings 14 and the light emitting chips 13 located on both sides of this region are formed. Expose. At this time, in the present embodiment, the region to be the upper and lower wirings 14 is n-type GaN layer (n-type) between the exposed surface of the first diffusion prevention layer 21 and the exposed surface of the bonding layer 22. The compound semiconductor layer) 16 and the conductive metal (Ti / Al) 19 that is in ohmic contact with the n-type compound semiconductor layer 16 are configured.

(7) Bonding layer removing step As in the bonding layer removing step in the first embodiment, a first region between the first diffusion preventing layer 21 and the first diffusion preventing layer 21 adjacent to each other, It exists in the second region between the second diffusion prevention layer 23 and the second diffusion prevention layer 23 adjacent to each other and the third region sandwiched between the first and second regions. The bonding layer 22 is completely removed. Thus, a laminated structure having the cross-sectional structure shown in FIG.

(8) Insulator Embedding Step In the same manner as the insulator embedding step in the first embodiment, the insulator 24 is buried in the gap between the light emitting chip 13 and the upper and lower wirings 14. Thus, a laminated structure having the cross-sectional structure shown in FIG.
(9) Upper surface wiring formation step In the same manner as in the upper surface wiring formation step in the first embodiment, the n-type GaN layer (n-type compound semiconductor layer) 16 of the light emitting chip 13 and the n-type GaN of the upper and lower wirings 14 are used. An upper surface wiring 15 that connects the layer (n-type compound semiconductor layer) 16 is formed. Thus, a laminated structure having the cross-sectional structure shown in FIG.

(10) Packaging Step Similarly to the packaging step in the first embodiment, each light emitting chip integrated device is divided for each light emitting chip integrated device by dicing, and the light emitting chip integrated device is packaged by phosphor encapsulating resin or the like. Is done.

  As described above, according to the present embodiment, as in the case of the first embodiment, the formation of the upper and lower wirings 14 is easy, and the time spent for forming the upper and lower wirings 14 can be greatly reduced. Thus, it is possible to obtain a light-emitting chip integrated device that is less necessary to worry about disconnection of the upper and lower wirings 14.

  In each of the above embodiments, the thin light-emitting chip 13 bonded onto the wafer 11 epitaxially grows the n-type compound semiconductor layer 16, the active layer 17, and the p-type compound semiconductor layer 18 on the growth substrate 25. The substrate is peeled off from the growth substrate 25 and formed. As a result, since the n-type compound semiconductor layer 16 becomes the outermost layer of the light-emitting chip 13, the light emitted from the surface of the n-type compound semiconductor layer 16 occupies the light emitted from the active layer 17 of the light-emitting chip 13. The ratio can be increased to about 97%. Therefore, the ratio of the light emitted from the side surface of the light emitting chip 13 can be reduced to about 3%, and the light emitted from the side surface of the light emitting chip 13 is absorbed mainly by the active layer 17 of the adjacent light emitting chip 13. Light can be reduced, and reduction in light extraction efficiency can be prevented.

  Further, the surface of the n-type compound semiconductor layer 16 after the growth substrate 25 in the light emitting chip 13 is peeled off is subjected to uneven processing. Therefore, it is possible to suppress the total reflection between the surface of the light emitting chip 13 made of the epi layer and the resin or the like that covers the periphery of the light emitting chip 13 and to prevent the light extraction efficiency from being lowered.

  Further, the growth substrate 25 having a high thermal resistance such as sapphire used for obtaining an epi layer having a good crystallinity when the light emitting chip 13 is formed is peeled off and AlN, SiC, Si or Ge having a low thermal resistance. Or the like. Therefore, the heat dissipation of the light emitting chip integrated device obtained can be improved.

  Furthermore, a light emitting chip with a low decrease in light emitting efficiency is obtained by configuring a light emitting chip integrated device by connecting a plurality of light emitting chips 13 having high heat dissipation characteristics and high light extraction characteristics as described above in series. An integrated device can be obtained. There are two reasons for this.

  The first reason is that the light emitting chip integrated device as a whole, even if the location where the penetrating potential is locally concentrated or abnormally grown in the light emitting chip 13 made of the epi layer becomes leaky. May emit light normally. For example, when a light-emitting chip integrated device is configured by using one light-emitting chip having a large area, current does not flow in a portion where normal current is epitaxially grown due to current flowing intensively in the leak portion. When the entire light emitting chip is pulled, the light emitting chip integrated device does not emit light. On the other hand, when a plurality of light-emitting chips 13 are integrated to form a light-emitting chip integrated device having the same size as the case where one large-area light-emitting chip is used, there is a leak failure in one light-emitting chip 13. Even in such a case, current flows through the other light emitting chips 13 that are normally epitaxially grown, so that most of the light emitting chips 13 except the defective light emitting chips 13 emit light normally. Therefore, the light emitting chip integrated device as a whole emits light normally, and the yield can be significantly improved.

  The second reason is that the area of the light emitting chip 13 is reduced, and the current density flowing in the active layer 17 may be made uniform. For example, when the area of the light emitting chip is increased, the current density flowing in the active layer becomes non-uniform, and the light emission intensity decreases. On the other hand, when a plurality of light emitting chips 13 are integrated to form a light emitting chip integrated device having the same size as that of a large area light emitting chip, the size of each light emitting chip 13 is small. 17 is less likely to cause uneven current density. Therefore, it is possible to maintain the high internal quantum efficiency of the light-emitting chip 13 and prevent the emission intensity per unit area from being lowered. Therefore, it is possible to obtain a light-emitting chip integrated device with extremely high light emission efficiency.

  In each of the above embodiments, the conductive metal 19 constituting the upper and lower wirings 14 of the conductive path for electrically connecting the light emitting chips 13 adjacent to each other is connected to the n-type GaN layer (n-type compound semiconductor layer) 16. In order from the side, it is composed of a laminated film in which a Ti layer and an Al layer are laminated. By doing so, Ti of the Ti layer diffuses into the n-type compound semiconductor layer 16 to reduce the thickness of the Schottky barrier and to reduce ohmic resistance. Therefore, the ohmic resistance between the n-type compound semiconductor layer 16 and the conductive metal 19 can be lowered. As a result, the electric resistance of the conductive path can be reduced, and the power consumption of the light emitting chip integrated device can be reduced.

  In each of the above embodiments, the length of the conductor metal 19 in the direction of the conductive path is set to 10 nm or more. Therefore, the conductor metal 19 can be formed with high accuracy, good ohmic characteristics with the n-type compound semiconductor layer 16 can be obtained, and the upper and lower wirings 14 exhibiting good characteristics can be obtained. Further, the length in the conductive path direction is set to 500 nm or less. Therefore, good embeddability in the active layer 17 and the p-type compound semiconductor layer 18 can be obtained.

  In each of the above embodiments, a translucent insulator 24 is embedded between the light emitting chip 13 and the upper and lower wirings 14. Therefore, the light emitted from the light emitting chip 13 is not absorbed by the adjacent light emitting chip 13, and the light extraction efficiency of the present light emitting chip integrated device can be maximized.

  In the present embodiment, in the above packaging process, 12 light emitting chips 13 arranged in 6 × 6 are divided for each light emitting chip integrated device electrically connected in series. However, the present invention is not limited to this. For example, if 29 or more and 40 or less light emitting chips 13 are electrically connected in series to form a light emitting chip integrated device, a light emitting chip integrated device that can be driven by a commercial 100V power supply can be realized in one package.

  Since the rated voltage of one light emitting chip 13 is generally 2.5 V to 3.5 V, when driving with a commercial 100 V power supply, 29 to 40 light emitting chips 13 can be connected in series and used. It is. However, when the number of light emitting chips 13 to be connected exceeds or is less than the range of 2.5V to 3.5V, the internal quantum efficiency of each light emitting chip 13 is significantly reduced. Even in such a light emitting chip integrated device in which 29 to 40 light emitting chips 13 are connected in series, the heat resistance of the wafer 11 made of AlN, SiC, Si, Ge, or the like is small, so that heat dissipation is high. Since the mutual absorption of light by the light emitting chips 13 adjacent to each other is several percent, the light emission efficiency as a light emitting chip integrated device is very high.

  Furthermore, even if there is a defective light emitting chip 13, since the defect is in the leak mode, it does not adversely affect other normal light emitting chips 13 such as a decrease in light emission efficiency. For example, even if there is one defective light emitting chip 13 in a light emitting chip integrated device having 35 light emitting chips 13, it is possible to limit the decrease in the light emission amount of the light emitting chip integrated device to about 2.9%. . And the thin light emitting chip integrated device in which such light output has been reduced can be ranked and used as a product. Therefore, according to the present embodiment, the defect rate of the light emitting chip integrated device can be reduced.

  In addition, the number of wires used for wiring connection of the light emitting chip 13 can be reduced. For example, even in a light emitting chip integrated device having 35 light emitting chips 13, since the 35 light emitting chips 13 are connected in series, only two wires used for external terminal connection are necessary. The existing mounting process can be greatly shortened.

  In the present embodiment, a light emitting chip integrated device having a plurality of light emitting chips 13 is arranged in two or more rows of light emitting chip arrays in which a plurality of light emitting chips 13 are electrically connected in series via the conductive path. It is configured by electrical connection in parallel. Therefore, a light-emitting chip integrated device that can be driven by a commercial 100V power supply can be realized in one package.

  When driving a light-emitting chip integrated device with a commercial 100V power supply, a light-emitting chip array in which 29 to 40 light-emitting chips 13 are connected in series is electrically connected in parallel to a plurality of columns, thereby simply having 29 to 40 light-emitting chips. A light-emitting chip integrated device larger than the light-emitting chip integrated device in which the light-emitting chips 13 are connected in series can be formed.

  At this time, even if the driving voltage of each light emitting chip 13 varies greatly, when viewed for each light emitting chip array, the driving voltage is averaged to reduce variation. Accordingly, the currents flowing through the respective light emitting chip arrays are substantially equal, and all the light emitting chip arrays can emit light uniformly.

  In the present embodiment, a light emitting chip integrated device having a plurality of light emitting chips 13 is arranged in two or more rows of light emitting chip arrays in which a plurality of light emitting chips 13 are electrically connected in series via the conductive path. It is configured to be electrically connected in antiparallel. Therefore, a light-emitting chip integrated device that can be driven by an AC commercial 100V power supply can be realized in one package.

  When a light-emitting chip array in which 29 to 40 light-emitting chips 13 are connected in series is driven by an AC commercial 100V power source, each light-emitting chip 13 emits light only when forward biased, so a bias is applied in the reverse direction. It does not emit light during the specified period. Therefore, a light emitting chip integrated device in which any one of the light emitting chip arrays always emits light can be obtained by electrically connecting the light emitting chip arrays in which 29 to 40 light emitting chips 13 are connected in series in reverse parallel. It can be done. Moreover, the number of mounted light emitting chips 13 can be doubled. Therefore, it is possible to form a light emitting chip integrated device that is larger than a light emitting chip integrated device in which 29 to 40 light emitting chips 13 are simply connected in series.

11 ... wafer,
12 ... lower surface wiring,
13: Light emitting chip,
14: Vertical wiring,
15 ... upper surface wiring,
16 ... n-type compound semiconductor layer,
17 ... active layer,
18 ... p-type compound semiconductor layer,
19: Conductor metal,
20 ... reflective layer,
21 ... 1st diffusion prevention layer,
22: bonding layer,
23 ... second diffusion prevention layer,
24. Insulator,
25: Growth substrate.

Claims (7)

a light-emitting chip configured by sequentially stacking a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer;
A plurality of the light emitting chips are bonded using the surface of the p-type compound semiconductor layer of each light emitting chip as a bonding surface;
A lower surface wiring interposed between the wafer and the plurality of light emitting chips bonded to each other;
A conductive path that electrically connects the n-type compound semiconductor layer in any one of the two light emitting chips adjacent to each other and the p-type compound semiconductor layer in the other;
The conductive path is
A top surface wiring connected to the n-type compound semiconductor layer in the one light emitting chip;
The lower surface wiring connected to the p-type compound semiconductor layer in the other light emitting chip;
An n-type compound semiconductor layer that is connected to the upper surface wiring and the lower surface wiring and is formed at the same time as the n-type compound semiconductor layer of the light emitting chip in a region between the two adjacent light emitting chips; It is configured to include upper and lower wiring including conductor metal,
A light-emitting chip integrated device, wherein a plurality of the light-emitting chips joined to the wafer via the lower surface wiring are electrically connected in series by the conductive path. The light emitting chip integrated device according to claim 1, wherein the upper and lower wirings are
Regarding a stacked structure of the n-type compound semiconductor layer, the active layer, and the p-type compound semiconductor layer, which are in a region between the light-emitting chips adjacent to each other and separated from each light-emitting chip by an insulator,
The n-type compound semiconductor layer;
The active metal layer laminated below the n-type compound semiconductor layer, and the conductive metal embedded so as to penetrate the p-type compound semiconductor layer and reach the n-type compound semiconductor layer. A light-emitting chip integrated device. The light emitting chip integrated device according to claim 1, wherein the upper and lower wirings are
The n-type compound semiconductor layer in a region between the light emitting chips adjacent to each other and separated from each light emitting chip by an insulator;
In the region between the light emitting chips adjacent to each other, stacked below the n-type compound semiconductor layer and electrically connected to the n-type compound semiconductor layer, and each light-emitting chip is an insulator. A light-emitting chip integrated device, comprising: the conductive metal separated by (1). The light-emitting chip integrated device according to any one of claims 1 to 3,
The conductive metal is composed of a metal containing titanium and aluminum,
The light emitting chip integrated device, wherein the conductive metal is laminated in the order of the titanium, the aluminum and other metals from the n-type compound semiconductor layer side. The light-emitting chip integrated device according to any one of claims 1 to 4,
A length of the conductive metal in the direction of the conductive path is 10 nm or more and 500 nm or less. The light-emitting chip integrated device according to any one of claims 1 to 5,
A light emitting chip integrated device, wherein a translucent insulator is embedded between the upper and lower wirings and the light emitting chip adjacent to the upper and lower wirings. A method for manufacturing a light-emitting chip integrated device according to any one of claims 1 to 6,
Sequentially forming an n-type compound semiconductor layer, an active layer, and a p-type compound semiconductor layer on a first substrate;
Removing a part of the p-type compound semiconductor layer and the active layer formed on the first substrate to form a plurality of recesses, and exposing the n-type compound semiconductor layer;
A conductor metal is formed on the p-type compound semiconductor layer on the first substrate, the insides of the plurality of recesses are filled with the conductor metal, and the conductor metal is electrically connected to the n-type compound semiconductor layer. Connecting to
Forming a lower surface wiring layer on the entire surface including the p-type compound semiconductor layer on the first substrate;
The first substrate on which the n-type compound semiconductor layer, the active layer, the p-type compound semiconductor layer, the conductor metal, and the lower surface wiring layer are formed on a second substrate is formed on the surface of the lower surface wiring layer. As a bonding surface, a step of bonding via a bonding layer;
Peeling the first substrate from the n-type compound semiconductor layer;
One side of each recess embedded with the conductor metal is removed until the lower surface wiring layer is exposed to form a first separation groove, while the other side is removed until the second substrate is exposed. Forming a second separation groove and separating into a plurality of light emitting chips including the n-type compound semiconductor layer, the active layer, and the p-type compound semiconductor layer;
Embedding an insulator in the first separation groove and the second separation groove;
The n-type compound semiconductor layer between the first separation groove and the second separation groove, and the light-emitting chip adjacent to the n-type compound semiconductor layer with the second separation groove interposed therebetween. forming an upper surface wiring for electrically connecting the n-type compound semiconductor layer,
The adjacent light emitting chips formed on the second substrate are electrically connected to the upper surface wiring between the upper surface wiring, the first separation groove, and the second separation groove. A light-emitting chip integrated device, wherein the n-type compound semiconductor layer is connected in series via the connected n-type compound semiconductor layer, the conductive metal, and the lower wiring layer in contact with the conductive metal. Production method.

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