CN1956158A - 焊料凸块的制造方法、中间结构 - Google Patents

焊料凸块的制造方法、中间结构 Download PDF

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CN1956158A
CN1956158A CNA2005100969213A CN200510096921A CN1956158A CN 1956158 A CN1956158 A CN 1956158A CN A2005100969213 A CNA2005100969213 A CN A2005100969213A CN 200510096921 A CN200510096921 A CN 200510096921A CN 1956158 A CN1956158 A CN 1956158A
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solder
scolder
cylinder
solder projection
less important
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蔡育莹
陈世明
林国伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明是提供一焊料凸块的制造方法、中间结构。此方法包括在一半导体基板上形成一焊垫以及在此基板及此焊垫上配置一掩膜层。此方法亦包括在具有一个主要焊料模仁以及至少一个与主要焊料模仁相连接的次要焊料模仁的掩膜层内形成一开口，此开口曝露此焊垫的一部分。更包括以焊料填充此主要焊料模仁以及此至少一个次要焊料模仁，以形成一个相对应的主要焊料柱体及至少一个相对应的次要焊料柱体而与此焊垫形成电性接触。此方法也包括于填充步骤之后移除此掩膜层。此方法更包括一再流动步骤，使得焊料于熔化时相互结合以形成一主要焊料凸块，其中上述焊料是来自此主要焊料柱体的焊料及至少一部分来自此次要焊料柱体的焊料。

Description

焊料凸块的制造方法、中间结构
技术领域
本发明是有关于一种用于提供不同基板间电性及机械性结合的焊料凸块(solder bump)，且特别有关于一种中间集成电路晶片焊料凸块结构、一种已完成的集成电路晶片焊料凸块结构，及其制造方法。
背景技术
集成电路晶片封装制程是整个制程中最重要的一个步骤，其影响整个成本、封装晶片的性能、以及元件可靠度。当半导体元件达到更高程度的整合，晶片封装技术亦达极限。集成电路晶片封装对于元件的制造成本具有一定的影响，且封装失败会造成重大的良率损失。
当半导体元件与晶片的尺寸不断缩小，晶片上元件的密度便不断增加，因此使得晶片封装的难度提高。其中导致封装失败的最主要问题是材料之间热膨胀系数(TCE)的差异，如此会导致应力的产生及后续制程的失败。
例如，在覆晶封装技术中，是在下凸块金属化层上形成焊料凸块，其中下凸块金属化层覆盖在一集成电路晶片焊垫(bonding pad)上方。但是通常焊料凸块与下凸块金属化层彼此之间材料性质的差异会导致集成电路晶片无法承受应力。
封装失败后的重新封装制程很耗费成本，且需要重复晶片封装制程。有些封装技术利用焊料凸块与晶片上的焊垫结合，使得晶片元件与封装基板形成电性连接。
例如，C4封装技术(Controlled-Collapse ChipConnection；C4)在电子封装中是一个连接半导体晶片与基板的工具。C4封装技术是一种覆晶封装技术，利用晶片焊垫与小焊料球(凸块)连接。因为焊料球形成一区域阵列(ball gridarray；BGA)，所以对于具有低寄生电感的元件而言，覆晶封装技术的优点在于可以达到一高密度的连接。
焊料凸块的形成方法如下。首先，于一焊垫上方形成下凸块金属化层。然后，例如利用气相沉积法于下凸块金属化层上沉积焊料以形成焊料凸块。
在其它方法中，可以在焊垫上形成下凸块金属化层，然后沉积晶种层材料，再利用电子沉积(clectro-deposition)沉积焊料层。
还有其它方法则是利用焊膏网版印刷方法(solder-pastescreen-printing method)，并以光罩或印刷模板导引焊膏的放置。通常在沉积层状或均匀相的混合物的焊料后，将定义焊料位置的光致抗蚀剂保护层移除，然后将焊料加热至熔点(即所谓的再流动步骤)而形成焊料凸块(球)，其中焊料凸块(球)是借助表面张力而形成。
其它的方法则可能以光致抗蚀剂或其它有机树脂材料制成的永久保护层定义焊垫上的焊料凸块区的位置，并于此焊料凸块区内形成焊料凸块。由于焊料凸块/球在覆晶封装技术中占有重要地位，因此业界急需一种于集成电路晶片上形成焊料凸块/球的制程的改善方法。
图1A至图1E为一集成电路晶片焊垫区的系列剖面图，用以说明现有技术于半导体晶片上制作焊料凸块的流程。
图1A是说明形成焊料凸块的初期步骤。首先，于半导体晶圆8的表面上形成一晶片焊垫10，此晶片焊垫10例如是铜或铝。
然后，在半导体元件表面形成一保护层12，此保护层12例如是二氧化硅。其中，此保护层12只覆盖此晶片焊垫10的部分表面。
接着，通常沉积一层或多层厚度约介于500埃至5000埃的下凸块金属化层14A(under-bump metallization layer；UBM layer)于此晶片焊垫10上，以及如图1B所示的光致抗蚀剂层16。此下凸块金属化层14A可以是一钛层。通常，此光致抗蚀剂层16的高度约介于10微米至25微米。
如图1B所示，经过微影制程后于此光致抗蚀剂层16形成开口17，使得此晶片焊垫10上的此下凸块金属化层14A外露。
另外，亦可以利用电镀制程或气相沉积制在开口17内形成额外的下凸块金属化层14B及14C，如图1C所示。下凸块金属化层14B及14C可以分别是铜层及镍层。其中，形成于焊垫10上的下凸块金属化层具有两个功用，一个是增加最上层下凸块金属化层14C与其上的焊料之间的结合及润湿能力，另一个则是最下层的下凸块金属化层14A可以保护其下方的焊垫10。
接着，亦可以沉积一焊料18A的圆形柱状物，其包括一铅层及其上的一锡层，此焊料18A会在后续的再流动步骤(暂时熔化)中形成一均匀相的焊料。在其它实施例中，可以利用气相沉积法或电镀法在一晶种层上，例如是在下凸块金属化层14C上沉积一均匀相的焊料。
图1D说明，移除光致抗蚀剂层16后，利用反应离子蚀刻制程或其它蚀刻制程以移除部分区域的下凸块金属化层14A，以露出保护层12的部分表面。另一方面，下凸块金属化层14A未被移除的部分区域则是利用焊料18A作为一蚀刻掩膜层，以保护其下方的下凸块金属化层14A、14B、以及14C。
随后，焊料18A被加热至熔点而发生再流动(reflow)的现象，以便在下凸块金属化层14C上形成一焊料凸块18B，如图1E所示。
于再流动步骤后，形成一均匀相的铅/锡的焊料凸块，例如以组成比表示重量百分比的富铅合金，包括95Pb/5Sn(95/5)或90Pb/10Sn(90/10)，其熔点超过300℃；或者共熔合金63Pb/37Sn(63/37)，其熔点为183℃。焊料凸块18B由一均匀相的材料构成且有一明确的熔点。例如，具有高熔点的Pb/Sn合金因为有良好的金属疲劳抗性，所以适合凸块冶金。
多层的方式适合形成下凸块金属化层且在再流动步骤中，最上面邻接焊料的下凸块金属化层为后续形成的焊料凸块的再流动过程提供一润湿层(wettable layer)。例如，形成多个下凸块金属化层，有些多个下凸块金属化层可以包括铬/铜、钛/铜、和钛-钨/铜(Ti:W/Cu)，以及钛/铜/镍。其中，先叙述者表示连接焊垫10的最下层。
因为在覆晶封装技术的焊料的再流动步骤中，传统凸块是完全熔化以与下凸块金属化层完全地接触，此下凸块金属化层必须能承受热及机械应力，并且阻止金属之间的界面形成。因此，下凸块金属化层的品质及润湿能力于再流动步骤中，对于其与焊料凸块之间结合的可靠度是很重要的。
此下凸块金属化层有助于决定再流动步骤后的焊料凸块18B的尺寸，并且提供一具备润湿能力的表面，此表面也会与焊料反应，使得下凸块金属化层与焊料凸块18B之间的结合更为完整，因而使得元件在机械应力与热应力下具有更高的可靠度。另外，下凸块金属化层亦可在半导体元件与内连线层的金属之间扮演阻障层的角色。
发明内容
本发明是揭示一种半导体元件上的焊料凸块的制造方法。此方法包括形成一焊垫于一半导体基板上，然后配置一掩膜层于此基板及此焊垫上。此方法亦包括于此掩膜层形成一开口，此掩膜层具有一个主要焊料模仁以及至少一个与主要焊料模仁相连接的次要焊料模仁，此开口曝露此焊垫的一部分。此方法更包括以焊料填充此主要焊料模仁以及此至少一个次要焊料模仁，以形成一个相对应的主要焊料柱体及至少一个相对应的次要焊料柱体而与此焊垫形成电性接触。此方法也包括于填充步骤之后移除此掩膜层。此方法更包括一再流动步骤，使得焊料于熔化时相互结合以形成一主要焊料凸块，其中上述焊料是来自此主要焊料柱体的焊料及至少一部分来自此次要焊料柱体的焊料。
本发明所述的焊料凸块的制造方法，该主要焊料柱体的体积是大于每一该至少一个次要焊料柱体的体积。
本发明所述的焊料凸块的制造方法，该再流动步骤更包括该至少一个次要焊料柱体的一剩余部分，该剩余部分未用于该主要焊料凸块，而是用于形成至少一个相对应的次要焊料凸块，与该主要焊料凸块连接而形成电性接触。
本发明所述的焊料凸块的制造方法，该主要焊料凸块的高度高于每一该至少一个次要焊料凸块的高度。
本发明所述的焊料凸块的制造方法，该主要焊料凸块的宽度大体上等于该焊垫的宽度。
本发明所述的焊料凸块的制造方法，更包括在置放该掩膜层之前，先形成一下凸块金属化层(under-bumpmetallization layer；下凸块金属化层)于该焊垫上，其中该主要及至少一个次要焊料柱体借着该下凸块金属化层而与该焊垫形成电性接触。
本发明所述的焊料凸块的制造方法，更包括形成较该焊垫宽的该下凸块金属化层，其中该次要焊料柱体形成于该下凸块金属化层凸出该焊垫宽度外的部分上。
本发明所述的焊料凸块的制造方法，该下凸块金属化层是一钛层。
本发明所述的焊料凸块的制造方法，更包括利用电镀或气相沉积法，并以焊料填充该主要及该至少一个次要焊料模仁。
从另一观点来看，本发明是揭示一种焊料凸块结构。其中，焊料凸块形成于具备一焊垫的第一基板上，以电性地及机械性地结合此第一基板与第二基板的焊垫。
此结构包括一个主要焊料凸块，此主要焊料凸块包括一焊料并且具有第一高度及以一底部(nadir)所定义的一基底周边(base perimeter)。
而且，焊料凸块结构更包括至少一个次要焊料凸块，此至少一个次要焊料凸块包括一焊料，此焊料具有一个第二高度，此第二高度小于此第一高度。此外，此次要焊料凸块与此主要焊料凸块在上述底部相连接。
再从另一观点来看，本发明是揭示一种中间结构。此中间结构包括一个主要焊料柱体，此主要焊料柱体包括主要焊料，且此主要焊料柱体被配置于一半导体基板上，与一焊垫形成电性接触。此中间结构包括至少一个次要焊料柱体，此至少一个次要焊料柱体包括次要焊料，且与此主要焊料柱体形成电性接触。此至少一个次要焊料柱体的高度及体积小于此主要焊料柱体的高度及体积。此中间结构进行一再流动步骤时，此至少一个次要焊料柱体熔化并流向此主要焊料柱体而结合，进一步形成一个主要焊料凸块，此主要焊料凸块包括主要焊料及至少一部分的次要焊料。
本发明所述的中间结构，该主要焊料柱体的体积大于每一该至少一个次要焊料柱体的体积。
本发明所述的中间结构，该主要焊料凸块的宽度大体上等于该焊垫的宽度。
本发明所述的中间结构，更包括一下凸块金属化层置于焊垫上，其中该主要及至少一个次要焊料柱体借着该下凸块金属化层而与该焊垫形成电性接触。
本发明所述的中间结构，该下凸块金属化层是一钛层。
附图说明
图1A至图1E为一IC晶片焊垫区的系列剖面图，用以说明现有技术于半导体晶片上制作焊料凸块的流程；
图2A至图2F为一系列剖面图，用以说明本发明一较佳实施例于半导体晶片上制作焊料凸块的流程。
具体实施方式
为让本发明的上述和其他目的、特征和优点能更明显易懂，下文特举出较佳实施例，并配合所附图式，作详细说明如下：
依据本发明的一较佳实施例，图2A至图2F说明制造半导体晶片上的焊料凸块的方法。
首先，图2A说明的是在形成焊料凸块之前的焊料凸块区200，焊料凸块区200的作用是在集成电路晶片与例如印刷电路板的其它元件之间提供电性及机械性接合。如图所示，焊料凸块区200包括一半导体基板205及形成于基板上一部分表面的焊垫210。而且经常会包括一保护层215。如果包括保护层215，则可能会以传统蚀刻技术移除覆盖在焊垫210上的部分的保护层215，以使焊垫210的部分表面外露。
接着，一或多层下凸块金属化层220可能会形成于保护层215上，且与焊垫210形成电性接触。上述下凸块金属化层220可以提供一较大的印迹(footprint)，以便于其上形成焊料凸块，且下凸块金属化层220经常使用可以在焊料凸块形成时提供较强接合的材料，例如钛。
参考图2B，进一步说明以上所述的焊料凸块区200的凸块制程。尤其是，一掩膜层置于焊料凸块区200的表面上，以去除不必要的部分。在一较佳实施例中，此掩膜层是一光致抗蚀剂层225，沉积于焊料凸块区200上。然后，利用典型的传统微影技术将此光致抗蚀剂层225图案化及显影。而未被此光致抗蚀剂层225覆盖的部分则可能被蚀刻掉。在所述的实施例中，下凸块金属化层220的宽度是利用光致抗蚀剂层225及蚀刻制程加以定义。
接下来，图2C是光致抗蚀剂层225的图案的俯视图。如图所示，光致抗蚀剂层225经图案化及显影以便产生形状不同但彼此连通的模仁(molds)，在后续的制程中将会被填以焊料。尤其是，一主要焊料模仁230形成于光致抗蚀剂层225内，且大致位于焊料凸块区200的中心，典型的方式是正好落在焊垫210上(以及下凸块金属化层220上，假如存在的话)。
邻接着主要焊料模仁230的两个次要焊料模仁235a、235b亦于光致抗蚀剂层225内形成。此两个次要焊料模仁235a、235b可以于靠近下凸块金属化层外围的地方形成，并于后续的制程中被填以焊料。虽然实施例所述的模仁230、235a、235b为八角形，但在不脱离本发明所揭示的原则的范围内，模仁230、235a、235b亦可以应用其它形状包括圆形、泪滴形(teardrop)等。
图2D是一俯视图，用以说明经过焊料沉积的焊料凸块区200。在经过图2C所示的光致抗蚀剂层225的图案化及显影制程后，焊料沉积于此主要及次要焊料模仁230、235a、235b内。任何适当的技术皆可使用，但较佳的实施例之一是使用气相沉积制程或电镀的方式沉积焊料。而且任何适当形式的焊料，包括不同材料的合金皆可作为焊料，例如铅、金、银、铜以及锡等，但不限定于这些材料。在一较佳实施例中，焊料包括90％以上的铅，然而这并非必要的。以铅为主成分的合金，也可能因为低熔点而有助于再流动步骤。
在焊料沉积之后，将光致抗蚀剂层225由焊料凸块区200移除，于是形成一主要焊料柱体240及次要焊料柱体245a、245b。而且主要焊料柱体240大致上较次要焊料柱体245a、245b为大，例如焊料柱体245a、245b的体积大致是主要焊料柱体240的10％至90％。
而且，光致抗蚀剂层225的开口中，原先连接主要及次要焊料模仁230、235a、235b的部分，亦形成焊料连接区250(soldjoining regions)。通常，焊料连接区250的尺寸大小及体积大致上比主要及次要焊料模仁230、235a、235b都小。
在另一较佳实施例中，焊料柱体245a、245b直接与主要焊料柱体240相连。在又一较佳实施例中，如图2D所示的焊料柱体240、245a、245b由于先前的焊料模仁230、235a、235b是八角形而呈现相同形状，但是其它形状例如圆形及泪滴型亦有可能。
图2E是说明一经过再流动步骤的焊料凸块区200用于形成焊料凸块的最后形状。尤其是，焊料柱体240、245a、245b被加热到足以熔化的温度。在再流动步骤中，主要焊料柱体240熔成一个主要焊料凸块255，其上半部是属圆形。除了主要焊料凸块255，次要焊料凸块260a、260b也形成并且分别与主要焊料凸块255相连接。
甚者，依据本发明所揭示的原则，焊料柱体245a、245b与主要焊料柱体240底部相连的部分导致其彼此之间在再流动步骤产生结合。结果在再流动步骤时，原先沉积为焊料柱体245a、245b的一部分的焊料移向主要焊料柱体240，如箭头A1、A2所示，因此主要焊料凸块255增加了流动自次要焊料柱体245a、245b的部分体积。
因此，在再流动步骤中当所有焊料熔化然后冷却再硬化至形成最后的焊料凸块255、260a、260b，其中流动自次要焊料柱体245a、245b的焊料增加了主要焊料凸块255整体的尺寸及体积，而传统方法只形成主要焊料柱体240，相较之下其整体的尺寸及体积较小。
而且，主要焊料凸块255的高度约高于次要焊料凸块260a、260b，其原因除了焊料柱体原本的高度即较高之外，还要加上再流动步骤造成的效果。在许多实施例中，次要焊料凸块260a、260b的高度约是主要焊料凸块255的10％至90％。尤其是，主要焊料凸块255的体积及/或其高度足以将第一基板205的焊垫210与第二基板的另一相对应的焊垫结合在一起，以达到电性及机械性接触的效果，而且每一个次要焊料凸块260a、260b的体积及高度皆不足以接触到此第二基板。此一特点在接合技术如覆晶封装技术上是相当有益的。甚者，虽然实施例揭示了两个次要焊料凸块260a、260b(以及两个次要焊料柱体245a、245b)，但并非用以限定次要柱体及凸块的特定数目，因此也可以只用一个次要柱体或凸块。
依据本发明所揭示的原则及制程，图2F用以说明一个已完成的焊料凸块区200的俯视图。其进一步说明在再流动步骤后所形成的此主要及次要焊料凸块255、260a、260b的圆形部分。另外，此主要及次要焊料凸块255、260a、260b之间发生内聚力(Cohesion)的方向再一次以箭头A1、A2表示。而且焊料柱体245a、245b与主要焊料柱体240底部相连的部分亦通过此图加以说明。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
附图中符号的简单说明如下：
8：半导体晶圆
10：晶片焊垫
12：保护层
14A：下凸块金属化层
14B：下凸块金属化层
14C：下凸块金属化层
16：光致抗蚀剂层
17：开口
18A：焊料
18B：焊料凸块
200：焊料凸块区
205：第一基板
210：焊垫
215：保护层
220：下凸块金属化层
225：光罩层
230：焊料模仁
235a：焊料模仁
235b：焊料模仁
240：焊料柱体
245a：焊料柱体
245b：焊料柱体
250：焊料连接区
255：主要焊料凸块
260a：次要焊料凸块
260b：次要焊料凸块
A1：箭头
A2：箭头

Claims (14)

1、一种焊料凸块的制造方法，该焊料凸块置于半导体元件上，所述焊料凸块的制造方法包括下列步骤：
形成一焊垫于一半导体基板上；
配置一掩膜层于该焊垫及该半导体基板上；
于该掩膜层形成一开口，该开口曝露该焊垫的一部分，其中该掩膜层具有一个主要焊料模仁以及至少一个与主要焊料模仁相连接的次要焊料模仁；
以焊料填充该主要焊料模仁以及该至少一个次要焊料模仁，以形成一个相对应的主要焊料柱体及至少一个相对应的次要焊料柱体而与该焊垫形成电性接触；
于填充步骤之后移除该掩膜层；以及
再流动该焊料并透过该焊料的结合以形成一主要焊料凸块，其中该焊料是来自该主要焊料柱体的焊料及至少一部分来自该次要焊料柱体的焊料。
2、根据权利要求1所述的焊料凸块的制造方法，其特征在于：该主要焊料柱体的体积是大于每一该至少一个次要焊料柱体的体积。
3、根据权利要求1所述的焊料凸块的制造方法，其特征在于：该再流动步骤更包括该至少一个次要焊料柱体的一剩余部分，该剩余部分未用于该主要焊料凸块，而是用于形成至少一个相对应的次要焊料凸块，与该主要焊料凸块连接而形成电性接触。
4、根据权利要求3所述的焊料凸块的制造方法，其特征在于：该主要焊料凸块的高度高于每一该至少一个次要焊料凸块的高度。
5、根据权利要求1所述的焊料凸块的制造方法，其特征在于：该主要焊料凸块的宽度等于该焊垫的宽度。
6、根据权利要求1所述的焊料凸块的制造方法，其特征在于：更包括在置放该掩膜层之前，先形成一下凸块金属化层于该焊垫上，其中该主要及至少一个次要焊料柱体借着该下凸块金属化层而与该焊垫形成电性接触。
7、根据权利要求6所述的焊料凸块的制造方法，其特征在于：更包括形成较该焊垫宽的该下凸块金属化层，其中该次要焊料柱体形成于该下凸块金属化层凸出该焊垫宽度外的部分上。
8、根据权利要求6所述的焊料凸块的制造方法，其特征在于：该下凸块金属化层是一钛层。
9、根据权利要求1所述的焊料凸块的制造方法，其特征在于：更包括利用电镀或气相沉积法，并以焊料填充该主要及该至少一个次要焊料模仁。
10、一中间结构，所述中间结构包括：
一个主要焊料柱体，包括主要焊料且被配置于一半导体基板上，与一焊垫形成电性接触；
至少一个次要焊料柱体，包括次要焊料且与该主要焊料柱体形成电性接触，该至少一个次要焊料柱体的高度及体积小于该主要焊料柱体的高度及体积；以及
其中该中间结构进行一再流动步骤时，该主要焊料柱体与该至少一个次要焊料柱体结合，进一步形成一个主要焊料凸块，该主要焊料凸块包括该主要焊料及至少一部分的该次要焊料。
11、根据权利要求10所述的中间结构，其特征在于：该主要焊料柱体的体积大于每一该至少一个次要焊料柱体的体积。
12、根据权利要求10所述的中间结构，其特征在于：该主要焊料凸块的宽度等于该焊垫的宽度。
13、根据权利要求10所述的中间结构，其特征在于：更包括一下凸块金属化层置于焊垫上，其中该主要及至少一个次要焊料柱体借着该下凸块金属化层而与该焊垫形成电性接触。
14、根据权利要求13所述的中间结构，其特征在于：该下凸块金属化层是一钛层。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113200509A (zh) * 2021-04-08 2021-08-03 日月光半导体制造股份有限公司 电子元件及半导体封装装置

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7547623B2 (en) 2002-06-25 2009-06-16 Unitive International Limited Methods of forming lead free solder bumps
JP4232044B2 (ja) * 2005-07-05 2009-03-04 セイコーエプソン株式会社 半導体装置の製造方法
US7994043B1 (en) 2008-04-24 2011-08-09 Amkor Technology, Inc. Lead free alloy bump structure and fabrication method
US9024431B2 (en) 2009-10-29 2015-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die contact structure and method
US8294265B1 (en) * 2010-03-31 2012-10-23 Amkor Technology, Inc. Semiconductor device for improving electrical and mechanical connectivity of conductive pillers and method therefor
US9190348B2 (en) * 2012-05-30 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Scheme for connector site spacing and resulting structures
US9472521B2 (en) 2012-05-30 2016-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Scheme for connector site spacing and resulting structures
US9215809B2 (en) * 2012-08-10 2015-12-15 Smartrac Technology Gmbh Contact bumps methods of making contact bumps
US9373539B2 (en) 2014-04-07 2016-06-21 Freescale Semiconductor, Inc. Collapsible probe tower device and method of forming thereof

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69014871T2 (de) * 1990-07-31 1995-05-24 Ibm Verfahren zur Bildung metallischer Kontaktflächen und Anschlüsse auf Halbleiterchips.
US5268072A (en) * 1992-08-31 1993-12-07 International Business Machines Corporation Etching processes for avoiding edge stress in semiconductor chip solder bumps
US5767580A (en) * 1993-04-30 1998-06-16 Lsi Logic Corporation Systems having shaped, self-aligning micro-bump structures
JPH0817860A (ja) * 1994-06-30 1996-01-19 Oki Electric Ind Co Ltd 電子部品の製造方法
JP3348528B2 (ja) * 1994-07-20 2002-11-20 富士通株式会社 半導体装置の製造方法と半導体装置及び電子回路装置の製造方法と電子回路装置
US5542601A (en) * 1995-02-24 1996-08-06 International Business Machines Corporation Rework process for semiconductor chips mounted in a flip chip configuration on an organic substrate
DE69628161T2 (de) 1995-04-05 2004-03-25 Unitive International Ltd. Eine löthöckerstruktur für ein mikroelektronisches substrat
KR0157906B1 (ko) * 1995-10-19 1998-12-01 문정환 더미볼을 이용한 비지에이 패키지 및 그 보수방법
US6002172A (en) * 1997-03-12 1999-12-14 International Business Machines Corporation Substrate structure and method for improving attachment reliability of semiconductor chips and modules
US6025649A (en) * 1997-07-22 2000-02-15 International Business Machines Corporation Pb-In-Sn tall C-4 for fatigue enhancement
SG71734A1 (en) * 1997-11-21 2000-04-18 Inst Materials Research & Eng Area array stud bump flip chip and assembly process
US6225206B1 (en) * 1999-05-10 2001-05-01 International Business Machines Corporation Flip chip C4 extension structure and process
US6300250B1 (en) 1999-08-09 2001-10-09 Taiwan Semiconductor Manufacturing Company Method of forming bumps for flip chip applications
JP3968554B2 (ja) * 2000-05-01 2007-08-29 セイコーエプソン株式会社 バンプの形成方法及び半導体装置の製造方法
US6333104B1 (en) * 2000-05-30 2001-12-25 International Business Machines Corporation Conductive polymer interconnection configurations
US6551856B1 (en) 2000-08-11 2003-04-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming copper pad redistribution and device formed
US6375062B1 (en) * 2000-11-06 2002-04-23 Delphi Technologies, Inc. Surface bumping method and structure formed thereby
US6426283B1 (en) 2000-12-01 2002-07-30 Taiwan Semiconductor Manufacturing Co., Ltd Method for bumping and backlapping a semiconductor wafer
JP2002190497A (ja) * 2000-12-21 2002-07-05 Sony Corp フリップチップ実装用の封止樹脂
JP3910363B2 (ja) * 2000-12-28 2007-04-25 富士通株式会社 外部接続端子
US6426281B1 (en) 2001-01-16 2002-07-30 Taiwan Semiconductor Manufacturing Company Method to form bump in bumping technology
JP2002261111A (ja) * 2001-03-06 2002-09-13 Texas Instr Japan Ltd 半導体装置及びバンプ形成方法
US6372545B1 (en) 2001-03-22 2002-04-16 Taiwan Semiconductor Manufacturing Company Method for under bump metal patterning of bumping process
US6649507B1 (en) 2001-06-18 2003-11-18 Taiwan Semiconductor Manufacturing Company Dual layer photoresist method for fabricating a mushroom bumping plating structure
US6605524B1 (en) 2001-09-10 2003-08-12 Taiwan Semiconductor Manufacturing Company Bumping process to increase bump height and to create a more robust bump structure
US6756184B2 (en) 2001-10-12 2004-06-29 Taiwan Semiconductor Manufacturing Co., Ltd Method of making tall flip chip bumps
US6583039B2 (en) 2001-10-15 2003-06-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a bump on a copper pad
US6586322B1 (en) 2001-12-21 2003-07-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a bump on a substrate using multiple photoresist layers
TWI245402B (en) * 2002-01-07 2005-12-11 Megic Corp Rod soldering structure and manufacturing process thereof
US6541366B1 (en) 2002-01-08 2003-04-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method for improving a solder bump adhesion bond to a UBM contact layer
US6486054B1 (en) 2002-01-28 2002-11-26 Taiwan Semiconductor Manufacturing Company Method to achieve robust solder bump height
US20040222520A1 (en) * 2002-09-19 2004-11-11 Yonggang Jin Integrated circuit package with flat metal bump and manufacturing method therefor
JP3611561B2 (ja) * 2002-11-18 2005-01-19 沖電気工業株式会社 半導体装置
JP4056424B2 (ja) * 2003-05-16 2008-03-05 シャープ株式会社 半導体装置の製造方法
TWI230994B (en) * 2004-02-25 2005-04-11 Via Tech Inc Circuit carrier
US7045893B1 (en) * 2004-07-15 2006-05-16 Amkor Technology, Inc. Semiconductor package and method for manufacturing the same
US20060046434A1 (en) * 2004-08-26 2006-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing lead precipitation during wafer processing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113200509A (zh) * 2021-04-08 2021-08-03 日月光半导体制造股份有限公司 电子元件及半导体封装装置

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