CN1684253A - 半导体器件的凸点结构和制造方法 - Google Patents

半导体器件的凸点结构和制造方法 Download PDF

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Publication number
CN1684253A
CN1684253A CNA2005100649588A CN200510064958A CN1684253A CN 1684253 A CN1684253 A CN 1684253A CN A2005100649588 A CNA2005100649588 A CN A2005100649588A CN 200510064958 A CN200510064958 A CN 200510064958A CN 1684253 A CN1684253 A CN 1684253A
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China
Prior art keywords
bump structure
semiconductor device
sidewall
salient point
substrate
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CNA2005100649588A
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CN100527398C (zh
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权容焕
李忠善
姜思尹
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020040025853A external-priority patent/KR100632472B1/ko
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Publication of CN1684253A publication Critical patent/CN1684253A/zh
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Abstract

本发明涉及一种半导体器件和制造该器件的方法，该器件使用凸点结构，其包括多个第一方向上沿衬底排列的凸点结构。每个凸点结构在第一方向上具有的宽度大于相继排列的凸点结构之间的间距，且至少一个凸点结构具有面对第一方向的非导电侧壁。

Description

半导体器件的凸点结构和制造方法
技术领域
本发明涉及半导体器件的凸点结构和制造方法。
背景技术
存在多种用于在半导体芯片或封装和电路板或其它衬底之间提供电连接的不同技术。在许多这些技术中的现在的潮流是使用焊料凸点(solderbump)以形成电连接来取代引线接合(wiring bonding)。例如，在如带载封装(TCP)、膜上芯片(COF)和玻璃上芯片(COG)的技术中使用凸点。如TCP和COF的技术被更广泛地称为带式自动焊接(TAB)。
虽然通过允许在焊料凸点之间的间隔比引线接合之间的间隔减小，凸点提供了优于引线接合的优点，但是甚至凸点技术也面临凸点之间的间隔上的潜在的限制。例如，在COG技术中，半导体芯片(例如液晶显示器驱动器集成电路(IC)封装)可以直接焊接到LCD基板上。在该技术中，在LCD基板的焊盘和驱动器IC封装的相关凸点之间设置ACF(各向异性导电膜)带以形成电连接。ACF带包含在绝缘材料中嵌入的导电颗粒。导电颗粒在LCD基板的焊盘和焊料凸点之间提供电连接。但是当凸点之间的间隙变小时，在ACF带中的颗粒可以提供凸点之间的电连接；因此造成短路。
发明内容
本发明提供了一种去除在半导体芯片或封装的焊料凸点之间的间隔上的障碍物的凸点结构。如此，本发明允许更小和更薄的半导体器件。
在一示范性实施例中，沿衬底在第一方向上排列多个凸点结构。每个凸点结构在第一方向上的宽度大于相继排列的凸点结构的间距。该间距可以认为是在衬底沿第一方向相继排列的凸点结构的相对侧壁的平面之间的测量的间隙。至少一个凸点结构具有在第一方向上面对的非导电侧壁。因为该侧壁为非导电的，在该凸点和相邻于非导电侧壁的凸点之间设置的导电颗粒不会在两个凸点之间形成短路。
在一示范性实施例中，每个凸点结构具有至少一非导电侧壁面向第一方向。
在另一示范性实施例中，每个凸点结构具有两个相对面对的非导电侧壁面向第一方向。
在再一示范性实施例中，每个凸点结构具有一非导电侧壁面向第一方向和一导电侧壁面向第一方向，使得导电侧壁不面对另一凸点结构的导电侧壁。
在又一示范性实施例中，凸点结构阵列从第一型至第二型交替。第一型的凸点结构具有两个相对面对的非导电侧壁面向第一方向，而第二型的凸点结构具有两个相对面对的导电侧壁面向第一方向。
对于上述实施例的任意一个，可以沿衬底在第二方向上彼此偏移地设置相继排列的凸点结构。
本发明的示范性实施例也包括多个沿衬底第一方向上排列的凸点和多个在第二方向上形成的导电线。每个导电线与凸点之一相关，而且每个导电线设置在相关凸点的顶表面和凸点的两个相对面对的侧壁之上；两个相对面对的侧壁面对第二方向。每个导电线从两个相对面对的侧壁的每个在衬底上延伸。因此，导电线有助于保持相关凸点附着于衬底。
其它本发明的示范性实施例提供了形成上述实施例的方法。
附图说明
从以下给出的详细描述和附图，本发明将变得明显易懂。附图中，相似的元件由相似的附图标记指示。只通过说明的方法给出详细描述和附图，而因此不用于本发明的限制。
图1图示了本发明的示范性实施例的具有凸点结构的半导体器件；
图2图示了在图1所示的衬底沿线II-II的剖面图；
图3图示了在图1所示的衬底沿线III-III的剖面图；
图4图示了本发明的示范性实施例的具有凸点结构的半导体器件；
图5图示了在图4所示的衬底沿线V-V的剖面图；
图6图示了本发明的示范性实施例的具有凸点结构的半导体器件；
图7图示了在图4所示的衬底沿线VII-VII的剖面图；
图8图示了本发明的示范性实施例的具有凸点结构的半导体器件；
图9图示了具有三组凸点结构的半导体器件的俯视图；
图10A-15B图示了本发明的凸点结构的制造方法的实施例，其中图10A、11A、12、13A、14和15A表现在制造工艺期间的衬底的剖面图，而图10B、11B、13B和15B表现在制造工艺期间的衬底的俯视图。
具体实施方式
本发明提供一种去除半导体芯片或封装的焊料凸点之间的间隔上的障碍物的凸点结构。如此，本发明允许更小和更薄的半导体器件。首先，将描述几个本发明的结构实施例，随后描述本发明的形成凸点结构的方法。
第一结构实施例
图1图示了本发明的示范性实施例的具有凸点结构的半导体器件。如所示，在衬底200上的绝缘层202上在由双向箭头A指示的第一方向上排列凸点结构100。每个凸点结构100包括非导电凸点102。非导电凸点102具有两个面对第一方向的相对面对的侧壁104和两个面对第二方向的相对面对的侧壁106，第二方向基本垂直于第一方向，由双向箭头B指示。
在一示范实施例中，每个凸点102具有2至30μm的高度H、10至50μm的宽度Wb和20至200μm的长度Lb。
每个凸点结构100也包括在与之相关的凸点102的顶表面和在第二方向上面对的每个侧壁106上设置的导电层108。在凸点102上的导电层108形成导电线110的一部分，导电线110从一侧壁104在衬底200上方延伸较短距离，而从另一侧壁106在衬底200上方延伸较长距离。如所示，导电线110在第二方向上延伸。导电线110的较长延伸通向相关的芯片焊盘204，其中导电层110电连接于相关的焊盘204。可以理解，焊盘204提供导电线110和在衬底200上形成的电路(未示出)之间的电连接。
图2图示了在图1所示的衬底沿线II-II的剖面图而图3图示了在图1所示的衬底沿线III-III的剖面图。虽然为了清晰的目的在图1中未显示，本发明的该实施例的凸点结构还包括在衬底200的一部分上形成的钝化层180，如图2和3所示。
图2显示了图1中的相邻凸点结构100之间的间距PG。间距PG是两个凸点结构之间的距离；且更具体地，可以是在衬底200或钝化层180沿第一方向上在相继排列的凸点结构100的相对侧壁104所在的平面之间测量的间隙。在本实施例中，凸点结构100的宽度Wb大于间距PG。例如，间距PG可以大约为10μm。
因为间距PG小于凸点结构100的宽度Wb，当使用例如ACF带时，可能会发生短路。但是，因为凸点结构100面向第一方向的侧壁104为非导电的，所以防止了此类短路。因此，本发明提供了去除在半导体芯片或封装的焊料凸点之间的间隔上的障碍物的凸点结构。如此，本发明允许更小和更薄的半导体器件。
第二结构实施例
图4图示了本发明的示范性实施例的具有凸点结构的半导体器件，而图5图示了在图4所示的衬底沿线V-V的剖面图。如所示，图4的实施例除了凸点结构之外与图1的实施例相同。在图4的实施例中，每个凸点结构100’与图1所示的凸点结构100相同，只是导电层108覆盖了相同的在第一方向上面对的侧壁104之一。如此，一凸点结构100的导电侧壁104面对另一凸点结构100的非导电侧壁104。
因为在第一方向上面对的凸点结构100的侧壁104之一是非导电的，所以避免了短路。因此，本发明提供了去除在半导体芯片或封装的焊料凸点之间的间隔上的障碍物的凸点结构。如此，本发明允许更小和更薄的半导体器件。
第三结构实施例
图6图示了本发明的示范性实施例的具有凸点结构的半导体器件，而图7图示了在图6所示的衬底沿线VII-VII的剖面图。如所示，图6的实施例除了凸点结构之外与图1的实施例相同。在图6的实施例包括交替的两种类型的凸点结构。第一型凸点结构100与图1所示的凸点结构100相同。第二型凸点结构100”与图1所示的凸点结构100相同，除了导电层108覆盖在第一方向上面对的两个侧壁104之外。但是，因为凸点结构的两个类型沿衬底200的第一方向交替，第二型凸点结构100”的导电侧壁104面对第一型凸点结构100的非导电侧壁104。因此避免了短路。因此，本发明提供了去除在半导体芯片或封装的焊料凸点之间的间隔上的障碍物的凸点结构。如此，本发明允许更小和更薄的半导体器件。
第四结构实施例
图8图示了本发明的示范性实施例的具有凸点结构的半导体器件。如所示，图8中的凸点结构与图1所示的凸点结构相同，除了相继排列的凸点结构在第二方向上从彼此偏移之外。更具体地，凸点结构100被分为两组。第一组中的凸点结构100-1具有比第二组中的凸点结构100-2短的导电线110，且第一组的凸点结构100-1与第二组的凸点结构100-2在第一方向上交替。
应当理解，如图8所示，偏移凸点结构100进一步有助于防止可能的短路。因为连续的凸点结构100没有排成一行，短路不易发生，且因为排成一行的凸点结构之间的间隙大(例如，大于20μm)，短路不易发生。
虽然使用图1的凸点结构100显示和描述图8的实施例，但是应当理解该实施例可以结合在前描述的实施例的任意一个凸点结构。
另外，虽然已经图示了两组排成一行的凸点结构，但是应当理解可以形成多于两组凸点结构，每个从其它的组偏移。图9图示了具有三组凸点结构100的半导体器件的俯视图。
方法实施例
接下来，将描述本发明的具有凸点结构的半导体器件的制造方法。只为了举例的目的，将参照图1所示的凸点结构100的制造描述该方法。将参照图10A-15B描述该方法，其中图10A、11A、12、13A、14和15A表现在制造工艺期间的衬底的剖面图，而图10B、11B、13B和15B表现在制造工艺期间的衬底的俯视图。
如图10A和10B所示，工艺由具有芯片焊盘204形成于其上的衬底200开始。为了清晰的目的，只显示了单一的芯片焊盘。同样，为了清晰，未显示芯片焊盘204电连接的器件、电路等。第一钝化层202形成于衬底200上且被构图以暴露芯片焊盘204的部分225。第一钝化层202可以是SiN、SiO2或SiN+SiO2，且可以由化学气相沉积(CVD)形成。
之后，例如，通过旋涂在衬底上形成如聚酰亚胺、BCB(苯并环丁烷)、PBO(聚苯唑)、光敏树脂等的介电层。介电层可以形成至2-30μm的厚度。然后，使用掩模构图介电层以形成如图11A和图11B所示的非导电凸点102。凸点102可以具有2-30μm的高度，且可以具有10-50μm的宽度和50-200μm的长度。在一示范实施例中，宽度是20μm且长度是100μm。
如图12所示，在衬底200上形成第一金属层140。第一金属层140可以具有0.05-1μm的厚度。第一金属层140可以由任何具有良好粘接性能和低电阻的金属形成，如TiW、Cr、Cu、Ti、Ni、NiV、Pd、Cr/Cu、TiW/Cu、TiW/Au、NiV/Cu等。同样，第一金属层140可以通过压力气相沉积(PVD)、电镀或无电镀(electroless plating)工艺等形成。
之后，如图13A和13B所示，在衬底200上形成光致抗蚀剂图案150。光致抗蚀剂图案150形成如图13B所示的掩模。使用该掩模，在由该掩模暴露的衬底200的部分上形成第二金属层160。第一和第二金属层140和160形成导电层108和导电线110。
第二金属层160可以形成至1-10μm的厚度。在一示范实施例中，第一和第二金属层140和160的总厚度小于10μm。第二金属层160可以通过例如电镀由Au、Ni、Cu、Pd、Ag、Pt等或这些金属的多层形成。
之后，如图14所示，去除光致抗蚀剂图案150，保持凸点结构100电连接于焊盘204。然后第二钝化层180可以形成于衬底200上且被构图以暴露凸点结构100，如图15A和15B所示。第二钝化层可以为聚酰亚胺、BCB、PBO、光敏树脂等，且可以由旋涂工艺涂覆。
如上描述的凸点结构和制造方法可以应用于任何使用凸点的技术，如带载封装(TCP)、膜上芯片(COF)和玻璃上芯片(COG)。而且，如上描述的凸点结构和制造方法可以应用于制造任何半导体芯片或封装(例如，液晶显示器(LCD)驱动器集成电路(IC)封装)。
如此描述本发明，显然本发明可以以许多的方法改变。这样的改变不认为是背离本发明，且所有这样的改变意在包括于本发明的范围内。

Claims (49)

1.一种半导体器件，包括：
沿衬底在第一方向上排列的多个凸点结构，每个凸点结构在第一方向上的宽度大于相继排列的凸点结构之间的间距，且至少一个凸点结构具有在第一方向上面对的非导电侧壁。
2.如权利要求1所述的半导体器件，其中每个凸点结构具有至少一面向所述第一方向的非导电侧壁。
3.如权利要求2所述的半导体器件，其中每个凸点结构具有两个面向所述第一方向的相对面对的非导电侧壁。
4.如权利要求3所述的半导体器件，其中每个凸点结构包括设置于所述凸点结构的顶表面和至少一面对第二方向的侧壁上的导电层，所述导电层从面对所述第二方向的侧壁在所述衬底的一部分上在第二方向上延伸。
5.如权利要求4所述的半导体器件，其中每个导电层电连接于所述衬底上的相关焊盘，设置所述相关焊盘远离所述相关凸点结构。
6.如权利要求4所述的半导体器件，其中每个导电层至少包括下金属层和上金属层。
7.如权利要求4所述的半导体器件，其中相继排列的凸点结构沿所述衬底在所述第二方向上从彼此偏离。
8.如权利要求7所述的半导体器件，其中所述第二方向基本垂直于所述第一方向。
9.如权利要求2所述的半导体器件，其中每个凸点结构具有一个面向所述第一方向的非导电侧壁和一个面向所述第一方向的导电侧壁，使得所述导电侧壁不面对另一凸点结构的导电侧壁。
10.如权利要求9所述的半导体器件，其中每个凸点结构包括设置于所述凸点结构的顶表面和至少一面对第二方向的侧壁上的导电层，所述导电层从面对所述第二方向的侧壁在所述衬底的一部分上在第二方向上延伸。
11.如权利要求10所述的半导体器件，其中每个导电层电连接于所述衬底上的相关焊盘，设置所述相关焊盘远离所述相关凸点结构。
12.如权利要求10所述的半导体器件，其中每个导电层至少包括下金属层和上金属层。
13.如权利要求10所述的半导体器件，其中相继排列的凸点结构沿所述衬底在所述第二方向上从彼此偏离。
14.如权利要求10所述的半导体器件，其中所述第二方向基本垂直于所述第一方向。
15.如权利要求1所述的半导体器件，其中凸点结构的阵列从第一型至第二型交替，所述第一型的凸点结构具有两个相对面对的面向所述第一方向的非导电侧壁，而所述第二型的凸点结构具有的每个侧壁为导电的。
16.如权利要求15所述的半导体器件，其中每个凸点结构包括设置于所述凸点结构的顶表面和所述凸点结构的至少一个面对第二方向的侧壁上的导电层，所述导电层从面对所述第二方向的侧壁在所述衬底的一部分上在第二方向上延伸。
17.如权利要求16所述的半导体器件，其中每个导电层电连接于所述衬底上的相关焊盘，设置所述相关焊盘远离所述相关凸点结构。
18.如权利要求16所述的半导体器件，其中每个导电层至少包括下金属层和上金属层。
19.如权利要求16所述的半导体器件，其中相继排列的凸点结构沿所述衬底在所述第二方向上从彼此偏离。
20.如权利要求19所述的半导体器件，其中所述第二方向基本垂直于所述第一方向。
21.如权利要求1所述的半导体器件，其中每个凸点结构包括设置于所述凸点结构的顶表面和所述凸点结构的至少一面对第二方向的侧壁上的导电层，所述导电层从面对第二方向的侧壁在所述衬底的一部分上在所述第二方向上延伸。
22.如权利要求21所述的半导体器件，其中每个导电层电连接于所述衬底上的相关焊盘，设置所述相关焊盘远离所述相关凸点结构。
23.如权利要求21所述的半导体器件，其中每个导电层至少包括下金属层和上金属层。
24.如权利要求23所述的半导体器件，其中所述下金属层具有0.05至1μm的厚度，且所述上金属层具有1至10μm的厚度。
25.如权利要求23所述的半导体器件，其中所述下金属层包括TiW、Cr、Cu、Ti、Ni、NiV、Pd、Cr/Cu、TiW/Cu、TiW/Au、NiV/Cu的至少一种，而且所述上金属层包括Au、Ni、Cu、Pd、Ag和Pt的至少一种。
26.如权利要求1所述的半导体器件，其中设置相继排列的凸点结构沿衬底在第二方向上从彼此偏离。
27.如权利要求26所述的半导体器件，其中所述第二方向基本垂直于所述第一方向。
28.如权利要求1所述的半导体器件，其中所述凸点结构具有10至50μm的宽度。
29.如权利要求1所述的半导体器件，其中每个凸点结构包括非导电凸点和设置于所述非导电凸点的至少一顶表面上的导电材料。
30.如权利要求29所述的半导体器件，其中每个凸点具有2-30μm的高度。
31.如权利要求29所述的半导体器件，其中每个凸点结构包括在两个相对面对的面对第二方向的侧壁上设置的导电材料，且所述导电材料从两个相对面对的侧壁的每一个在衬底上延伸。
32.如权利要求29所述的半导体器件，其中每个凸点包括聚酰亚胺、苯并环丁烷、聚苯唑和光敏树脂之一。
33.一种半导体器件，包括：
多个凸点，沿衬底在第一方向上排列；
多个导电线，在第二方向上形成，每个导电线与凸点之一相关，每个导电线设置于所述相关凸点的顶表面和所述凸点的两个相对面对的面对所述第二方向的侧壁上，且每个导电线从两个相对面对的侧壁的每一个在所述衬底上延伸。
34.一种半导体器件，包括：
多个凸点，沿衬底在第一方向上排列，每个凸点在所述第一方向上具有的宽度大于相继排列的凸点之间的间距；和
多个导电线，在第二方向上形成，每个导电线与凸点之一相关，每个导电线设置于所述相关凸点的顶表面和所述相关凸点的一面对所述第二方向的侧壁上，且每个导电线从面对第二方向的侧壁在所述衬底上延伸。
35.一种形成半导体器件的方法，包括：
形成多个凸点结构，所述凸点结构沿衬底在第一方向上排列，每个凸点结构在所述第一方向上具有的宽度大于相继排列的凸点结构之间的间距，且至少一凸点结构具有的面对所述第一方向的侧壁为非导电的。
36.如权利要求35所述的方法，其中形成步骤包括：
形成多个凸点，所述凸点沿所述衬底在所述第一方向上排列；和
在第二方向上形成与每个凸点相关的导电线，每个导电线设置于所述凸点的顶表面和所述凸点的对所述第二方向的一侧壁上，且每个导电线从面对所述第二方向的所述侧壁在衬底上延伸。
37.如权利要求35所述的方法，其中所述形成多个凸点的步骤包括：
在所述衬底上旋涂凸点材料；且
构图所述凸点材料以形成所述多个凸点。
38.如权利要求37所述的方法，其中每个凸点包括聚酰亚胺、苯并环丁烷、聚苯唑和光敏树脂之一。
39.如权利要求37所述的方法，其中所述构图步骤形成所述多个凸点使得每个凸点具有10至50μm的宽度。
40.如权利要求37所述的方法，其中所述构图步骤形成所述多个凸点使得每个凸点具有2-30μm的高度。
41.如权利要求35所述的方法，其中每个导电线至少包括下金属层和上金属层。
42.如权利要求41所述的方法，其中所述下金属层具有0.05至1μm的厚度，且所述上金属层具有1至10μm的厚度。
43.如权利要求41所述的方法，其中所述下金属层包括TiW、Cr、Cu、Ti、Ni、NiV、Pd、Cr/Cu、TiW/Cu、TiW/Au、NiV/Cu的至少一种，而且所述上金属层包括Au、Ni、Cu、Pd、Ag和Pt的至少一种。
44.如权利要求41所述的方法，其中所述形成导电线的步骤包括：
形成所述下金属层；和
用上金属层材料电镀所述下金属层以形成所述上金属层。
45.如权利要求35所述的方法，其中每个凸点结构至少具有一个面对所述第一方向的非导电侧壁。
46.如权利要求35所述的方法，其中每个凸点结构具有两个相对面对的面对所述第一方向的非导电侧壁。
47.如权利要求35所述的方法，其中每个凸点结构具有一个面对所述第一方向的非导电侧壁和一个面对所述第一方向的导电侧壁，使得所述导电侧壁不面对另一凸点结构的导电侧壁。
48.如权利要求35所述的方法，其中所述凸点结构的阵列从第一型至第二型交替，所述第一型的凸点结构具有两个相对面对的面对所述第一方向的非导电侧壁，而所述第二型的凸点结构的每个侧壁都是导电的。
49.一种形成半导体器件的方法，包括：
形成多个凸点，所述凸点沿衬底在第一方向上排列，每个凸点在所述第一方向上具有的宽度大于相继排列的凸点之间的间距；和
在第二方向上形成多个导电线，每个导电线与凸点之一相关，每个导电线设置于所述相关凸点的顶表面和所述相关凸点的面对所述第二方向的侧壁上，且每个导电线从面对第二方向的所述侧壁在衬底上延伸。
CNB2005100649588A 2004-04-14 2005-04-12 半导体器件的凸点结构和制造方法 Expired - Fee Related CN100527398C (zh)

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