CN1301544C - 半导体装置的制造方法 - Google Patents
半导体装置的制造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 229920005989 resin Polymers 0.000 claims abstract description 53
- 239000011347 resin Substances 0.000 claims abstract description 53
- 239000011888 foil Substances 0.000 claims abstract description 48
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000007789 sealing Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000009434 installation Methods 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 238000003475 lamination Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- ORQBXQOJMQIAOY-UHFFFAOYSA-N nobelium Chemical compound [No] ORQBXQOJMQIAOY-UHFFFAOYSA-N 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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Abstract
一种半导体装置的制造方法,其提供连接可靠性优良的半导体装置,其包括:通过蚀刻除构成端子(12)的位置以外的第一导电箔(10),在第一导电箔表面形成凸状地突起的端子部的工序;使树脂片(14)重叠在第一导电箔上,以埋入端子部的工序;通过将树脂层(15)作为下面,使背面形成有树脂层的第二导电箔(16)重叠在树脂片上,构成层积片(18)的工序;通过蚀刻第二导电箔形成导电图案(17)的工序;将导电图案和端子部电连接的工序;将端子部相互间电分离的工序;在层积片上固定半导体元件(22),将半导体元件和导电图案电连接的工序;在层积片表面形成密封树脂(24),以覆盖半导体元件的工序。
Description
技术领域
本发明涉及具有支承衬底的半导体装置。
背景技术
参照图12说明现有的安装衬底及半导体装置。图12(A)是半导体装置100的剖面图,图12(B)是其背面图(参照专利文献1)。
参照图12(A),在由玻璃环氧树脂等构成的支承衬底101上面形成由铜箔等构成的电极104。在支承衬底101的背面形成背面电极105,并利用敷金属夹层孔106和电极104连接。另外,利用镀膜109覆盖电极104及背面电极105。
作为半导体元件的半导体元件102被固定在支承衬底101上,并介由金属细线103和电极104连接。另外,形成覆盖半导体元件102的密封树脂107。
参照图12(B),在支承衬底101的背面与外周部平行并排列两列设有背面电极105。
专利文献1
特开平11-233688号公报(参照图7)
发明内容
在所述的半导体装置100中,由于采用支承衬底101,故限制了其薄型化及小型化。另外,由于在使用状态下温度变化会产生热应力,因此自背面电极105至电极104的连接路经的可靠性有问题。支承衬底101为了在制造工序中使电极104及背面电极105粘合是必需的,难以不使用该衬底制造半导体装置。另外,由于支承衬底101具有吸收热应力的作用,故难以不使用支承衬底101构成半导体装置。
本发明是鉴于所述的问题点而开发的,本发明的主要目的在于,提供小型化及薄型化且端子部的连接可靠性优良的半导体装置的制造方法。
本发明包括:通过有选择地蚀刻第一导电箔,在所述第一导电箔表面形成凸状地突起的端子部的工序;使树脂片重叠在所述第一导电箔上,以埋入所述端子部的工序;通过使第二导电箔重叠在所述树脂片构成层积片上的工序;通过蚀刻所述第二导电箔形成导电图案的工序;将所述导电图案和所述端子部电连接的工序;将所述端子部相互间电分离的工序;在所述层积片上固定半导体元件,将所述半导体元件和所述导电图案电连接的工序;在所述层积片表面形成密封树脂,以覆盖所述半导体元件的工序。
本发明通过由未形成所述端子部的背面蚀刻所述第一导电箔,将所述端子相互之间电分离。
本发明所述树脂片由可溶树脂构成,通过除去所述树脂片,露出所述端子部的侧面。
本发明所述半导体元件由面朝上接合法连接,并介由金属细线将所述半导体元件的电极和所述导电图案连接。
另外,本发明所述半导体元件通过倒装法安装,并利用补片电极将所述半导体元件的电极和所述导电图案连接。
附图说明
图1是说明本发明半导体装置制造方法的剖面图(A)、剖面图(B);
图2是说明本发明半导体装置制造方法的剖面图;
图3是说明本发明半导体装置制造方法的剖面图;
图4是说明本发明半导体装置制造方法的剖面图;
图5是说明本发明半导体装置制造方法的剖面图;
图6是说明本发明半导体装置制造方法的剖面图;
图7是说明本发明半导体装置制造方法的剖面图;
图8是说明本发明半导体装置制造方法的剖面图;
图9是说明本发明半导体装置制造方法的剖面图;
图10是说明本发明半导体装置制造方法的剖面图;
图11是说明本发明半导体装置制造方法的剖面图;
图12是说明现有的半导体装置的剖面图(A)、背面图(B)。
具体实施方式
以下,参照附图详细说明本发明半导体装置的制造方法。本发明半导体装置的制造方法包括:通过蚀刻除构成端子12的位置以外的第一导电箔10,在第一导电箔10表面形成凸状地突起的端子部12的工序;使树脂片14重叠在第一导电箔10上,以埋入端子部12的工序;通过将树脂层15作为下面,使背面形成有树脂层15的第二导电箔16重叠在树脂片14上,构成层积片18的工序;通过蚀刻第二导电箔16形成导电图案17的工序;将导电图案17和端子部12电连接的工序;将端子部12相互间电分离的工序;在层积片18上固定半导体元件22,而后将半导体元件22和导电图案17电连接的工序;在层积片18表面形成密封树脂24,以覆盖半导体元件22的工序。以下,说明所述各工序。
参照图1,本发明的第一工序在于,通过蚀刻除构成端子12的位置以外的第一导电箔10,在第一导电箔10表面形成凸状地突起的端子部12。
参照图1(A),准备以铜或铝等金属为主材料的第一导电箔10。第一导电箔10的厚度在以后的工序中被设定在可形成端子部12的范围内。而后,在除预定形成端子部12的位置以外的区域的第一导电箔10表面形成抗蚀剂11。通过进行湿式蚀刻或干式蚀刻,凸状地形成端子部12。
参照图1(B),在自抗蚀剂11露出的位置的第一导电箔10上形成分离槽13。特别是在进行湿式蚀刻时,端子部12的侧面形成弯曲,提高在以后的工序中和树脂材料的粘附强度。由此,端子部12被凸状地形成。进行蚀刻后将抗蚀剂11剥离。
参照图2,本发明的第二工序在于,使树脂片14重叠在第一导电箔10上,以埋入端子部12。树脂片14可采用在玻璃纤维布中含浸树脂的B级预浸树脂片。另外,该重叠作业可通过真空按压进行。
参照图3,本发明的第三工序在于,通过将树脂层15作为下面,使背面形成有树脂层15的第二导电箔16重叠在树脂片14上,构成层积片18。在此,树脂层15可采用所述的预浸树脂片。第二导电箔16可采用比第一导电箔更薄的导电箔,以形成微细的图案。另外,第二导电箔16的材料可采用和第一导电箔10相同的,以铜或铝为主体的金属。在该工序中,形成利用树脂层积具有端子部12的第一导电箔10和第二导电箔16而构成的层积片18。
参照图4,本发明的第四工序在于,通过蚀刻第二导电箔16形成导电图案17。在此,也通过使用抗蚀剂的干式蚀刻或湿式蚀刻选择性地除去第二导电箔16。
参照图5及图6,本发明的第五工序在于,将导电图案17和端子部12电连接。首先,参照图5,穿设贯通导电图案17、树脂层15及树脂片的通孔19。形成通孔19的方法有使用蚀刻和激光的方法。首先,利用蚀刻局部地除去形成通孔19的位置的导电图案17。而后,将除去的导电图案17下方的树脂层15及树脂片14利用激光照射除去。在此使用的激光可采用二氧化碳激光。
其次,参照图6,在利用所述方法形成的通孔19中形成连接部20。首先,清洗除去由先前工序形成的通孔19的树脂残渣(デスミア)。而后,利用无电解镀敷或电镀在通孔19的侧面形成由铜等金属构成的连接部20。利用该连接部20将导电图案17和端子部12电连接。在此,也可以进行填充镀敷,利用镀敷材料填充通孔19。
参照图7,本发明的第六工序在于,将端子部12相互间电分离。
具体地说,通过除去第一导电箔10的背面直至分离槽13内填充的树脂片14露出,将各端子部12电气独立。该工序可通过将第一导电箔10的背面通过整面地湿式蚀刻进行。另外,露出端子部12的位置以外的层积片18的背面利用抗蚀剂21覆盖。除和内装的元件电连接的位置以外,导电图案17的表面也可以利用抗蚀剂21覆盖。
参照图8,本发明的第七工序在于,将半导体元件22和导电图案17电连接,在层积片18的表面形成密封树脂24,以覆盖半导体元件22。利用粘结剂在层积片18上固定半导体元件22,并介由金属细线23电连接半导体元件22的电极和导电图案17。密封树脂24在层积片18的表面形成,覆盖半导体元件22及金属细线23。
由所述工序制造半导体装置30A,在露出的端子部12背面粘附焊锡等焊剂,在安装衬底等面装。另外,通过在半导体元件22下方形成散热电极26,可提高装置全体的散热性。另外,半导体装置30A具有多层配线结构,由薄的第二导电箔形成的导电图案17可形成微细的电路图案。由于构成端子部12的第一导电箔10较厚地形成,故直至进行树脂密封的工序之前具有支承整体的作用。
参照图9说明另一实施例的半导体装置30B的结构。在此,树脂片14被除去,形成端子部12侧面露出的结构。因此,形成具有PIN型端子部12的半导体装置。此时,树脂片14由碱可溶树脂构成,在进行各端子部12的分离后,通过由碱性药剂熔融树脂片14除去树脂片14。
参照图10说明另一实施例的半导体装置30C。在此,不形成散热用电极,而网状形成PIN型端子部12。从而,可提供具有多引脚结构的半导体装置。
参照图11说明另一实施例的半导体装置30C。在此,利用倒装法安装半导体元件22,并介由补片电极25和导电图案17电连接。如上所述,由于导电图案17可形成微细的图案,因此,即使半导体元件22的电极间距窄,也可以充分地对应。
另外,所述的本实施例可在不脱离本发明要旨的范围内进行种种变更。例如,可进行如下变更。
参照图2,在此,在第一导电箔上层积了树脂片14,但在此,可采用和铜箔层积的树脂片14。由此,参照图3,树脂片14和树脂层15由相同的树脂材料构成。从而,可减少构成半导体装置的构成要素。
在本发明中,可得到如下所示的效果。
介由树脂层层积构成端子部12的第一导电箔10和构成导电图案的第二导电箔16,构成多层的层积片18。从而,不需要现有例的支承衬底即可制造有多层配线结构的半导体装置。
另外,层积第一导电箔10和第二导电箔16的树脂采用可溶树脂,可得到端子部侧面露出的PIN型端子结构。
Claims (5)
1、一种半导体装置的制造方法,其特征在于,其包括:通过有选择地蚀刻第一导电箔,在所述第一导电箔表面形成凸状地突起的端子部的工序;使树脂片重叠在所述第一导电箔上,将所述端子部埋入的工序;通过使第二导电箔重叠在所述树脂片上构成层积片的工序;通过蚀刻所述第二导电箔形成导电图案的工序;将所述导电图案和所述端子部电连接的工序;将所述端子部相互间电分离的工序;在所述层积片上固定半导体元件,将所述半导体元件和所述导电图案电连接的工序;在所述层积片表面形成密封树脂,覆盖所述半导体元件的工序。
2、如权利要求1所述的半导体装置的制造方法,其特征在于,通过由未形成所述端子部的背面蚀刻所述第一导电箔,将所述端子相互之间电分离。
3、如权利要求1所述的半导体装置的制造方法,其特征在于,所述树脂片由可溶树脂构成,通过除去所述树脂片,露出所述端子部的侧面。
4、如权利要求1所述的半导体装置的制造方法,其特征在于,所述半导体元件由面朝上接合法连接,并介由金属细线将所述半导体元件的电极和所述导电图案连接。
5、如权利要求1所述的半导体装置的制造方法,其特征在于,所述半导体元件通过倒装法安装,并介由补片电极将所述半导体元件的电极和所述导电图案连接。
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US7459345B2 (en) * | 2004-10-20 | 2008-12-02 | Mutual-Pak Technology Co., Ltd. | Packaging method for an electronic element |
JP4961848B2 (ja) * | 2006-06-12 | 2012-06-27 | 日本電気株式会社 | 金属ポストを有する配線基板、半導体装置及び半導体装置モジュールの製造方法 |
SG140574A1 (en) * | 2006-08-30 | 2008-03-28 | United Test & Assembly Ct Ltd | Method of producing a semiconductor package |
JP5081578B2 (ja) * | 2007-10-25 | 2012-11-28 | ローム株式会社 | 樹脂封止型半導体装置 |
CN102054814B (zh) * | 2009-11-06 | 2012-07-25 | 欣兴电子股份有限公司 | 无核心层封装基板及其制法 |
TWI554171B (zh) * | 2014-09-15 | 2016-10-11 | 欣興電子股份有限公司 | 埋入式導電配線的製作方法 |
JP6577373B2 (ja) * | 2016-01-18 | 2019-09-18 | 新光電気工業株式会社 | リードフレーム及びその製造方法、半導体装置 |
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US6329711B1 (en) * | 1995-11-08 | 2001-12-11 | Fujitsu Limited | Semiconductor device and mounting structure |
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JP3481444B2 (ja) * | 1998-01-14 | 2003-12-22 | シャープ株式会社 | 半導体装置及びその製造方法 |
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US6329711B1 (en) * | 1995-11-08 | 2001-12-11 | Fujitsu Limited | Semiconductor device and mounting structure |
JPH11233688A (ja) * | 1997-12-02 | 1999-08-27 | Lg Semicon Co Ltd | 半導体パッケージ用基板とそれを用いたlga半導体パッケージ及びその製造方法 |
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