CN1392600A - 电路装置的制造方法 - Google Patents
电路装置的制造方法 Download PDFInfo
- Publication number
- CN1392600A CN1392600A CN02123153A CN02123153A CN1392600A CN 1392600 A CN1392600 A CN 1392600A CN 02123153 A CN02123153 A CN 02123153A CN 02123153 A CN02123153 A CN 02123153A CN 1392600 A CN1392600 A CN 1392600A
- Authority
- CN
- China
- Prior art keywords
- manufacture method
- circuit arrangement
- wiring layer
- conductive wiring
- insulating resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 44
- 239000011347 resin Substances 0.000 claims abstract description 106
- 229920005989 resin Polymers 0.000 claims abstract description 106
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 39
- 238000009413 insulation Methods 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000007789 sealing Methods 0.000 claims description 17
- 239000011248 coating agent Substances 0.000 claims description 16
- 238000000576 coating method Methods 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 230000005684 electric field Effects 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 3
- 239000001569 carbon dioxide Substances 0.000 claims description 3
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 238000007650 screen-printing Methods 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 2
- 239000010931 gold Substances 0.000 claims 2
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 239000004332 silver Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 4
- 239000000463 material Substances 0.000 description 11
- 238000009434 installation Methods 0.000 description 8
- 239000000945 filler Substances 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 239000009719 polyimide resin Substances 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 208000037656 Respiratory Sounds Diseases 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000004090 dissolution Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000005868 electrolysis reaction Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- JYLNVJYYQQXNEK-UHFFFAOYSA-N 3-amino-2-(4-chlorophenyl)-1-propanesulfonic acid Chemical compound OS(=O)(=O)CC(CN)C1=CC=C(Cl)C=C1 JYLNVJYYQQXNEK-UHFFFAOYSA-N 0.000 description 1
- 229910017083 AlN Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 1
- 239000006071 cream Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- FBAFATDZDUQKNH-UHFFFAOYSA-M iron chloride Chemical compound [Cl-].[Fe] FBAFATDZDUQKNH-UHFFFAOYSA-M 0.000 description 1
- 229920002521 macromolecule Polymers 0.000 description 1
- 235000011837 pasties Nutrition 0.000 description 1
- 230000021715 photosynthesis, light harvesting Effects 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01011—Sodium [Na]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01025—Manganese [Mn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0495—5th Group
- H01L2924/04953—TaN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
目前正在开发将具有导电图形的挠性板作为支撑基板采用,在其上边安装半导体元件,整体封装的半导体装置。这时会产生不能形成多层配线结构的问题、和在制造工序中绝缘树脂板的翘曲显著的问题。本发明采用以绝缘树脂2覆盖在导电膜3单面的绝缘树脂板1,在绝缘树脂2上形成通孔后,形成导电镀膜4,将导电镀膜4蚀刻形成的第一导电配线层5和多层连接的第二导电配线层6,实现多层配线结构。另外,半导体元件7固定在覆盖第一导电配线层5的外敷层树脂8上,由此,第一导电配线层5成精密图形,布线也自由。
Description
技术领域
本发明涉及一种电路装置的制造方法,特别是涉及一种以采用导电镀膜及导电膜的薄型,也能实现多层配线的电路装置的制造方法。
背景技术
近年来,IC部件不断向移动设备及小型、高密度安装设备的采用迈进,目前的IC部件及其安装概念正在经历很大的变革。例如特开2000-133678号公报所述。这是一种涉及半导体装置的技术,作为一例绝缘树脂板,采用挠性板的聚酰亚胺树脂片。
图12-图14中,将挠性板50作为插件基板采用,且,各图中上面的图为平面图,下面的图为A-A线的断面图。
首先,在图12表示的挠性板50之上,通过粘接剂粘贴铜箔图形51备用。该铜箔图形51随安装的半导体元件为晶体管、IC,其图形不同,但是一般的来说,形成焊盘51A、隔离岛51B。另外符号52,是用于从挠性板50的背面取出电极的开口部,露出前述铜箔图形51。
然后,该挠性板50送到装片机,如图13,安装半导体元件53。之后,该挠性板50送到引线接合器,把焊盘51A和半导体元件53的接点用细金属线54进行电联接。
最后,如图14(A),在挠性板50的表面设置密封树脂55进行密封。在此,为将焊盘51A、隔离岛51B、半导体元件53及细金属线54覆盖而进行传递模模装。
之后,如图14(B)所示,设置焊料及焊料球等连接装置56,通过焊料反射炉,经开口部52,形成焊盘51A和熔融的球状焊料56。而且在挠性板50上矩阵状形成半导体元件53,如图14所示进行切割,分离为一个一个的元件。
另外图14(C)表示的断面图,是在挠性板50的两面,作为电极形成51A、51D。通常该挠性板50两面形成图形,由厂商提供。
发明内容
采用上述挠性板50的半导体装置,不用周知的金属架,具有以下优点,能够以极其小型化实现薄形组件结构,但是存在以下问题,实质上只是用设置在挠性板50表面的一层铜箔图形51实施配线,不能实现多层配线结构。
为了实现多层配线结构,就要保持支承强度,因此,必须将挠性板50设置的很厚,约为200μm,与薄形化有背道而驰的问题。
而且在制造方法中,要在上述的制造装置,例如,装片机、引线接合器、传递模装置、反射炉等之间,传送挠性板50,并安装在被称为载物台或工作台的部分。
但是,构成挠性板50的基础材料的绝缘树脂的厚度,薄薄地形成50μm程度,在表面形成的铜箔图形51的厚度也只有9-35μm很薄时,则如图15所示翘曲,传送性很差,还有在上述载物台或工作台上安装性恶化的缺点。这可认为是由于绝缘树脂自身很薄形成的翘曲、铜箔图形51和绝缘树脂的热膨胀系数不同形成的翘曲。特别是当未将玻璃布纤维作为芯材的硬的绝缘材料如图15所示翘曲时,会因从上边加压而开裂。
另外开口部52部分,由于封装时从上边加压,有使焊盘51A的周边向上翘曲的力起作用,有时也使焊盘51A的粘接性恶化。
另外构成挠性板50的树脂材料自身没有柔软性,或者为了提高热传导性,而混入填料时则变硬。在这种状态下在引线接合器接合时,接合部分有时产生裂纹。另外在传递模模装时,在金属模具相接部分也会产生裂纹。这一点如图15所示,有翘曲时更明显。
以前说明的挠性板50是背面未形成电极的,但是如图14所示,挠性板50背面也常形成电极51D。这时,由于电极51D与上述制造装置接触或与该制造装置间的传送装置的传送面接触,所以,有电极51D的背面产生损伤的问题,带着该损伤成为电极,会因之后的加热等,在电极51D自身产生裂纹。
另外如果挠性板50的背面设置电极51D,那么在传递模模装时,会产生不能与载物面面接触的问题。这时,如果如上所述,挠性板50以硬材料构成,那么电极51D就会构成支点,使电极51D的周围被向下方加压,有挠性板50产生裂纹的问题。
本发明者为了解决这些问题,提出采用将薄的第一导电膜与厚的第二导电膜以绝缘树脂相互粘合的绝缘树脂板的方案。
本发明的电路装置的制造方法,包括以下工序:预备用绝缘树脂覆盖导电膜的表面而成的绝缘树脂板的工序;在所述绝缘树脂板的所需部位的所述绝缘树脂上形成通孔,选择性地露出所述导电膜背面的工序;在所述通孔及所述绝缘树脂表面形成导电镀膜的工序;将所述导电镀膜蚀刻为所需的图形,形成第一导电配线层的工序;在所述第一导电配线层上电绝缘地固定半导体元件的工序;将所述第一导电配线层及所述半导体元件用密封树脂层覆盖的工序;将所述第二导电膜蚀刻成所需的图形,形成第二导电配线层的工序;在所述第二导电配线层的所需的部位形成外部电极的工序。
由于导电模厚厚地形成,所以即使绝缘树脂薄,也能维持片状电路基板的平整性。
另外,在一直到用密封树脂层覆盖第一导电配线层及半导体元件的工序前,用导电膜维持机械性的强度,之后用密封树脂层维持机械性的强度,所以,可容易地以导电膜形成第二导电配线层。其结果是,绝缘树脂不需要机械性的强度,只要能够保持电绝缘,其厚度能够形成得很薄。
而且,由于在传递模模装时下金属模具能以面与导电膜整体接触,所以没有局部加压,可以抑制绝缘树脂的裂纹产生。
附图说明
图1是说明本发明电路装置制造方法的断面图。
图2是说明本发明电路装置制造方法的断面图。
图3是说明本发明电路装置制造方法的断面图。
图4是说明本发明电路装置制造方法的断面图。
图5是说明本发明电路装置制造方法的断面图。
图6是说明本发明电路装置制造方法的断面图。
图7是说明本发明电路装置制造方法的断面图。
图8是说明本发明电路装置制造方法的断面图。
图9是说明本发明电路装置制造方法的断面图。
图10是说明利用本发明制造的电路装置的平面图。
图11是说明本发明电路装置制造方法的断面图。
图12是说明目前半导体装置制造方法的图。
图13是说明目前半导体装置制造方法的图。
图14是说明目前半导体装置制造方法的图。
图15是说明目前的挠性板的图。
具体实施方式
参照图1到图11说明本发明的电路装置的制造方法
本发明电路装置的制造方法有以下工序构成:预备用绝缘树脂覆盖导电膜的表面而成的绝缘树脂板的工序;在所述绝缘树脂板的所需部位的所述绝缘树脂上形成通孔,选择性地露出所述导电膜背面的工序;在所述通孔及所述绝缘树脂表面形成导电镀膜的工序;将所述导电镀膜蚀刻为所需的图形,形成第一导电配线层的工序;在所述第一导电配线层上电绝缘地固定半导体元件的工序;将所述第一导电配线层及所述半导体元件用密封树脂层覆盖的工序;将所述第二导电镀膜蚀刻成所需的图形,形成第二导电配线层的工序;在所述第二导电配线层的所需的部位,形成外部电极的工序。
本发明的第一工序,如图1所示,预备用绝缘树脂2覆盖导电膜3表面而成的绝缘树脂板1。
绝缘树脂板1,是以绝缘树脂2覆盖导电膜3的全表面形成的。另外,绝缘树脂2的材料,是由聚酰亚胺树脂或环氧树脂等高分子构成的绝缘材料制成。另外,导电膜3最好是以Cu为主材料的材料,或是公知的引线框架材料。
绝缘树脂板1是首先在平膜状的导电膜3上涂敷糊状的聚酰亚胺树脂,使其半硬化而形成的。因此绝缘树脂板1还具有不需要补强用的玻璃布纤维的特征。
本发明的特征在于导电膜3形成得很厚。
导电膜3厚度最好在70-200μm,重视具有支承强度这一点。
因此,以导电膜3的厚度能维持绝缘树脂板1的平坦性,提高后续工序的操作性,能够防止绝缘树脂2的缺陷、裂纹等的发生。
绝缘树脂2最好是聚酰亚胺树脂、环氧树脂等。用涂敷糊状物形成薄片的铸塑法时,其膜厚为10μm-100μm的程度。另外,形成薄片时,市售品的最小膜厚为25μm。另外,考虑热传导性,其中混入填料也可以。作为材料可以考虑玻璃、氧化硅、氧化铝、氮化铝、炭化硅、氮化硼等。
这样,绝缘树脂2,可以选择混入上述填料的低热阻树脂、超低热阻树脂或聚酰亚胺树脂,根据形成的电路装置的性质不同区分使用。
本发明的第二工序,如图2所示,在绝缘树脂板1所需的部位的绝缘树脂2上形成通孔21,选择性地露出导电膜3的背面。
只露出绝缘树脂2的形成通孔21的部分,以光致抗蚀剂覆盖整个面。然后将该光致抗蚀剂作为掩膜,用激光除去通孔21正下方的绝缘树脂2,使通孔21的底部露出导电膜3的背面。作为激光最好为二氧化碳激光。另外用激光使绝缘树脂2蒸发后,开口部的底部留有残渣时,用过锰酸钠、或过硫酸氨等进行湿蚀刻,除去该残渣。通孔21的开口直径,由于光刻法的图像分辨率不同而改变,在此为50-100μm的程度。
本发明的第三工序,如图3所示,在通孔21及绝缘树脂2表面形成导电镀膜4。
在包含通孔21的绝缘树脂2整个面无掩模地形成导电镀膜4。
该导电镀膜4以非电解电镀和电解镀两方面形成,在此,利用非电解镀至少在包含通孔21的绝缘树脂2整个面形成大约2μm铜。由此导电镀膜4与导电膜3电气导通,再次以导电膜3为电极进行电解镀,镀约20μm的铜。由此通孔21被铜的导电镀膜4所埋。另外导电镀膜4在此采用了铜、但也可以采用Au、Ag、Pd等。另外也可以使用掩膜进行局部镀。
本发明的第四工序,如图4及图5所示,将导电镀膜4蚀刻为所需的图形,形成第一导电配线层5。
以所需图形的光致抗蚀剂覆盖在导电镀膜4上,利用化学蚀刻形成焊盘10及从焊盘10延伸到中央的第一导电配线层5。由于导电镀膜4以铜作为主材,所以蚀刻液可以采用氯化铁、氯化铜。
导电镀膜4形成5-20μm的厚度,第一导电配线层5形成20μm以下的精密图形。
然后如图5所示,将第一导电配线层5及焊盘10露出,其它部分用外敷层树脂8覆盖,外敷层树脂8是把用溶剂溶解的环氧树脂等用网印附着并进行热硬化而得到的。
另外,在焊盘10上考虑接合性,形成Cu、Ag等的镀膜22。该镀膜22是将外敷层树脂8作为掩膜,选择性地在焊盘10上进行无电场镀,或者将导电膜3作为电极,以电场电镀附着。
本发明的第五工序,如图6所示,在第一导电配线层5上电绝缘地固定半导体元件7。
半导体元件7以裸片状态由绝缘性粘接树脂25在外敷层树脂8上进行装片,半导体元件7和其下的第一导电配线层5以外敷层树脂8进行电气绝缘,所以第一导电配线层5即使在半导体元件7之下,也能自由配线,能够实现多层配线结构。
另外半导体元件7的各电极接点9,以接合线11连接在焊盘10上,该焊盘10是设置在周边的第一导电配线层5的一部分。半导体元件7以表面向下安装也可(参照图11)。这时,在半导体元件7的各电极接点9表面设有焊接球及凸起,在绝缘树脂板1的表面与焊接球位置对应的部分设置与焊盘10同样的电极。
下面叙述线接合时采用绝缘树脂板1的优点。一般Au线接合时,加热到200-300℃。这时,这时,如果导电膜3薄,绝缘树脂板1形成翘曲,如果以该状态通过焊头向绝缘树脂板1加压,则绝缘树脂板1有可能产生龟裂。这如果在绝缘树脂2掺入填料,那么,材料自身变硬,失去柔软性时更明显。另外树脂比金属柔软,所以在Au、Al的接合时,加压和超声波的能量扩散。但是,通过把绝缘树脂2变薄而且导电膜3自身加厚形成可以解决这些问题。
本发明的第六工序,如图7所示,将第一导电配线层5及半导体元件7用密封树脂层13覆盖。
绝缘树脂板1装在模装装置中,进行树脂模装。作为模装方法,可以为传递模模装、注入模模装、涂敷、浸渍等。但是,如果考虑批量生产,则传递模模装、注入模模装最适合。
本工序中,在膜腔的下金属模,绝缘树脂板1必须平整地接触,厚导电模3实施这一功能。而且从模腔取出后,一直到密封树脂层13的收缩完全结束,都由导电模3维持组件的平坦性。
即,本工序之前,对绝缘树脂板1的机械支承的作用,由导电膜3承担。
本发明的第七工序,如图8所示,将导电膜3蚀刻为所需的图形,形成第二导电配线层6。
导电膜3以所需图形的光致抗蚀剂覆盖,以化学蚀刻形成第二导电配线层6。第二导电配线层6通过通孔21个别地与第一导电配线层5电联接,实现多层配线结构。再者如果有必要,可以在空白部分形成用于与第一导电配线层5交叉的第二导电配线层6。
本发明的第八工序,如图9所示,在第二导电配线层6的所需部位形成外部电极14。
第二导电配线层6露出形成外部电极14的部分,对以溶剂溶解的环氧树脂等进行丝网印刷,用外敷层树脂15覆盖大部分。然后利用焊料的反流或焊料膏的丝网印刷,同时在该露出的部分形成电极14。
最后,在绝缘树脂板1上,矩阵状形成多个电路装置,所以将密封树脂层13及绝缘树脂板1切块,将其分离成逐个的电路装置。
参照图10,说明用本发明具体的制造方法形成的电路装置。首先,以实线表示的图形就是第一导电配线层5,以虚线表示的图形就是第二导电配线层6。第一导电配线层5象包围半导体元件7那样,将焊盘10设置在周边,一部分配置为2段,与具有多个接点的半导体元件7对应。焊盘10以接合线11与半导体元件7对应的电极接点9联接,多个精密图形的第一导电配线层5从焊盘10延伸到半导体元件7之下,以用黑点表示的通孔21与第二导电配线层6联接。
利用这种构造,即使是具有200以上接点的半导体元件,也可利用第一导电配线层5的精密图形,以多层配线结构延伸到所需的第二导电配线层6,可由设置在第二导电配线层6的外部电极14连接到外部电路。
在图11,表示了半导体元件7表面向下安装的结构。与图9相同的结构要素,赋予同一符号。在半导体元件7上设置凸出电极31,该凸出电极31与接点电极10联接。外敷层树脂8与半导体元件7的间隙以填充树脂32填充。在该结构中可以没有接合线,可使密封树脂13的厚度更薄。另外,外部电极14也可以实现将第二导电膜4蚀刻并将其表面用镀金或镀钯膜33覆盖的凸出电极。
本发明具有以下优点:
第一,在以密封树脂层模装之前,作为绝缘树脂板的翘曲能用导电膜消除,能够提高搬送性等。
第二,在绝缘树脂上以二氧化碳激光形成通孔后,形成用于形成第一导电配线层的导电镀膜,所以能同时实现与第二导电配线层的多层连接,工序很简单。
第三,能形成很薄的用于形成第一导电配线层的导电镀膜,能使第一导电配线层极其精密图形化。
第四,到密封树脂层形成之前,以导电膜进行绝缘树脂板的机械性的支承,第二导电配线层形成后,用密封树脂层进行绝缘树脂板的机械性的支承,所以不用考虑绝缘树脂的机械性的强度,可以实现极薄型的安装方法。
第五,无论绝缘树脂自身硬,还是另外掺入填料而变硬,由于以导电膜支承,所以在制造工序中绝缘树脂板自身的平整性提高,可以防止产生裂纹。
第六,绝缘树脂板上由于形成厚导电膜,所以能作为用于芯片的装片、引线接合器、半导体元件密封的支承基板利用。而且即使绝缘树脂材料自身柔软时,也能提高线接合时的能量传送,也可提高线接合性。
Claims (17)
1、一种电路装置的制造方法,其特征在于,包括:
预备用绝缘树脂覆盖导电膜的表面而成的绝缘树脂板的工序;在所述绝缘树脂板的所需部位的所述绝缘树脂上形成通孔,选择性地露出所述导电膜背面的工序;在所述通孔及所述绝缘树脂表面形成导电镀膜的工序;将所述导电镀膜蚀刻为所需的图形,形成第一导电配线层的工序;在所述第一导电配线层上电绝缘地固定半导体元件的工序;将所述第一导电配线层及所述半导体元件用密封树脂层覆盖的工序;将所述第二导电膜蚀刻成所需的图形,形成第二导电配线层的工序;在所述第二导电配线层的所需部位形成外部电极的工序。
2、如权利要求书1所述的电路装置的制造方法,其特征在于,所述导电膜及所述导电镀膜用铜形成。
3、如权利要求书1所述的电路装置的制造方法,其特征在于,所述导电镀膜形成得薄,使所述第一导电配线层形成精细图形化。
4、如权利要求书1所述的电路装置的制造方法,其特征在于,所述导电膜形成得厚,到用所述密封树脂层覆盖的工序前,以所述导电膜机械地支承。
5、如权利要求书1所述的电路装置的制造方法,其特征在于,在用所述密封树脂层覆盖的工序后,以所述密封树脂层机械地支承。
6、如权利要求书1所述的电路装置的制造方法,其特征在于,所述通孔是激光蚀刻所述绝缘树脂形成的。
7、如权利要求书6所述的电路装置的制造方法,其特征在于,所述激光蚀刻采用二氧化碳激光。
8、如权利要求书1所述的电路装置的制造方法,其特征在于,所述导电镀膜以导电金属的无电场镀及电场镀形成于所述通孔及所述绝缘树脂的表面。
9、如权利要求书1所述的电路装置的制造方法,其特征在于,形成所述第一导电配线层之后,除所需部位外用外敷层树脂覆盖。
10、如权利要求书9所述的电路装置的制造方法,其特征在于,在从所述第一导电配线层的所述外敷层树脂露出的部位,形成金或银的镀层。
11、如权利要求书9所述的电路装置的制造方法,其特征在于,所述半导体元件固定在所述外敷层树脂上。
12、如权利要求书10所述的电路装置的制造方法,其特征在于,所述半导体元件的电极与所述金或银的镀层以接合线来连接。
13、如权利要求书1所述的电路装置的制造方法,其特征在于,所述密封树脂层以传递模形成。
14、如权利要求书1所述的电路装置的制造方法,其特征在于,所述第二导电配线层大部分被外敷层树脂覆盖。
15、如权利要求书1所述的电路装置的制造方法,其特征在于,所述外部电极以焊料的丝网印刷附着焊料,加热熔融后形成。
16、如权利要求书1所述的电路装置的制造方法,其特征在于,所述外部电极以焊料的反流形成。
17、如权利要求书1所述的电路装置的制造方法,其特征在于,所述外部电极是将所述导电膜蚀刻为所需的图形,将其表面镀金或镀钯形成的。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP185422/2001 | 2001-06-19 | ||
JP2001185422A JP2003007916A (ja) | 2001-06-19 | 2001-06-19 | 回路装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1392600A true CN1392600A (zh) | 2003-01-22 |
CN1191618C CN1191618C (zh) | 2005-03-02 |
Family
ID=19025010
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB021231532A Expired - Fee Related CN1191618C (zh) | 2001-06-19 | 2002-06-19 | 电路装置的制造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6720209B2 (zh) |
JP (1) | JP2003007916A (zh) |
KR (1) | KR20020096968A (zh) |
CN (1) | CN1191618C (zh) |
TW (1) | TW540148B (zh) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1301544C (zh) * | 2003-06-13 | 2007-02-21 | 三洋电机株式会社 | 半导体装置的制造方法 |
CN100440500C (zh) * | 2003-03-11 | 2008-12-03 | 古河电气工业株式会社 | 印刷配线基板、其制造方法、引线框封装件以及光模块 |
CN101393874B (zh) * | 2007-09-21 | 2010-04-14 | 中芯国际集成电路制造(上海)有限公司 | 基于硅通孔的三维堆叠封装方法 |
CN102215640A (zh) * | 2010-04-06 | 2011-10-12 | 富葵精密组件(深圳)有限公司 | 电路板制作方法 |
CN106328607A (zh) * | 2015-07-03 | 2017-01-11 | 株式会社吉帝伟士 | 半导体器件及其制造方法 |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003007922A (ja) * | 2001-06-19 | 2003-01-10 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
JP4086607B2 (ja) * | 2002-09-26 | 2008-05-14 | 三洋電機株式会社 | 回路装置の製造方法 |
JP2004335710A (ja) * | 2003-05-07 | 2004-11-25 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
US6992380B2 (en) * | 2003-08-29 | 2006-01-31 | Texas Instruments Incorporated | Package for semiconductor device having a device-supporting polymeric material covering a solder ball array area |
US20060134831A1 (en) * | 2003-12-31 | 2006-06-22 | Microfabrica Inc. | Integrated circuit packaging using electrochemically fabricated structures |
US7355283B2 (en) * | 2005-04-14 | 2008-04-08 | Sandisk Corporation | Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging |
TWI283056B (en) * | 2005-12-29 | 2007-06-21 | Siliconware Precision Industries Co Ltd | Circuit board and package structure thereof |
WO2009107880A1 (en) * | 2008-02-25 | 2009-09-03 | Ls Mtron, Ltd. | Flip chip packaging method using double layer type wafer level underfill, flip chip package manufactured using the same, and semiconductor device for the same |
US7830024B2 (en) * | 2008-10-02 | 2010-11-09 | Advanced Semiconductor Engineering, Inc. | Package and fabricating method thereof |
JP6923299B2 (ja) * | 2016-09-26 | 2021-08-18 | 株式会社アムコー・テクノロジー・ジャパン | 半導体装置及び半導体装置の製造方法 |
Family Cites Families (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US702789A (en) * | 1902-03-20 | 1902-06-17 | Charles Gordon Gibson | Dilator. |
US4181123A (en) * | 1977-12-28 | 1980-01-01 | The University Of Virginia Alumni Patents Foundation | Apparatus for cardiac surgery and treatment of cardiovascular disease |
US4319562A (en) * | 1977-12-28 | 1982-03-16 | The University Of Virginia Alumni Patents Foundation | Method and apparatus for permanent epicardial pacing or drainage of pericardial fluid and pericardial biopsy |
US4291707A (en) * | 1979-04-30 | 1981-09-29 | Mieczyslaw Mirowski | Implantable cardiac defibrillating electrode |
US4765341A (en) * | 1981-06-22 | 1988-08-23 | Mieczyslaw Mirowski | Cardiac electrode with attachment fin |
US5033477A (en) * | 1987-11-13 | 1991-07-23 | Thomas J. Fogarty | Method and apparatus for providing intrapericardial access and inserting intrapericardial electrodes |
US4991578A (en) * | 1989-04-04 | 1991-02-12 | Siemens-Pacesetter, Inc. | Method and system for implanting self-anchoring epicardial defibrillation electrodes |
US5071428A (en) * | 1989-09-08 | 1991-12-10 | Ventritex, Inc. | Method and apparatus for providing intrapericardial access and inserting intrapericardial electrodes |
US5345927A (en) * | 1990-03-02 | 1994-09-13 | Bonutti Peter M | Arthroscopic retractors |
US5129394A (en) * | 1991-01-07 | 1992-07-14 | Medtronic, Inc. | Method and apparatus for controlling heart rate in proportion to left ventricular pressure |
US5246014A (en) * | 1991-11-08 | 1993-09-21 | Medtronic, Inc. | Implantable lead system |
US6102046A (en) * | 1995-11-22 | 2000-08-15 | Arthrocare Corporation | Systems and methods for electrosurgical tissue revascularization |
US5339801A (en) * | 1992-03-12 | 1994-08-23 | Uresil Corporation | Surgical retractor and surgical method |
US5336252A (en) * | 1992-06-22 | 1994-08-09 | Cohen Donald M | System and method for implanting cardiac electrical leads |
GR930100244A (el) * | 1992-06-30 | 1994-02-28 | Ethicon Inc | Εύκαμπτο ενδοσκοπικό χειρουργικό στόμιο εισόδου. |
US5613937A (en) * | 1993-02-22 | 1997-03-25 | Heartport, Inc. | Method of retracting heart tissue in closed-chest heart surgery using endo-scopic retraction |
US6346074B1 (en) * | 1993-02-22 | 2002-02-12 | Heartport, Inc. | Devices for less invasive intracardiac interventions |
US5431676A (en) * | 1993-03-05 | 1995-07-11 | Innerdyne Medical, Inc. | Trocar system having expandable port |
US5433198A (en) * | 1993-03-11 | 1995-07-18 | Desai; Jawahar M. | Apparatus and method for cardiac ablation |
US5385156A (en) * | 1993-08-27 | 1995-01-31 | Rose Health Care Systems | Diagnostic and treatment method for cardiac rupture and apparatus for performing the same |
US5464447A (en) * | 1994-01-28 | 1995-11-07 | Sony Corporation | Implantable defibrillator electrodes |
US5681278A (en) * | 1994-06-23 | 1997-10-28 | Cormedics Corp. | Coronary vasculature treatment method |
US5827216A (en) * | 1995-06-07 | 1998-10-27 | Cormedics Corp. | Method and apparatus for accessing the pericardial space |
US5797946A (en) * | 1995-07-13 | 1998-08-25 | Origin Medsystems, Inc. | Method for arterial harvest and anastomosis for coronary bypass grafting |
US6405431B1 (en) * | 1996-06-27 | 2002-06-18 | Samsung Electro-Mechanics Co., Ltd. | Method for manufacturing build-up multi-layer printed circuit board by using yag laser |
US5755764A (en) * | 1996-09-10 | 1998-05-26 | Sulzer Intermedics Inc. | Implantable cardiac stimulation catheter |
US6237605B1 (en) * | 1996-10-22 | 2001-05-29 | Epicor, Inc. | Methods of epicardial ablation |
US5989935A (en) * | 1996-11-19 | 1999-11-23 | Texas Instruments Incorporated | Column grid array for semiconductor packaging and method |
US5931810A (en) * | 1996-12-05 | 1999-08-03 | Comedicus Incorporated | Method for accessing the pericardial space |
US6206004B1 (en) * | 1996-12-06 | 2001-03-27 | Comedicus Incorporated | Treatment method via the pericardial space |
US5957835A (en) * | 1997-05-16 | 1999-09-28 | Guidant Corporation | Apparatus and method for cardiac stabilization and arterial occlusion |
US5897586A (en) * | 1997-08-15 | 1999-04-27 | Regents Of The University Of Minnesota | Implantable defibrillator lead |
US5972013A (en) * | 1997-09-19 | 1999-10-26 | Comedicus Incorporated | Direct pericardial access device with deflecting mechanism and method |
US5997509A (en) * | 1998-03-06 | 1999-12-07 | Cornell Research Foundation, Inc. | Minimally invasive gene therapy delivery device and method |
US5902331A (en) * | 1998-03-10 | 1999-05-11 | Medtronic, Inc. | Arrangement for implanting an endocardial cardiac lead |
US5972010A (en) * | 1998-05-14 | 1999-10-26 | Taheri; Syde A. | Vein harvesting system |
US6030406A (en) * | 1998-10-05 | 2000-02-29 | Origin Medsystems, Inc. | Method and apparatus for tissue dissection |
CA2261488A1 (en) * | 1999-01-21 | 2000-07-21 | Anthony Paolitto | Transabdominal device for performing closed-chest cardiac surgery |
US6488689B1 (en) * | 1999-05-20 | 2002-12-03 | Aaron V. Kaplan | Methods and apparatus for transpericardial left atrial appendage closure |
-
2001
- 2001-06-19 JP JP2001185422A patent/JP2003007916A/ja active Pending
-
2002
- 2002-05-28 TW TW091111257A patent/TW540148B/zh not_active IP Right Cessation
- 2002-06-14 US US10/172,445 patent/US6720209B2/en not_active Expired - Fee Related
- 2002-06-18 KR KR1020020033938A patent/KR20020096968A/ko active IP Right Grant
- 2002-06-19 CN CNB021231532A patent/CN1191618C/zh not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100440500C (zh) * | 2003-03-11 | 2008-12-03 | 古河电气工业株式会社 | 印刷配线基板、其制造方法、引线框封装件以及光模块 |
CN1301544C (zh) * | 2003-06-13 | 2007-02-21 | 三洋电机株式会社 | 半导体装置的制造方法 |
CN101393874B (zh) * | 2007-09-21 | 2010-04-14 | 中芯国际集成电路制造(上海)有限公司 | 基于硅通孔的三维堆叠封装方法 |
CN102215640A (zh) * | 2010-04-06 | 2011-10-12 | 富葵精密组件(深圳)有限公司 | 电路板制作方法 |
CN102215640B (zh) * | 2010-04-06 | 2013-11-06 | 富葵精密组件(深圳)有限公司 | 电路板制作方法 |
CN106328607A (zh) * | 2015-07-03 | 2017-01-11 | 株式会社吉帝伟士 | 半导体器件及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US6720209B2 (en) | 2004-04-13 |
KR20020096968A (ko) | 2002-12-31 |
CN1191618C (zh) | 2005-03-02 |
US20020192858A1 (en) | 2002-12-19 |
TW540148B (en) | 2003-07-01 |
JP2003007916A (ja) | 2003-01-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100350607C (zh) | 半导体器件及其制造方法 | |
CN1191618C (zh) | 电路装置的制造方法 | |
CN1191619C (zh) | 电路装置及其制造方法 | |
CN101480116B (zh) | 电路基板、电子器件配置及用于电路基板的制造工艺 | |
TWI437647B (zh) | 具有凸塊/基座/凸緣層散熱座及增層電路之散熱增益型半導體組體 | |
CN1320620C (zh) | 半导体器件及其制造方法 | |
CN1716587A (zh) | 内插器及其制造方法以及使用该内插器的半导体器件 | |
US20080296056A1 (en) | Printed circuit board, production method therefor, electronic-component carrier board using printed circuit board, and production method therefor | |
CN1873935B (zh) | 配线基板的制造方法及半导体器件的制造方法 | |
CN1254859C (zh) | 电路装置的制造方法 | |
CN1835661A (zh) | 配线基板的制造方法 | |
CN1491439A (zh) | 多芯片电路模块及其制造方法 | |
CN1697163A (zh) | 布线板及使用该板的半导体封装 | |
CN1282982A (zh) | 半导体器件的制造方法 | |
CN1505147A (zh) | 电子部件封装结构和生产该结构的方法 | |
CN1949467A (zh) | 无芯基板及其制造方法 | |
CN101080958A (zh) | 部件内置模块及其制造方法 | |
JP2008085089A (ja) | 樹脂配線基板および半導体装置 | |
CN1186807C (zh) | 电路装置的制造方法 | |
CN1186808C (zh) | 电路装置的制造方法 | |
CN101355857A (zh) | 电子部件内置基板及其制造方法 | |
CN1929122A (zh) | 半导体封装及其制造方法 | |
CN1193417C (zh) | 电路装置的制造方法 | |
JP2008270362A (ja) | 積層配線基板及びその製造方法 | |
CN1254856C (zh) | 电路装置的制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050302 Termination date: 20130619 |