WO2009107880A1 - Flip chip packaging method using double layer type wafer level underfill, flip chip package manufactured using the same, and semiconductor device for the same - Google Patents

Flip chip packaging method using double layer type wafer level underfill, flip chip package manufactured using the same, and semiconductor device for the same Download PDF

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Publication number
WO2009107880A1
WO2009107880A1 PCT/KR2008/001087 KR2008001087W WO2009107880A1 WO 2009107880 A1 WO2009107880 A1 WO 2009107880A1 KR 2008001087 W KR2008001087 W KR 2008001087W WO 2009107880 A1 WO2009107880 A1 WO 2009107880A1
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WO
WIPO (PCT)
Prior art keywords
underfill layer
underfill
layer
flip chip
packaging method
Prior art date
Application number
PCT/KR2008/001087
Other languages
French (fr)
Inventor
June Roh
Byung-Un Kang
Choong-Hyun Sung
Joon-Mo Seo
Jae-Hun Kim
Soon-Young Hyun
Ji-Eun Kim
Jun-Woo Lee
Original Assignee
Ls Mtron, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ls Mtron, Ltd. filed Critical Ls Mtron, Ltd.
Priority to PCT/KR2008/001087 priority Critical patent/WO2009107880A1/en
Publication of WO2009107880A1 publication Critical patent/WO2009107880A1/en

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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08L—COMPOSITIONS OF MACROMOLECULAR COMPOUNDS
    • C08L63/00—Compositions of epoxy resins; Compositions of derivatives of epoxy resins
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J163/00—Adhesives based on epoxy resins; Adhesives based on derivatives of epoxy resins
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Definitions

  • the present invention relates to flip chip packaging using an underfill, in particular, to a flip chip packaging method using a wafer level underfill having the improved cure characteristics, a flip chip package manufactured using the same, and a semiconductor device for the same.
  • a flip chip bonding technique used widely in semiconductor packaging has a drawback that quality of products may be reduced by stresses applied to an assembly structure after thermal cycling due to a difference in CTE (Coefficient of Thermal Expansion) between a chip die and a substrate.
  • CTE Coefficient of Thermal Expansion
  • NUF no-flow Underfill
  • molded underfill or wafer level underfill have been developed, which fill a gap between a chip die and a substrate with a polymeric en- capsulant to reinforce interconnect materials and absorb a portion of stresses occurring due to thermal cycling.
  • the wafer level underfill process coats a semiconductor wafer with an underfill encapsulant before dicing the semiconductor wafer into individual chips, thereby resulting in simple process and improved production efficiency.
  • the U.S. Patent Application No. 09/648,777 discloses a process which dispenses an underfill on a wafer having bumps to a level lower than the height of the bumps, removes a solvent to solidify the underfill, dices the wafer into individual chips, covers the bumps with a tacky film, mounts the chips to a substrate, and reflows the solder bumps and cures the underfill simultaneously.
  • the Korean Patent Registration No. 621438 teaches a stack chip package of a three- dimensional stack structure using a photosensitive polymer, in which each of semiconductor chips with penetration electrodes has a photosensitive polymer layer formed on an upper surface thereof and the semiconductor chips are stacked by thermo- compression such that upper surfaces of the semiconductor chips face an upper surface of a wiring substrate, and a manufacturing method thereof.
  • the Korean Patent Laid-Open Publication No. 2004-68145 suggests a wafer level underfill including a combination of different compositions having different curing temperatures or curing temperature ranges.
  • the conventional wafer level underfill structures cannot completely prevent an electrical short caused by a filler existing near the surface thereof, and have a drawback of reduction in adhesion or electrical connection reliability after a B-stage process or a reflow process. Disclosure of Invention Technical Problem
  • the present invention is designed to solve the problem, and therefore an object of the present invention is to provide a flip chip packaging method using a double layer type wafer level underfill having different curing systems, a flip chip package manufactured using the same, a semiconductor wafer for the same and a semiconductor chip for the same.
  • a flip chip packaging method comprises (a) forming a double layer type underfill layer having different curing temperatures on one surface of a semiconductor wafer having a solder bump pattern; (b) performing a B-stage process on the underfill layer to cure a layer having a relatively lower curing temperature among the double layer type underfill layer; (c) dicing the semiconductor wafer into individual chips; (d) aligning the individual chips on a substrate such that a surface of the underfill layer faces a surface of the substrate; and (e) performing a reflow process with temperature capable of curing all of the double layer type underfill layer.
  • a first underfill layer and a second underfill layer are formed on the semiconductor wafer in sequence, and the curing temperature of the first underfill layer is relatively lower than the curing temperature of the second underfill layer.
  • the first underfill layer contains a filler, and the second underfill layer does not contain a filler.
  • the first underfill layer does not contain a fluxing agent
  • the second underfill layer contains a fluxing agent
  • the first underfill layer has a thickness corresponding to 70 to 90 % of a thickness of the entire underfill layer including the first underfill layer and the second underfill layer.
  • the chips are aligned with the substrate such that the solder bumps of the chips are contacted with contact pads of the substrate.
  • the underfill layer may be formed by any one process selected from the group consisting of screen printing, stencil printing and spin coating.
  • a flip chip package manufactured by the above-mentioned flip chip packaging method is provided.
  • a semiconductor wafer of a front-end semiconductor process having a solder bump pattern and an underfill layer formed on one surface thereof is provided, wherein the underfill layer is formed of a double layer type underfill layer having different curing temperatures.
  • a semiconductor chip provided through a dicing process and having a solder bump pattern and an underfill layer formed on one surface thereof is provided, wherein the underfill layer is formed of a double layer type underfill layer having different curing temperatures.
  • FIG. 1 is a flow chart illustrating steps of a flip chip packaging method according to a preferred embodiment of the present invention.
  • FIG. 2 is a process view illustrating processing steps of a semiconductor wafer and a semiconductor chip as a semiconductor device provided by the present invention.
  • FIG. 3 is a cross-sectional view illustrating a configuration of a flip chip package according to the present invention. Mode for the Invention
  • FIGs. 1 and 2 show a flip chip packaging process according to a preferred embodiment of the present invention.
  • patterning 101 is performed on an active surface of a semiconductor wafer 100 and a solder bump pattern 102 are formed on the active surface of the semiconductor wafer 100 (SlOO).
  • a first underfill layer 103 is formed on the active surface of the semiconductor wafer 100 having the solder bump pattern 102, and as shown in FIG. 2(e), a second underfill layer 104 is formed on the first underfill layer 103, so that the semiconductor wafer 100 has a double layer type underfill layer (SI lO).
  • SI lO double layer type underfill layer
  • the first underfill layer 103 and the second underfill layer 104 may be formed by screen printing, stencil printing or spin coating.
  • the first underfill layer 103 has such a curing system that the first underfill layer
  • the first underfill layer 103 contains main components including a thermosetting reaction resin, at least one thermal initiator, a crosslinkable resin such as epoxy, and a filler
  • the second underfill layer 104 contains main components including a thermosetting reaction resin, at least one thermal initiator, a crosslinkable resin such as epoxy, and a fluxing agent.
  • the first underfill layer 103 contains a filler, but the second underfill layer 104 does not contain a filler. And, the first underfill layer 103 does not contain a fluxing agent, but the second underfill layer 104 contains a fluxing agent.
  • the thermosetting reaction resin includes vinyl eter, vinyl silane, a styrene compound, a bismaleide compound having a cinnamyl compound, or a thermosetting epoxy compound having a latent amine or imidazole curing agent.
  • the thermosetting reaction resin has a content of 5 to 30 weight% based on the entire underfill.
  • the thermal initiator includes an organic peroxide such as benzoyl peroxide or cumyl peroxide, an azo-based thermal initiator such as azobisisobuty- ronitrile, or a UV curing agent such as acetophenone, benzophenone or benzaldehyde, and the thermal initiator has a content of 0.1 to 10 weight%.
  • an organic peroxide such as benzoyl peroxide or cumyl peroxide
  • an azo-based thermal initiator such as azobisisobuty- ronitrile
  • a UV curing agent such as acetophenone, benzophenone or benzaldehyde
  • the epoxy resin includes bisphenol A and bisphenol F monofunctional and multifunctional glycidyl eter, fatty and aromatic epoxy, saturated and unsaturated epoxy, an alicyclic epoxy resin, or mixtures thereof.
  • the epoxy resin has a content of 10 to 70 weight% based on the entire underfill.
  • the filler contained in the first underfill layer 103 includes an inorganic filler such as a nonconductive silica or calcium carbonate, or an organic filler such as an acryl rubber or tetra fluoroethylene to improve moisture resistance and control coefficient of thermal expansion.
  • the filler has a content of 30 to 70% based on the first underfill layer 103.
  • the fluxing agent contained in the second underfill layer 104 removes a metal oxide from a contact pad of a substrate and prevent a reoxidation reaction.
  • the fluxing agent includes carboxylic acid or carboxylic anhydride, polysebacic polyanhydride, rosin gum, dodecandioic acid, or mixtures thereof.
  • the first underfill layer 103 and the second underfill layer 104 further contain an amine -based, anhydride -based or amide-based curing agent with a content of 1 to 10 weight%.
  • the first underfill layer 103 has a thickness corresponding to
  • the first underfill layer 103 is excessively thin, for example the thickness of the first underfill layer 103 is less than 70% of the thickness of the entire underfill layer, a filler is not sufficiently filled, thereby deteriorating the coefficient of thermal expansion, and in the case that the first underfill layer 103 is excessively thick, for example the thickness of the first underfill layer 103 is more than 90% of the thickness of the entire underfill layer, a filler is excessively distributed toward the substrate during a reflow process, which may cause an electrical short, and make it difficult to secure a sufficient thickness of the second underfill layer 104, thereby reducing flow characteristics of the second underfill layer 104.
  • a B-stage process for applying heat for example, of 100 to 150 0 C is performed to cure the first underfill layer 103 (S120), and subsequently, as shown in FIG. 2(f), a dicing process is performed to singulate the semiconductor wafer into individual chips (S 130).
  • the individual chips 100' separated through the dicing process are aligned with a substrate 200 (S 140), and a reflow process is performed (S150), so that the individual chips 100' are bonded to the substrate 200.
  • the semiconductor chip dies 100' are aligned with the substrate 200 such that the surface of the second underfill layer 104 faces the surface of the substrate 200 and the solder bumps 102 of the semiconductor chips 100' are contacted with contact pads 201 of the substrate 200.
  • heat for example, of 250 0 C is applied to cure both of the first underfill layer 103 and the second underfill layer 104, so that interconnection is established between the semiconductor chips 100' and the substrate 200.
  • the first underfill layer included 45 weight% of bisphenol A epichlorohydrin epoxy, 24.5 weight% of 2-phenoxy ethyl acrylate, 25 weight% of butylphenyl maleimide, 1.5 weight% of cobalt neodecanoate, 2 weight% of dicumyl peroxide, 2 weight% of methylhexahydrophthalic anhydride and 60 weight% of fused silica
  • the second underfill layer included 62 weight% of bisphenol A epichlorohydrin epoxy, 24 weight% of 2-phenoxyethyl acrylate, 10 weight% of 2-phenyl-4methyl imidazol, 2 weight% of dicumyl peroxide, 2 weight% of methylhexahydrophthalic anhydride and 10 weight% of polysebacic polyanhydride, and a B- stage process was performed and reliability of interconnection with the substrate was tested by fluxing an eutectic solder.
  • Eutectic solder balls having diameter of 20 mil were formed on a chip, and a first underfill layer and a second underfill layer were coated on an upper surface of a glass slide with a thickness of about 20 mil by stencil treatment.
  • a B-stage process was performed such that the glass slide coated with the underfill layer was put in a vacuum oven and heated under vacuum of 73.6 DHg vacuum degree at 130 0 C for 50 minutes, the glass slide was then flipped and placed on an FR-4 substrate such that the underfill layer-coated surface faces a copper finished surface of the FR-4 substrate, and the FR-4 substrate was placed on a heating plate preheated to 240 0 C.
  • the experimental example 2 was carried out on the same conditions as the first experimental example 1 except that dicumyl peroxide formulation and a substitute of methylhexahydrophthalic anhydride among the compositions of the experimental example 1 were used.
  • compositions of the first underfill layer and the second underfill layer 2 weight% of butyl peroctoate was used instead of dicumyl peroxide, 2 weight% of py- romellitic dianhydride was instead of methylhexahydrophthalic anhydride, and a B- stage process was performed and reliability of interconnection with the substrate was tested by fluxing an eutectic solder.
  • a nonviscous and void-free underfill coating can be formed in a B-stage process, and delamination or crack occurring in a reflow process can be prevented.

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Abstract

The present invention relates to a flip chip packaging method comprising the steps of forming a double layer type underfill layer having different curing temperatures on one surface of a semi¬ conductor wafer having a solder bump pattern; performing a B-stage process on the underfill layer to cure a layer having a relatively lower curing temperature among the double layer type underfill layer; dicing the semiconductor wafer into individual chips; aligning the individual chips on a substrate such that a surface of the underfill layer faces a surface of the substrate; and performing a reflow process with temperature capable of curing all of the double layer type underfill layer.

Description

Description
FLIP CHIP PACKAGING METHOD USING DOUBLE LAYER TYPE WAFER LEVEL UNDERFILL, FLIP CHIP PACKAGE MANUFACTURED USING THE SAME, AND SEMICONDUCTOR DEVICE FOR THE SAME Technical Field
[1] The present invention relates to flip chip packaging using an underfill, in particular, to a flip chip packaging method using a wafer level underfill having the improved cure characteristics, a flip chip package manufactured using the same, and a semiconductor device for the same. Background Art
[2] A flip chip bonding technique used widely in semiconductor packaging has a drawback that quality of products may be reduced by stresses applied to an assembly structure after thermal cycling due to a difference in CTE (Coefficient of Thermal Expansion) between a chip die and a substrate.
[3] To solve the problem, various underfill processes such as CUF (capillary underfill),
NUF (no-flow Underfill), molded underfill or wafer level underfill have been developed, which fill a gap between a chip die and a substrate with a polymeric en- capsulant to reinforce interconnect materials and absorb a portion of stresses occurring due to thermal cycling.
[4] Among the exemplary underfill processes, in particular, the wafer level underfill process coats a semiconductor wafer with an underfill encapsulant before dicing the semiconductor wafer into individual chips, thereby resulting in simple process and improved production efficiency.
[5] Prior arts related to the wafer level underfill process are disclosed in U.S. Patent
Application No. 09/648,777, Korean Patent Registration No. 621438 and Korean Patent Laid-Open Publication No. 2004-68145.
[6] The U.S. Patent Application No. 09/648,777 discloses a process which dispenses an underfill on a wafer having bumps to a level lower than the height of the bumps, removes a solvent to solidify the underfill, dices the wafer into individual chips, covers the bumps with a tacky film, mounts the chips to a substrate, and reflows the solder bumps and cures the underfill simultaneously.
[7] The Korean Patent Registration No. 621438 teaches a stack chip package of a three- dimensional stack structure using a photosensitive polymer, in which each of semiconductor chips with penetration electrodes has a photosensitive polymer layer formed on an upper surface thereof and the semiconductor chips are stacked by thermo- compression such that upper surfaces of the semiconductor chips face an upper surface of a wiring substrate, and a manufacturing method thereof.
[8] The Korean Patent Laid-Open Publication No. 2004-68145 suggests a wafer level underfill including a combination of different compositions having different curing temperatures or curing temperature ranges.
[9] However, the conventional wafer level underfill structures cannot completely prevent an electrical short caused by a filler existing near the surface thereof, and have a drawback of reduction in adhesion or electrical connection reliability after a B-stage process or a reflow process. Disclosure of Invention Technical Problem
[10] The present invention is designed to solve the problem, and therefore an object of the present invention is to provide a flip chip packaging method using a double layer type wafer level underfill having different curing systems, a flip chip package manufactured using the same, a semiconductor wafer for the same and a semiconductor chip for the same. Technical Solution
[11] In order to achieve the above-mentioned object, a flip chip packaging method according to a preferred embodiment of the present invention comprises (a) forming a double layer type underfill layer having different curing temperatures on one surface of a semiconductor wafer having a solder bump pattern; (b) performing a B-stage process on the underfill layer to cure a layer having a relatively lower curing temperature among the double layer type underfill layer; (c) dicing the semiconductor wafer into individual chips; (d) aligning the individual chips on a substrate such that a surface of the underfill layer faces a surface of the substrate; and (e) performing a reflow process with temperature capable of curing all of the double layer type underfill layer.
[12] Preferably, in the step (a), a first underfill layer and a second underfill layer are formed on the semiconductor wafer in sequence, and the curing temperature of the first underfill layer is relatively lower than the curing temperature of the second underfill layer.
[13] The first underfill layer contains a filler, and the second underfill layer does not contain a filler.
[14] And, the first underfill layer does not contain a fluxing agent, and the second underfill layer contains a fluxing agent.
[15] Preferably, the first underfill layer has a thickness corresponding to 70 to 90 % of a thickness of the entire underfill layer including the first underfill layer and the second underfill layer.
[16] Preferably, in the step (d), the chips are aligned with the substrate such that the solder bumps of the chips are contacted with contact pads of the substrate.
[17] The underfill layer may be formed by any one process selected from the group consisting of screen printing, stencil printing and spin coating.
[18] According to another aspect of the present invention, a flip chip package manufactured by the above-mentioned flip chip packaging method is provided.
[19] According to still another aspect of the present invention, a semiconductor wafer of a front-end semiconductor process, having a solder bump pattern and an underfill layer formed on one surface thereof is provided, wherein the underfill layer is formed of a double layer type underfill layer having different curing temperatures.
[20] According to yet another aspect of the present invention, a semiconductor chip provided through a dicing process and having a solder bump pattern and an underfill layer formed on one surface thereof is provided, wherein the underfill layer is formed of a double layer type underfill layer having different curing temperatures. Brief Description of the Drawings
[21] The present invention will be more fully described in the following detailed description, taken accompanying drawings, however, the description proposed herein is just a preferable example for the purpose of illustrations, not intended to limit the scope of the invention. In the drawings:
[22] FIG. 1 is a flow chart illustrating steps of a flip chip packaging method according to a preferred embodiment of the present invention.
[23] FIG. 2 is a process view illustrating processing steps of a semiconductor wafer and a semiconductor chip as a semiconductor device provided by the present invention.
[24] FIG. 3 is a cross-sectional view illustrating a configuration of a flip chip package according to the present invention. Mode for the Invention
[25] Hereinafter, preferred embodiments of the present invention are described in detail with reference to the accompanying drawings. Prior to the description, it should be understood that the terms used in the specification and the appended claims should not be construed as limited to general and dictionary meanings, but interpreted based on the meanings and concepts corresponding to technical aspects of the present invention on the basis of the principle that the inventor is allowed to define terms appropriately for the best explanation. Therefore, the description proposed herein is just a preferable example for the purpose of illustrations only, not intended to limit the scope of the invention, so it should be understood that other equivalents and modifications could be made thereto without departing from the spirit and scope of the invention. [26] FIGs. 1 and 2 show a flip chip packaging process according to a preferred embodiment of the present invention.
[27] Referring to FIGs. 1 and 2, first, as shown in FIG. 2(a) to (c), patterning 101 is performed on an active surface of a semiconductor wafer 100 and a solder bump pattern 102 are formed on the active surface of the semiconductor wafer 100 (SlOO).
[28] Next, as shown in FIG. 2(d), a first underfill layer 103 is formed on the active surface of the semiconductor wafer 100 having the solder bump pattern 102, and as shown in FIG. 2(e), a second underfill layer 104 is formed on the first underfill layer 103, so that the semiconductor wafer 100 has a double layer type underfill layer (SI lO).
[29] The first underfill layer 103 and the second underfill layer 104 may be formed by screen printing, stencil printing or spin coating.
[30] The first underfill layer 103 has such a curing system that the first underfill layer
103 is cured at a relatively lower temperature than the second underfill layer 104.
[31] The first underfill layer 103 contains main components including a thermosetting reaction resin, at least one thermal initiator, a crosslinkable resin such as epoxy, and a filler, and the second underfill layer 104 contains main components including a thermosetting reaction resin, at least one thermal initiator, a crosslinkable resin such as epoxy, and a fluxing agent.
[32] Preferably, the first underfill layer 103 contains a filler, but the second underfill layer 104 does not contain a filler. And, the first underfill layer 103 does not contain a fluxing agent, but the second underfill layer 104 contains a fluxing agent.
[33] Preferably, the thermosetting reaction resin includes vinyl eter, vinyl silane, a styrene compound, a bismaleide compound having a cinnamyl compound, or a thermosetting epoxy compound having a latent amine or imidazole curing agent. Preferably, the thermosetting reaction resin has a content of 5 to 30 weight% based on the entire underfill.
[34] Preferably, the thermal initiator includes an organic peroxide such as benzoyl peroxide or cumyl peroxide, an azo-based thermal initiator such as azobisisobuty- ronitrile, or a UV curing agent such as acetophenone, benzophenone or benzaldehyde, and the thermal initiator has a content of 0.1 to 10 weight%.
[35] Preferably, the epoxy resin includes bisphenol A and bisphenol F monofunctional and multifunctional glycidyl eter, fatty and aromatic epoxy, saturated and unsaturated epoxy, an alicyclic epoxy resin, or mixtures thereof. Preferably, the epoxy resin has a content of 10 to 70 weight% based on the entire underfill.
[36] The filler contained in the first underfill layer 103 includes an inorganic filler such as a nonconductive silica or calcium carbonate, or an organic filler such as an acryl rubber or tetra fluoroethylene to improve moisture resistance and control coefficient of thermal expansion. Preferably, the filler has a content of 30 to 70% based on the first underfill layer 103.
[37] The fluxing agent contained in the second underfill layer 104 removes a metal oxide from a contact pad of a substrate and prevent a reoxidation reaction. Preferably, the fluxing agent includes carboxylic acid or carboxylic anhydride, polysebacic polyanhydride, rosin gum, dodecandioic acid, or mixtures thereof.
[38] Preferably, the first underfill layer 103 and the second underfill layer 104 further contain an amine -based, anhydride -based or amide-based curing agent with a content of 1 to 10 weight%.
[39] Meanwhile, preferably, the first underfill layer 103 has a thickness corresponding to
70 to 90% of a thickness of the entire underfill layer including the first underfill layer 103 and the second underfill layer 104.
[40] In the case that the first underfill layer 103 is excessively thin, for example the thickness of the first underfill layer 103 is less than 70% of the thickness of the entire underfill layer, a filler is not sufficiently filled, thereby deteriorating the coefficient of thermal expansion, and in the case that the first underfill layer 103 is excessively thick, for example the thickness of the first underfill layer 103 is more than 90% of the thickness of the entire underfill layer, a filler is excessively distributed toward the substrate during a reflow process, which may cause an electrical short, and make it difficult to secure a sufficient thickness of the second underfill layer 104, thereby reducing flow characteristics of the second underfill layer 104.
[41] Continuously, a B-stage process for applying heat, for example, of 100 to 150 0C is performed to cure the first underfill layer 103 (S120), and subsequently, as shown in FIG. 2(f), a dicing process is performed to singulate the semiconductor wafer into individual chips (S 130).
[42] As shown in FIG. 3, the individual chips 100' separated through the dicing process are aligned with a substrate 200 (S 140), and a reflow process is performed (S150), so that the individual chips 100' are bonded to the substrate 200. Here, the semiconductor chip dies 100' are aligned with the substrate 200 such that the surface of the second underfill layer 104 faces the surface of the substrate 200 and the solder bumps 102 of the semiconductor chips 100' are contacted with contact pads 201 of the substrate 200.
[43] According to the reflow process, heat, for example, of 250 0C is applied to cure both of the first underfill layer 103 and the second underfill layer 104, so that interconnection is established between the semiconductor chips 100' and the substrate 200.
[44] Experimental example 1
[45] In the experimental example 1, the first underfill layer included 45 weight% of bisphenol A epichlorohydrin epoxy, 24.5 weight% of 2-phenoxy ethyl acrylate, 25 weight% of butylphenyl maleimide, 1.5 weight% of cobalt neodecanoate, 2 weight% of dicumyl peroxide, 2 weight% of methylhexahydrophthalic anhydride and 60 weight% of fused silica, the second underfill layer included 62 weight% of bisphenol A epichlorohydrin epoxy, 24 weight% of 2-phenoxyethyl acrylate, 10 weight% of 2-phenyl-4methyl imidazol, 2 weight% of dicumyl peroxide, 2 weight% of methylhexahydrophthalic anhydride and 10 weight% of polysebacic polyanhydride, and a B- stage process was performed and reliability of interconnection with the substrate was tested by fluxing an eutectic solder.
[46] Eutectic solder balls having diameter of 20 mil were formed on a chip, and a first underfill layer and a second underfill layer were coated on an upper surface of a glass slide with a thickness of about 20 mil by stencil treatment.
[47] And, a B-stage process was performed such that the glass slide coated with the underfill layer was put in a vacuum oven and heated under vacuum of 73.6 DHg vacuum degree at 130 0C for 50 minutes, the glass slide was then flipped and placed on an FR-4 substrate such that the underfill layer-coated surface faces a copper finished surface of the FR-4 substrate, and the FR-4 substrate was placed on a heating plate preheated to 240 0C.
[48] It was observed that areas of the solder balls were increased and the glass slide was seated closely on the upper surface of the substrate. Thus, it was found that the solder was fluxed and interconnection was established between the chip and the substrate.
[49] Meanwhile, it was found that a flat, nonviscosous and void-free coating was formed in the B-stage process.
[50] Experimental example 2
[51] The experimental example 2 was carried out on the same conditions as the first experimental example 1 except that dicumyl peroxide formulation and a substitute of methylhexahydrophthalic anhydride among the compositions of the experimental example 1 were used.
[52] Among the compositions of the first underfill layer and the second underfill layer, 2 weight% of butyl peroctoate was used instead of dicumyl peroxide, 2 weight% of py- romellitic dianhydride was instead of methylhexahydrophthalic anhydride, and a B- stage process was performed and reliability of interconnection with the substrate was tested by fluxing an eutectic solder.
[53] After a B-stage heating time passed, a glass slide was placed on a FR-4 substrate and gone through a reflow oven of a typical reflow temperature profile having a maximum temperature set to 250 0C.
[54] Like the experimental example 1 , it was observed that areas of solder balls were increased and the glass slide was seated closely on an upper surface of the substrate, and thus it was found that the solder was fluxed and interconnection was established between a chip and the substrate. [55] And, it was observed that a fillet of the underfill was formed well, and thus it was found that flowability and wettability of the underfill were excellent.
[56] As such, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. Industrial Applicability
[57] According to the present invention, through the double layer type underfill layer having differences in a curing system and use of a filler/fluxing agent, reliability of electrical and mechanical interconnection can be improved, and a process is simplified to reduce process costs.
[58] And, a nonviscous and void-free underfill coating can be formed in a B-stage process, and delamination or crack occurring in a reflow process can be prevented.

Claims

Claims
[1] A flip chip packaging method, comprising:
(a) forming a double layer type underfill layer having different curing temperatures on one surface of a semiconductor wafer having a solder bump pattern;
(b) performing a B-stage process on the underfill layer to cure a layer having a relatively lower curing temperature among the double layer type underfill layer;
(c) dicing the semiconductor wafer into individual chips;
(d) aligning the individual chips on a substrate such that a surface of the underfill layer faces a surface of the substrate; and
(e) performing a reflow process with temperature capable of curing all of the double layer type underfill layer.
[2] The flip chip packaging method according to claim 1 , wherein, in the step (a), a first underfill layer and a second underfill layer are formed on the semiconductor wafer in sequence, and wherein the curing temperature of the first underfill layer is relatively lower than the curing temperature of the second underfill layer. [3] The flip chip packaging method according to claim 2, wherein the first underfill layer contains a filler, and the second underfill layer contains no filler. [4] The flip chip packaging method according to claim 3, wherein the filler has a content of 30 to 70 weight% based on the first underfill layer. [5] The flip chip packaging method according to claim 2, wherein the first underfill layer contains no fluxing agent, and the second underfill layer contains a fluxing agent. [6] The flip chip packaging method according to claim 2, wherein the first underfill layer has a thickness corresponding to 70 to 90 % of a thickness of the entire underfill layer including the first underfill layer and the second underfill layer. [7] The flip chip packaging method according to claim 1, wherein, in the step (d), the chips are aligned such that the solder bumps of the chips are contacted with contact pads of the substrate. [8] The flip chip packaging method according to claim 1, wherein the underfill layer is formed by any one process selected from the group consisting of screen printing, stencil printing and spin coating. [9] A flip chip package manufactured by the flip chip packaging method defined in any one of the claims 1 to 8. [10] A semiconductor wafer of a front-end semiconductor process, having a solder bump pattern and an underfill layer formed on one surface thereof, wherein the underfill layer is formed of a double layer type underfill layer having different curing temperatures. [11] The semiconductor wafer according to claim 10, wherein, in the step (a), a first underfill layer and a second underfill layer are formed on the semiconductor wafer in sequence, and wherein the curing temperature of the first underfill layer is relatively lower than the curing temperature of the second underfill layer. [12] The semiconductor wafer according to claim 11, wherein the first underfill layer contains a filler, and the second underfill layer contains no filler. [13] The semiconductor wafer according to claim 12, wherein the filler has a content of 30 to 70 weight% based on the first underfill layer. [14] The semiconductor wafer according to claim 11, wherein the first underfill layer contains no fluxing agent, and the second underfill layer contains a fluxing agent. [15] The semiconductor wafer according to claim 11 , wherein the first underfill layer has a thickness corresponding to 70 to 90 % of a thickness of the entire underfill layer including the first underfill layer and the second underfill layer. [16] A semiconductor chip provided through a dicing process and having a solder bump pattern and an underfill layer formed on one surface thereof, wherein the underfill layer is formed of a double layer type underfill layer having different curing temperatures. [17] The semiconductor chip according to claim 16, wherein the underfill layer includes a first underfill layer and a second underfill layer formed from a surface of a die in sequence, and wherein the first underfill layer has a relatively lower curing temperature than the second underfill layer. [18] The semiconductor chip according to claim 17, wherein the first underfill layer contains a filler, and the second underfill layer contains no filler. [19] The semiconductor chip according to claim 18, wherein the filler has a content of 30 to 70 weight% based on the first underfill layer. [20] The semiconductor chip according to claim 17, wherein the first underfill layer contains no fluxing agent, and the second underfill layer contains a fluxing agent. [21] The semiconductor chip according to claim 17, wherein the first underfill layer has a thickness corresponding to 70 to 90 % of a thickness of the entire underfill layer including the first underfill layer and the second underfill layer.
PCT/KR2008/001087 2008-02-25 2008-02-25 Flip chip packaging method using double layer type wafer level underfill, flip chip package manufactured using the same, and semiconductor device for the same WO2009107880A1 (en)

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EP2842735A1 (en) * 2013-09-03 2015-03-04 Rohm and Haas Electronic Materials LLC Pre-applied underfill
EP2960929A1 (en) * 2014-06-23 2015-12-30 Rohm and Haas Electronic Materials LLC Pre-applied underfill
CN105489620A (en) * 2014-10-03 2016-04-13 株式会社东芝 Method for manufacturing solid-state imaging device and method for manufacturing camera module

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JP2003007916A (en) * 2001-06-19 2003-01-10 Sanyo Electric Co Ltd Method of manufacturing circuit device
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JP2003007916A (en) * 2001-06-19 2003-01-10 Sanyo Electric Co Ltd Method of manufacturing circuit device
JP2004228152A (en) * 2003-01-20 2004-08-12 Shinko Electric Ind Co Ltd Wafer dicing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2842735A1 (en) * 2013-09-03 2015-03-04 Rohm and Haas Electronic Materials LLC Pre-applied underfill
EP2960929A1 (en) * 2014-06-23 2015-12-30 Rohm and Haas Electronic Materials LLC Pre-applied underfill
CN105489620A (en) * 2014-10-03 2016-04-13 株式会社东芝 Method for manufacturing solid-state imaging device and method for manufacturing camera module

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