TWI246364B - Method for making a semiconductor device - Google Patents

Method for making a semiconductor device Download PDF

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Publication number
TWI246364B
TWI246364B TW93106433A TW93106433A TWI246364B TW I246364 B TWI246364 B TW I246364B TW 93106433 A TW93106433 A TW 93106433A TW 93106433 A TW93106433 A TW 93106433A TW I246364 B TWI246364 B TW I246364B
Authority
TW
Taiwan
Prior art keywords
conductive
mentioned
semiconductor device
manufacturing
resin
Prior art date
Application number
TW93106433A
Other languages
English (en)
Other versions
TW200501839A (en
Inventor
Kiyoshi Mita
Original Assignee
Sanyo Electric Co
Kanto Sanyo Semiconductors Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co, Kanto Sanyo Semiconductors Co filed Critical Sanyo Electric Co
Publication of TW200501839A publication Critical patent/TW200501839A/zh
Application granted granted Critical
Publication of TWI246364B publication Critical patent/TWI246364B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02G—INSTALLATION OF ELECTRIC CABLES OR LINES, OR OF COMBINED OPTICAL AND ELECTRIC CABLES OR LINES
    • H02G7/00—Overhead installations of electric lines or cables
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/12—Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B17/00—Insulators or insulating bodies characterised by their form
    • H01B17/02—Suspension insulators; Strain insulators
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
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    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

1246364 予乂貼口所而I ’因此’在半導體裝置製造中無法予以免 f該支持基板。復因支持基板HH具有吸收熱應力的效 月b，故極難於半導體裝置的構造上免除支持基板1 ^。 本^明為有鑑於上述問題而作，因而本發明的主要目 的，係在於提供-種小型化及薄型化，且具有優異之端子 部連接可靠性之半導體裝置的製造方法。 [解決問題的手段] •本發明係為一種半導體震置的製造方法，此方法具 備·將第1導電羯之除了成為端子以外部位加以钱刻，由 此在上述第1導電箔表面形成突出之凸狀端子部的製程； 將樹脂片疊合在上述第！導電％卜表矛 乐1 ¥電治上以埋設上述端子部的製 程，將第2導電箔疊合在上 製程；蚀刻第2導電⑽=1 構成疊層片的 ¥電，自而形成導電圖案的製程；將上述導 電圖案及上述端子部，予以雷备、串杜μ & 電軋連接的製程：將上述各端 子：彼此予以電氣分離的製帛；在上述疊層片固定半導體 ^，且將上述半導體元件與上述導電圖案，予以電氣連 接的製程；以及在上述疊層 ” 、十、坐11 且層片表面形成封裴樹脂以覆蓋上 述+ V體70件的製程，為其特徵者。 :且本發明係由背面㈣上述第丨導電羯，將上述各 鈿子部，予以電氣分離者。 r上月’上述樹脂片係以可溶性樹脂製成，且去 牙、上述树月曰片，使上述端子部側面露出者。 又在本發明中’上述半導體元件係以面朝上方式，藉 315626 6 1246364 ㈣如1:二(A):準備以銅或銘等金屬為主材的第1導電 ' "弟1導電箔10之厚度’即以可形成後續製程 之端子部12範圍為準'予以設定。然後，在第i導電‘ 1了Ο:::定形成端子部12部位形成“膜11，而對除 而。以外之部位進行濕式蝕刻或乾式蝕刻，將端子 部12形成為凸狀。 肝而子 再如第1圖（B)，在其由抗蝕膜11露出部分之第i導 電V自1 〇，形成分離溝丨3。尤於施行濕式蝕刻時，端子部 12側面將變成彎曲狀’故得於後續製程使之與樹脂㈣的 密接強度提升。由而，可將端子部12形成為凸出狀。施行 蝕刻作業後，須將抗蝕膜11予以剝離。 丁 在本發明的第2製程，係如第2圖所示，將樹脂片Μ 重疊於第1導電箔10，以埋設端子部12。該樹脂片丨4可 使用玻璃布浸潰於樹脂之B級（B stage)半固化預浸片 (Prepreg sheet)。該重疊作業可由真空壓機進行。 在本發明的第3製程，係如第3圖所示，係將背面形 成有樹脂層1 5的第2導電箔1 6，以樹脂層1 5為下面予以 貼合為疊層片（Uminate)18。此時之樹脂層15亦可用上述 之預浸片。第2導電鎢1 6即可用能形成微細型樣之較第1 導電箔10為薄的導電箔為材料。而該第2導電箔} 6材， 亦可如第1導電箔1 0，得採用以銅或鋁等為主材的金屬。 由此製程，巧*形成藉由樹脂重疊之第1導電箔1 0及第2 導電箔16的疊層片18。 本發明的第4製程，如第4圖所示，係以蝕刻第2導 315626 8 1246364 3〇D。於此形態中’半導體元件22係以面朝下如Μ。叫 方式組裝，並藉由塊形（bump)電極25與導電圖案17成為 電氣連接。如上述，導電圖案17可形成為微細圖案，因而， 半導體元件22之電極間距狹窄時’也能予以充分對應。 如以上所述，本實施形態係以不脫離本發明要旨範 圍，可有種種變化，亦能容許如下述之變更。 如第2圖，係將樹脂片14堆疊於第！導電箔ι〇上者。 但得使用與銅箱堆積而成的樹脂片14。若如上述即第3 圖中之樹脂片14及樹脂層15為同一樹脂層，因而得將構 成半導體裝置的構成要素予以減少。 [發明的效果] 本發明的功效如下： 將構成端子部12之第1導電箔丨〇，及構成導電圖案 的第2導電箔16藉由樹脂層堆積成為多層疊層片丨8。因 此，可製造具有不須習用例之支持基板的多層配線構造之 半導體裝置。 又因彳于以採用可溶性樹脂為堆疊第1導電箔1 〇及第2 ^電娼1 6的樹脂，故可獲得露出端子部側面的接腳型端子 構造。 【圖式簡單說明】 第1圖（A)及（B)係說明本發明半導體裝置製造方法之 剖面圖。 第2圖係說明本發明半導體裝置製造方法之剖面圖。 第3圖係說明本發明半導體裝置製造方法之剖面圖。 315626 I246364 第4圖係說明本發明半導體裝置製造方法之剖面圖。 第5圖係說明本發明半導體裝置製造方法之剖面圖。 第6圖係說明本發明半導體裝置製造方法之剖面圖。 第7圖係說明本發明半導體裝置製造方法之剖面圖。 f 8圖係說明本發日月半導體裝置製造方法之剖面圖。 第9圖係說明本發明+導體裝置製W法之剖面圖。 第1〇圖係說明本發明半導體裝置製造方法之剖面 第11圖係說明本發明半導體裴置製造方法之剖面 第1 2圖（A)係習用半導體裝置製造方法之剖面圖 一 -叫丨/丁、白用千導體裝置製造方法之背面圖c [元件符號說明] 10 第1導電箔 1卜 21 抗敍膜 12 端子部 13 分離溝 14 樹脂片 15 樹脂層 16 第2導電箔 17 導電型樣 18 疊層片 19 穿通孔 20 連接部 11、 102 半導體元件 23 、 103 金屬細絲 24、 107 封裝樹脂 25 塊形電極 26 散熱電極 30A、30B 、30C、30D、100半導體裝置 101 支持基板 104 電極 105 背面電極 106 貫穿孔 109 電鍍膜 315626 12

Claims (1)

  1. /V ^ 1246364 拾、申請專利範圍： 喱千導體裝置 货、丹備- 將第1導電箔之除了虑A妒工”， 战马立而子以外夕立R μ a 左 刻，而在上述第1導電笮# & 卜之邛位加以蝕 矛夺电v白表面形成突 製程； &八山〈凸狀端子部的 導電羯上以埋設上述端 將樹脂片疊合在上述第 子部的製程； 將第 的製程； 2導電箔疊合在上述樹脂片 上以構成疊層片 名虫刻苐2導電箱以形成導電 將上述導電圖案及上述端子 程： 圖案的製程； 部’予以電氣連接的製 將上述各端子部，予以彼此電氣分離的製程； 將半導體元件固定在上述疊層片，且將上述半導體 70件與上述導電圖案’予以電氣連接的製程，以及 一在上述疊層片表面形成封裝樹脂以覆蓋上述半導 體元件的製程者。 2.如申請專利範圍帛i項之半導體裝置製造方法，係由背 面蝕刻上述第Ϊ導電笛’將上述各端子部彼此予以電氣 分離者。 3.如申請專利範圍第丨項之半導體裝置製造方法其中 上述樹脂片係由可溶性樹脂所製成，且係以去除 述樹脂片，使上述端子部側面露出者。 4·如申請專利範圍第1項之半導體裝置製造方法，其中 315626 13 1246364 上述半導體元件传 ’並藉由 電圖案予 丁你从面朝上(face_uD、士」 孟屬細絲，將上述丰導— 工 ’上述牛導體兀件之電極與上 以電氣連接者。 V 如申请專利範圍第丨項之半導體裝置製造方法，其中， 另上述半‘體元件係以面朝下（^扣卜方式組 放，且藉由塊形電極，並將上述半導體元件之電極與上 述導電圖案予以電氣連接者。 315626 14
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