CN1574260A - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

Info

Publication number
CN1574260A
CN1574260A CNA2004100318701A CN200410031870A CN1574260A CN 1574260 A CN1574260 A CN 1574260A CN A2004100318701 A CNA2004100318701 A CN A2004100318701A CN 200410031870 A CN200410031870 A CN 200410031870A CN 1574260 A CN1574260 A CN 1574260A
Authority
CN
China
Prior art keywords
terminal
conductive foil
semiconductor device
semiconductor element
conductive pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2004100318701A
Other languages
English (en)
Other versions
CN1301544C (zh
Inventor
三田清志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northeast Sanyo Semi-Conductive Co Ltd, Sanyo Electric Co Ltd filed Critical Northeast Sanyo Semi-Conductive Co Ltd
Publication of CN1574260A publication Critical patent/CN1574260A/zh
Application granted granted Critical
Publication of CN1301544C publication Critical patent/CN1301544C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02GINSTALLATION OF ELECTRIC CABLES OR LINES, OR OF COMBINED OPTICAL AND ELECTRIC CABLES OR LINES
    • H02G7/00Overhead installations of electric lines or cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/12Testing dielectric strength or breakdown voltage ; Testing or monitoring effectiveness or level of insulation, e.g. of a cable or of an apparatus, for example using partial discharge measurements; Electrostatic testing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01BCABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B17/00Insulators or insulating bodies characterised by their form
    • H01B17/02Suspension insulators; Strain insulators
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15182Fan-in arrangement of the internal vias
    • H01L2924/15183Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

一种半导体装置的制造方法,其提供连接可靠性优良的半导体装置,其包括:通过蚀刻除构成端子12的位置以外的第一导电箔10,在第一导电箔10表面形成凸状地突起的端子部12的工序;使树脂片14重叠在第一导电箔10上,以埋入端子部12的工序;通过将树脂层15作为下面,使背面形成有树脂层15的第二导电箔16重叠在树脂片14上,构成层积片18的工序;通过蚀刻第二导电箔16形成导电图案17的工序;将导电图案17和端子部12电连接的工序;将端子部12相互间电分离的工序;在层积片18上固定半导体元件22,将半导体元件22和导电图案17电连接的工序;在层积片18表面形成密封树脂24,以覆盖半导体元件22的工序。

Description

半导体装置的制造方法
技术领域
本发明涉及具有支承衬底的半导体装置。
背景技术
参照图12说明现有的安装衬底及半导体装置。图12(A)是半导体装置100的剖面图,图12(B)是其背面图(参照专利文献1)。
参照图12(A),在由玻璃环氧树脂等构成的支承衬底101上面形成由铜箔等构成的电极104。在支承衬底101的背面形成背面电极105,并利用敷金属夹层孔106和电极104连接。另外,利用镀膜109覆盖电极104及背面电极105。
作为半导体元件的半导体元件102被固定在支承衬底101上,并介由金属细线103和电极104连接。另外,形成覆盖半导体元件102的密封树脂107。
参照图12(B),在支承衬底101的背面与外周部平行并排列两列设有背面电极105。
专利文献1
特开平11-233688号公报(参照图7)
发明内容
在所述的半导体装置100中,由于采用支承衬底101,故限制了其薄型化及小型化。另外,由于在使用状态下温度变化会产生热应力,因此自背面电极105至电极104的连接路经的可靠性有问题。支承衬底101为了在制造工序中使电极104及背面电极105粘合是必需的,难以不使用该衬底制造半导体装置。另外,由于支承衬底101具有吸收热应力的作用,故难以不使用支承衬底101构成半导体装置。
本发明是鉴于所述的问题点而开发的,本发明的主要目的在于,提供小型化及薄型化且端子部的连接可靠性优良的半导体装置的制造方法。
本发明包括:通过蚀刻除构成端子的位置以外的第一导电箔,在所述第一导电箔表面形成凸状地突起的端子部的工序;使树脂片重叠在所述第一导电箔上,以埋入所述端子部的工序;通过使第二导电箔重叠在所述树脂片构成层积片上的工序;通过蚀刻所述第二导电箔形成导电图案的工序;将所述导电图案和所述端子部电连接的工序;将所述端子部相互间电分离的工序;在所述层积片上固定半导体元件,将所述半导体元件和所述导电图案电连接的工序;在所述层积片表面形成密封树脂,以覆盖所述半导体元件的工序。
本发明通过由背面蚀刻所述第一导电箔,将所述端子相互之间电分离。
本发明所述树脂片由可溶树脂构成,通过除去所述树脂片,露出所述端子部的侧面。
本发明所述半导体元件由面朝上接合法连接,并介由金属细线将所述半导体元件的电极和所述导电图案连接。
另外,本发明所述半导体元件通过倒装法安装,并利用补片电极将所述半导体元件的电极和所述导电图案连接。
附图说明
图1是说明本发明半导体装置制造方法的剖面图(A)、剖面图(B);
图2是说明本发明半导体装置制造方法的剖面图;
图3是说明本发明半导体装置制造方法的剖面图;
图4是说明本发明半导体装置制造方法的剖面图;
图5是说明本发明半导体装置制造方法的剖面图;
图6是说明本发明半导体装置制造方法的剖面图;
图7是说明本发明半导体装置制造方法的剖面图;
图8是说明本发明半导体装置制造方法的剖面图;
图9是说明本发明半导体装置制造方法的剖面图;
图10是说明本发明半导体装置制造方法的剖面图;
图11是说明本发明半导体装置制造方法的剖面图;
图12是说明现有的半导体装置的剖面图(A)、背面图(B)。
具体实施方式
以下,参照附图详细说明本发明半导体装置的制造方法。本发明半导体装置的制造方法包括:通过蚀刻除构成端子12的位置以外的第一导电箔10,在第一导电箔10表面形成凸状地突起的端子部12的工序;使树脂片14重叠在第一导电箔10上,以埋入端子部12的工序;通过将树脂层15作为下面,使背面形成有树脂层15的第二导电箔16重叠在树脂片14上,构成层积片18的工序;通过蚀刻第二导电箔16形成导电图案17的工序;将导电图案17和端子部12电连接的工序;将端子部12相互间电分离的工序;在层积片18上固定半导体元件22,而后将半导体元件22和导电图案17电连接的工序;在层积片18表面形成密封树脂24,以覆盖半导体元件22的工序。以下,说明所述各工序。
参照图1,本发明的第一工序在于,通过蚀刻除构成端子12的位置以外的第一导电箔10,在第一导电箔10表面形成凸状地突起的端子部12。
参照图1(A),准备以铜或铝等金属为主材料的第一导电箔10。第一导电箔10的厚度在以后的工序中被设定在可形成端子部12的范围内。而后,在除预定形成端子部12的位置以外的区域的第一导电箔10表面形成抗蚀剂11。通过进行湿式蚀刻或干式蚀刻,凸状地形成端子部12。
参照图1(B),在自抗蚀剂11露出的位置的第一导电箔10上形成分离槽13。特别是在进行湿式蚀刻时,端子部12的侧面形成弯曲,提高在以后的工序中和树脂材料的粘附强度。由此,端子部12被凸状地形成。进行蚀刻后将抗蚀剂11剥离。
参照图2,本发明的第二工序在于,使树脂片14重叠在第一导电箔10上,以埋入端子部12。树脂片14可采用在玻璃纤维布中含浸树脂的B级预浸树脂片。另外,该重叠作业可通过真空按压进行。
参照图3,本发明的第三工序在于,通过将树脂层15作为下面,使背面形成有树脂层15的第二导电箔16重叠在树脂片14上,构成层积片18。在此,树脂层15可采用所述的预浸树脂片。第二导电箔16可采用比第一导电箔更薄的导电箔,以形成微细的图案。另外,第二导电箔16的材料可采用和第一导电箔10相同的,以铜或铝为主体的金属。在该工序中,形成利用树脂层积具有端子部12的第一导电箔10和第二导电箔16而构成的层积片18。
参照图4,本发明的第四工序在于,通过蚀刻第二导电箔16形成导电图案17。在此,也通过使用抗蚀剂的干式蚀刻或湿式蚀刻选择性地除去第二导电箔16。
参照图5及图6,本发明的第五工序在于,将导电图案17和端子部12电连接。首先,参照图5,穿设贯通导电图案17、树脂层15及树脂片的通孔19。形成通孔19的方法有使用蚀刻和激光的方法。首先,利用蚀刻局部地除去形成通孔19的位置的导电图案17。而后,将除去的导电图案17下方的树脂层15及树脂片14利用激光照射除去。在此使用的激光可采用二氧化碳激光。
其次,参照图6,在利用所述方法形成的通孔19中形成连接部20。首先,清洗除去由先前工序形成的通孔19的树脂残渣(デスミア)。而后,利用无电解镀敷或电镀在通孔19的侧面形成由铜等金属构成的连接部20。利用该连接部20将导电图案17和端子部12电连接。在此,也可以进行填充镀敷,利用镀敷材料填充通孔19。
参照图7,本发明的第六工序在于,将端子部12相互间电分离。
具体地说,通过除去第一导电箔10的背面直至分离槽13内填充的树脂片14露出,将各端子部12电气独立。该工序可通过将第一导电箔10的背面通过整面地湿式蚀刻进行。另外,露出端子部12的位置以外的层积片18的背面利用抗蚀剂21覆盖。除和内装的元件电连接的位置以外,导电图案17的表面也可以利用抗蚀剂21覆盖。
参照图8,本发明的第七工序在于,将半导体元件22和导电图案17电连接,在层积片18的表面形成密封树脂24,以覆盖半导体元件22。利用粘结剂在层积片18上固定半导体元件22,并介由金属细线23电连接半导体元件22的电极和导电图案17。密封树脂24在层积片18的表面形成,覆盖半导体元件22及金属细线23。
由所述工序制造半导体装置30A,在露出的端子部12背面粘附焊锡等焊剂,在安装衬底等面装。另外,通过在半导体元件22下方形成散热电极26,可提高装置全体的散热性。另外,半导体装置30A具有多层配线结构,由薄的第二导电箔形成的导电图案17可形成微细的电路图案。由于构成端子部12的第一导电箔10较厚地形成,故直至进行树脂密封的工序之前具有支承整体的作用。
参照图9说明另一实施例的半导体装置30B的结构。在此,树脂片14被除去,形成端子部12侧面露出的结构。因此,形成具有PIN型端子部12的半导体装置。此时,树脂片14由碱可溶树脂构成,在进行各端子部12的分离后,通过由碱性药剂熔融树脂片14除去树脂片14。
参照图10说明另一实施例的半导体装置30C。在此,不形成散热用电极,而网状形成PIN型端子部12。从而,可提供具有多引脚结构的半导体装置。
参照图11说明另一实施例的半导体装置30C。在此,利用倒装法安装半导体元件22,并介由补片电极25和导电图案17电连接。如上所述,由于导电图案17可形成微细的图案,因此,即使半导体元件22的电极间距窄,也可以充分地对应。
另外,所述的本实施例可在不脱离本发明要旨的范围内进行种种变更。例如,可进行如下变更。
参照图2,在此,在第一导电箔上层积了树脂片14,但在此,可采用和铜箔层积的树脂片14。由此,参照图3,树脂片14和树脂层15由相同的树脂材料构成。从而,可减少构成半导体装置的构成要素。
在本发明中,可得到如下所示的效果。
介由树脂层层积构成端子部12的第一导电箔10和构成导电图案的第二导电箔16,构成多层的层积片18。从而,不需要现有例的支承衬底即可制造有多层配线结构的半导体装置。
另外,层积第一导电箔10和第二导电箔16的树脂采用可溶树脂,可得到端子部侧面露出的PIN型端子结构。

Claims (5)

1、一种半导体装置的制造方法,其特征在于,其包括:通过蚀刻除构成端子的位置以外的第一导电箔,在所述第一导电箔表面形成凸状地突起的端子部的工序;使树脂片重叠在所述第一导电箔上,将所述端子部埋入的工序;通过使第二导电箔重叠在所述树脂片上构成层积片的工序;通过蚀刻所述第二导电箔形成导电图案的工序;将所述导电图案和所述端子部电连接的工序;将所述端子部相互间电分离的工序;在所述层积片上固定半导体元件,将所述半导体元件和所述导电图案电连接的工序;在所述层积片表面形成密封树脂,覆盖所述半导体元件的工序。
2、如权利要求1所述的半导体装置的制造方法,其特征在于,通过由背面蚀刻所述第一导电箔,将所述端子相互之间电分离。
3、如权利要求1所述的半导体装置的制造方法,其特征在于,所述树脂片由可溶树脂构成,通过除去所述树脂片,露出所述端子部的侧面。
4、如权利要求1所述的半导体装置的制造方法,其特征在于,所述半导体元件由面朝上接合法连接,并介由金属细线将所述半导体元件的电极和所述导电图案连接。
5、如权利要求1所述的半导体装置的制造方法,其特征在于,所述半导体元件通过倒装法安装,并介由补片电极将所述半导体元件的电极和所述导电图案连接。
CNB2004100318701A 2003-06-13 2004-03-30 半导体装置的制造方法 Expired - Fee Related CN1301544C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2003168581A JP4266717B2 (ja) 2003-06-13 2003-06-13 半導体装置の製造方法
JP168581/03 2003-06-13
JP168581/2003 2003-06-13

Publications (2)

Publication Number Publication Date
CN1574260A true CN1574260A (zh) 2005-02-02
CN1301544C CN1301544C (zh) 2007-02-21

Family

ID=33509055

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100318701A Expired - Fee Related CN1301544C (zh) 2003-06-13 2004-03-30 半导体装置的制造方法

Country Status (5)

Country Link
US (1) US6987030B2 (zh)
JP (1) JP4266717B2 (zh)
KR (1) KR100582145B1 (zh)
CN (1) CN1301544C (zh)
TW (1) TWI246364B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102054814B (zh) * 2009-11-06 2012-07-25 欣兴电子股份有限公司 无核心层封装基板及其制法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7176055B2 (en) * 2001-11-02 2007-02-13 Matsushita Electric Industrial Co., Ltd. Method and apparatus for manufacturing electronic component-mounted component, and electronic component-mounted component
US7459345B2 (en) * 2004-10-20 2008-12-02 Mutual-Pak Technology Co., Ltd. Packaging method for an electronic element
JP4961848B2 (ja) * 2006-06-12 2012-06-27 日本電気株式会社 金属ポストを有する配線基板、半導体装置及び半導体装置モジュールの製造方法
US9281218B2 (en) * 2006-08-30 2016-03-08 United Test And Assembly Center Ltd. Method of producing a semiconductor package
JP5081578B2 (ja) * 2007-10-25 2012-11-28 ローム株式会社 樹脂封止型半導体装置
TWI554171B (zh) * 2014-09-15 2016-10-11 欣興電子股份有限公司 埋入式導電配線的製作方法
JP6577373B2 (ja) * 2016-01-18 2019-09-18 新光電気工業株式会社 リードフレーム及びその製造方法、半導体装置
US10325842B2 (en) * 2017-09-08 2019-06-18 Advanced Semiconductor Engineering, Inc. Substrate for packaging a semiconductor device package and a method of manufacturing the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2994171B2 (ja) * 1993-05-11 1999-12-27 株式会社東芝 半導体装置の製造方法および封止用部材の製造方法
US6329711B1 (en) * 1995-11-08 2001-12-11 Fujitsu Limited Semiconductor device and mounting structure
EP0913429B1 (en) * 1997-10-29 2005-12-28 Hitachi Chemical Company, Ltd. Siloxane-modified polyamideimide resin composition adhesive film, adhesive sheet and semiconductor device
KR100253363B1 (ko) * 1997-12-02 2000-04-15 김영환 반도체 패키지용 기판과 그 기판을 이용한 랜드 그리드 어레이반도체 패키지 및 그들의 제조 방법
JP3481444B2 (ja) * 1998-01-14 2003-12-22 シャープ株式会社 半導体装置及びその製造方法
EP1143509A3 (en) * 2000-03-08 2004-04-07 Sanyo Electric Co., Ltd. Method of manufacturing the circuit device and circuit device
JP2003007916A (ja) * 2001-06-19 2003-01-10 Sanyo Electric Co Ltd 回路装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102054814B (zh) * 2009-11-06 2012-07-25 欣兴电子股份有限公司 无核心层封装基板及其制法

Also Published As

Publication number Publication date
US20040253769A1 (en) 2004-12-16
CN1301544C (zh) 2007-02-21
KR20040107359A (ko) 2004-12-20
JP4266717B2 (ja) 2009-05-20
KR100582145B1 (ko) 2006-05-22
TWI246364B (en) 2005-12-21
US6987030B2 (en) 2006-01-17
JP2005005545A (ja) 2005-01-06
TW200501839A (en) 2005-01-01

Similar Documents

Publication Publication Date Title
CN1182761C (zh) 印刷电路板及其制造方法
CN1315185C (zh) 包括载体的电子器件和制造该电子器件的方法
CN1197439C (zh) 印刷线路板和显示装置
EP1377141B1 (en) Printed circuit board, method for producing same and semiconductor device
CN1215742C (zh) 印刷电路板的焊盘及其形成方法
CN1193425C (zh) 用于半导体器件的多层基板
CN100568489C (zh) 电路模块及其制造方法
CN1491076A (zh) 布线基板的制备方法
CN1949467A (zh) 无芯基板及其制造方法
CN1678169A (zh) 印制线路板及其制造方法
CN1784121A (zh) 制造具有薄核心层的印刷电路板的方法
CN102763494B (zh) 导体结构元件及其制造方法
KR20070059186A (ko) 상호접속 소자를 제조하는 구조와 방법, 및 이 상호접속소자를 포함하는 다층 배선 기판
CN1728923A (zh) 具有液晶聚合物覆盖层的刚柔结合pcb及其制造方法
CN100512597C (zh) 一种制造电路板的方法
KR100757910B1 (ko) 매립패턴기판 및 그 제조방법
CN1234262C (zh) 用于印刷电路板的包层板
CN1301544C (zh) 半导体装置的制造方法
CN1244148C (zh) 电子元件及其制造方法
CN1993021A (zh) 用于制造配线基板的方法
CN1675766A (zh) 电引线架的制造方法,表面安装的半导体器件的制造方法和引线架带
CN1206729C (zh) 半导体装置及其制造方法、电路板和电子仪器
TW200919676A (en) Packaging substrate structure having capacitor embedded therein and method for manufacturing the same
CN100579339C (zh) 电路板的制造方法及减少电路板内埋元件电极接点厚度的方法
CN1684253A (zh) 半导体器件的凸点结构和制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20070221

Termination date: 20210330