CN100336207C - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN100336207C
CN100336207C CNB2004100319992A CN200410031999A CN100336207C CN 100336207 C CN100336207 C CN 100336207C CN B2004100319992 A CNB2004100319992 A CN B2004100319992A CN 200410031999 A CN200410031999 A CN 200410031999A CN 100336207 C CN100336207 C CN 100336207C
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conductive pattern
semiconductor device
substrate
plate wire
semiconductor element
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CN1551337A (zh
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三田清志
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Northeast Sanyo Semi-Conductive Co Ltd
Sanyo Electric Co Ltd
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Abstract

一种半导体装置及其制造方法，可提高安装衬底和密封树脂的可靠性。本发明的半导体装置(10A)包括如下结构：安装衬底(11)，其周边部具有台阶部(15)；第一导电图案(12)及第二导电图案(16)，在安装衬底(11)的表面及背面形成；半导体元件(13)，其被固定在安装衬底(11)上，和第一导电图案(12)电连接；密封树脂，覆盖安装衬底(11)表面及台阶部(15)，密封半导体元件(13)。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置，特别是涉及在安装衬底表面形成的焊盘上覆盖镀膜的半导体装置及其制造方法。
背景技术
参照图7说明现有型的半导体装置100的结构(参照下述专利文献1)。
在由柔性板或玻璃环氧树脂衬底构成的安装衬底104表面形成第一焊盘105，并在背面形成和第一焊盘105电连接的第二焊盘106。介由贯通安装衬底104的孔将第一焊盘105和第二焊盘106电连接。
半导体元件101被固定在安装衬底104上，并利用金属细线102和第一焊盘105电连接。另外，利用密封树脂103密封半导体元件101和安装衬底104的表面。
专利文献1
特开2000-174169号公报
发明内容
但是，在所述的半导体装置100中，密封半导体元件101的密封树脂103仅覆盖安装衬底104的表面。另外，由玻璃环氧树脂构成的安装衬底104和密封树脂103的密封性低下。从而，具有安装衬底104和密封树脂103的密封性的问题。
另外，在第一焊盘105或第二焊盘106上施行电镀时，必须形成连接所述焊盘相互之间的镀线。此时，该镀线自密封树脂103和安装衬底104的界面露出到外部，故具有半导体装置的可靠性低下的问题。另外，利用MAP(Multi Area Package)等制造方法制造多个半导体装置时，在进行各半导体装置分离的切割工序中包括镀线也进行分离。从而，具有沿外部露出的镀线向半导体装置内部侵入水分的问题。
本发明是鉴于所述的问题而产生的，本发明的主要目的在于，提供使安装衬底和密封树脂的可靠性提高的半导体装置及其制造方法。
本发明的半导体装置具体如下特征，其包括：由树脂构成的安装衬底，其周边部具有台阶部；导电图案，其在所述安装衬底的表面形成；半导体元件，其被固定在所述安装衬底上，和所述导电图案电连接；密封树脂，覆盖所述安装衬底表面及所述台阶部，密封所述半导体元件，所述导电图案延伸到所述台阶部。
本发明半导体装置的制造方法包括如下工序：在衬底表面形成构成由焊盘及自所述焊盘向周边部延伸的镀线构成的组件和电连接所述组件的所述镀线的共通镀线的第一导电图案的工序；在所述衬底背面形成和所述第一导电图案电连接的第二导电图案的工序；通过电镀法使用所述共通镀线在所述第一导电图案表面覆盖镀膜的工序；通过切割包含所述共通镀线的所述衬底表面，在所述衬底表面形成槽，将所述各第一导电图案电分离的工序；在所述衬底表面载置半导体元件的工序；形成密封树脂，在所述槽中填充，并密封所述半导体元件的工序；通过在所述各组件的边界切割所述衬底及所述密封树脂，将各个半导体装置分离的工序。
附图说明
图1是本发明半导体装置的平面图(A)、剖面图(B)；
图2是显示本发明半导体装置制造方法的平面图(A)、平面放大图(B)、剖面图(C)；
图3是显示本发明半导体装置制造方法的平面图(A)、剖面图(B)；
图4是显示本发明半导体装置制造方法的剖面图；
图5是显示本发明半导体装置制造方法的剖面图；
图6是显示本发明半导体装置制造方法的剖面图；
图7是说明现有的半导体装置的剖面图。
具体实施方式
首先，参照图1说明本发明的半导体装置10的结构。图1(A)是半导体装置10的平面图，图1(B)是其剖面图。
本发明的半导体装置10具有如下结构，其包括：安装衬底11，其周边部具有台阶部15；第一导电图案12及第二导电图案16，在安装衬底11的表面及背面形成；半导体元件13，其被固定在安装衬底11上，和第一导电图案12电连接；密封树脂，覆盖安装衬底11表面及台阶部15，密封半导体元件13。以下详述这样结构的半导体装置10。
安装衬底11是由玻璃环氧树脂等构成的半导体装置10的衬底(インタポ-ザ)，两面形成导电图案，并在表面安装半导体元件13。在安装衬底11的周边部设置台阶部15。该台阶部的深度为例如安装衬底11厚度的一半左右即可。通过设置该台阶部15，可防止镀线12B露出到外部。另外，由于密封树脂18也被填充在台阶部15，特别是利用台阶部15的侧面和密封树脂18粘附，可提高安装衬底11和密封树脂18的粘附。
参照图1(A)，第一导电图案12通过蚀刻铜等金属形成，并被形成在安装衬底11的表面。在此，第一导电图案12包围半导体元件13形成焊盘12A。另外，还形成自焊盘12A至台阶部15延伸的镀线12B。在利用电镀形成镀膜时，为在导电图案上导通电流使用该镀线12B。设置自各焊盘12A至内侧延伸的配线部，并介由连接部17和形成矩阵状电极的第二导电图案16电连接。另外，在第一导电图案12的表面形成由镍或金构成的镀膜。
第二导电图案16在安装衬底11的背面形成，并形成矩阵状的电极。也可以利用第二导电图案16形成LGA(Land grid array)，还可以在各电极上涂敷焊锡等焊剂形成BGA(Ball grid array)。另外，利用贯通安装衬底的连接部17将各第二导电图案16和第一导电图案12电连接。在第二导电图案16上也覆盖所述镀膜。
半导体元件13为例如IC芯片，其介由绝缘粘接剂被固定在安装衬底15上。这样，通过使用绝缘粘接剂可在半导体元件13的下方形成第一导电图案12。另外，利用金属细线14电连接半导体元件13和第一导电图案12。
密封树脂12由例如热硬化树脂构成，其覆盖半导体元件13。另外，由于密封树脂13也被填充至台阶部15，故可提高安装衬底11和密封树脂18的粘附。由于台阶部15通过切割形成，因此，其表面形成粗糙面，更可提高两者的粘附强度。
其次，参照图2之后说明本发明半导体装置的制造方法。本发明半导体装置的制造方法包括如下工序：在衬底20表面形成第一导电图案12的工序，所述第一导电图案12构成组件21和电连接组件21的镀线12B的共通镀线23，所述组件21由焊盘12A及自焊盘12A向周边部延伸的镀线12B构成；在衬底20背面形成和第一导电图案12电连接的第二导电图案16的工序；通过电镀法使用共通镀线23在第一导电图案12表面覆盖镀膜的工序；通过切割包含共通镀线23的衬底20表面，在衬底20表面形成槽24，将各导电图案电分离的工序；在衬底20表面载置半导体元件13的工序；形成密封树脂18，在槽24中填充，并密封半导体元件13的工序；通过由各组件21的边界切割衬底20及密封树脂18，将各个半导体元件分离的工序。
参照图2，首先，准备形成有导电图案的衬底20。图2(A)是形成有多个组件21的块22的平面图，图2(B)是图2(A)的放大平面图，图2(C)是剖面图。
衬底20是玻璃环氧树脂等树脂的制品，在其表面形成第一导电图案12。而后，在衬底20背面形成利用连接部17和第一导电图案12电连接的第二导电图案16。
参照图1(A)及图1(B)，在衬底20上形成有形成一个半导体装置的导电图案的组件21，并通过矩阵状地排列多个该组件21形成一个块22。下面说明在各组件21上形成的第一导电图案12的结构。包围预定载置的半导体元件13形成由第一导电图案12构成的焊盘12A。然后，自各焊盘12A向组件21的周边部延伸设置镀线23，与共通镀线23连接。而后，为实现BAG或LGA结构，自各焊盘12A向中央方向延伸设置配线部12D。
即，各组件21的焊盘12A利用镀线12B被连接在共通镀线23上。沿各组件21的分界线以格状延伸设置共通镀线23。另外，包围各组件21也延伸设置共通镀线23。从而，各焊盘12A利用镀线21B及共通镀线23电连接。在此，由四个组件21形成一个块，但组件21的个数是任意的。另外，也可以在衬底20上配置多个块22。
参照图2(C)，形成背面电极的第二导电图案16介由连接部17和形成焊盘12A等的第一导电图案12电连接。从而，如上所述，通过由镀线电连接第一导电图案12，第二导电图案16也和镀线23电导通。
其次，利用电镀法由镀膜覆盖第一导电图案12及第二导电图案16的表面。如上所述，利用共通镀线23电连接第一导电图案12及第二导电图案16。从而，可通过在第一导电图案12或第二导电图案16的任意一个上设置一处镀敷用电极进行电镀。在此，形成的镀膜是例如镍或金镀膜。由于这些镀膜利用电镀法形成，故具有非常高的可靠性。
参照图3，利用切割锯25包含共通镀线23切割衬底20的表面。即，沿各组件21的边界进行切割，除去共通镀线23。由此，由第一导电图案12构成的各焊盘被电分离。在各组件21的周边部形成槽24。另外，为可靠地进行共通镀线23的除去，也可以采用比共通镀线23更宽的切割锯。
参照图4，在各组件21上固定半导体元件13。该固定也可以采用绝缘粘接剂进行。而后，利用金属细线14电连接第一导电图案12和半导体元件13。
参照图5，形成填充槽24并覆盖半导体元件13的密封树脂18。密封树脂18的形成可以利用如传递模进行。另外，也可以采用总体密封一个块的树脂密封方法。
参照图6，通过由各组件21的边界切割，将各半导体装置分离。在此，在各组件21的边界形成槽24，并切割该槽24中央部附近的密封树脂18及衬底20。利用所述的工序制造图1所示的半导体装置10。
通过本发明的半导体装置，利用在安装衬底11的周边部设置台阶部15，使台阶部15和密封树脂18紧固地粘附，因此可提高密封树脂18和安装衬底11的粘接强度。还可防止自两者的界面侵入水分等。另外，通过设置台阶部15，可防止自安装衬底11和密封树脂18的边界向外部露出镀线12B。从而，可更加提高半导体装置的可靠性。
通过本发明半导体装置的制造方法，在衬底20上形成多个构成半导体装置的组件21，利用共通镀线电连接各组件21的导电图案，进行镀敷处理。从而，可利用电镀法高效地进行镀膜的形成。

Claims (5)

1、一种半导体装置，其包括：由树脂构成的安装衬底，其周边部具有台阶部；导电图案，其在所述安装衬底的表面形成；半导体元件，其被固定在所述安装衬底上，和所述导电图案电连接；密封树脂，覆盖所述安装衬底表面及所述台阶部，密封所述半导体元件，所述导电图案延伸到所述台阶部。
2、如权利要求1所述的半导体装置，其特征在于，所述导电图案包括：焊盘，其利用金属细线和所述半导体元件电连接；镀线，其自所述焊盘延伸至所述台阶部。
3、如权利要求2所述的半导体装置，其特征在于，所述焊盘包围所述半导体元件配置多个，且具有自所述焊盘向所述半导体元件下方延伸的配线部。
4、一种半导体装置的制造方法，其包括如下工序：在衬底表面形成构成由焊盘及自所述焊盘向周边部延伸的镀线构成的组件和电连接所述组件的所述镀线的共通镀线的第一导电图案的工序；在所述衬底背面形成和所述第一导电图案电连接的第二导电图案的工序；利用电镀法使用所述共通镀线在所述第一导电图案表面覆盖镀膜的工序；通过切割包含所述共通镀线的所述衬底表面，在所述衬底表面形成槽，将所述各第一导电图案电分离的工序；在所述衬底表面载置半导体元件的工序；形成密封树脂，在所述槽中填充，并密封所述半导体元件的工序；通过由所述各组件的边界切割所述衬底及所述密封树脂，将各个半导体装置分离的工序。
5、如权利要求4所述的半导体装置的制造方法，其特征在于，以矩阵状配置所述组件，并将所述共通镀线以格状延伸至所述各组件的分界线。
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