CN110610916B - 封装结构 - Google Patents

封装结构 Download PDF

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Publication number
CN110610916B
CN110610916B CN201810614302.6A CN201810614302A CN110610916B CN 110610916 B CN110610916 B CN 110610916B CN 201810614302 A CN201810614302 A CN 201810614302A CN 110610916 B CN110610916 B CN 110610916B
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Prior art keywords
solder
layer
barrier layer
conductive connection
package structure
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CN201810614302.6A
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CN110610916A (zh
Inventor
石磊
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Tongfu Microelectronics Co Ltd
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Tongfu Microelectronics Co Ltd
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Priority to CN201810614302.6A priority Critical patent/CN110610916B/zh
Priority to US16/235,389 priority patent/US11430706B2/en
Publication of CN110610916A publication Critical patent/CN110610916A/zh
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Abstract

一种封装结构，包括：半导体芯片；导电连接柱，所述导电连接柱具有相对的第一面和第二面，所述导电连接柱的第一面与半导体芯片的表面固定；载板，所述载板与所述半导体芯片相对设置，所述导电连接柱位于半导体芯片和所述载板之间，且第二面朝向载板；位于所述载板表面和所述第二面之间的焊料层；第二阻挡层，所述第二阻挡层位于焊料层周围的载板表面。所述封装结构的性能得到提高。

Description

封装结构
技术领域
本发明涉及封装领域，尤其涉及一种封装结构。
背景技术
倒装芯片工艺既是一种芯片互联技术，又是一种理想的芯片粘结技术。早在50余年前IBM(国际商业机器公司)已研发使用了这项技术。但是直到近几年来，倒装芯片已成为高端器件及高密度封装领域中经常采用的封装形成。目前，倒装芯片封装技术的应用范围日益广泛，封装形式更趋于多样化，对倒装芯片的要求也随之提高。
然而，现有的倒装方法形成的封装结构的性能较差。
发明内容
本发明解决的问题是提供一种封装结构，以提高封装结构的性能。
为解决上述问题，本发明提供一种封装结构，包括：半导体芯片；导电连接柱，所述导电连接柱具有相对的第一面和第二面，所述导电连接柱的第一面与半导体芯片的表面固定；载板，所述载板与所述半导体芯片相对设置，所述导电连接柱位于半导体芯片和所述载板之间，且第二面朝向载板；位于所述载板表面和所述第二面之间的焊料层；第二阻挡层，所述第二阻挡层位于焊料层周围的载板表面。
可选的，所述第二阻挡层的材料为绝缘胶或塑封材料。
可选的，所述第二阻挡层的厚度小于所述焊料层的高度。
可选的，所述第二阻挡层的厚度为10微米～30微米。
可选的，沿载板表面法线方向且自导电连接柱至载板的方向，所述焊料层的宽度逐渐减小。
可选的，还包括：位于所述导电连接柱的侧壁的第一阻挡层，且第一阻挡层未覆盖所述第二面。
可选的，所述第一阻挡层的材料为绝缘胶。
可选的，所述第一阻挡层的材料为金属氧化物；当所述导电连接柱为铜柱时，所述第一阻挡层的材料为氧化铜。
可选的，所述第一阻挡层的厚度为10微米～30微米。
可选的，还包括：塑封层，所述塑封层位于所述载板的表面，且所述塑封层覆盖半导体芯片、导电连接柱、焊料层、第一阻挡层和第二阻挡层。
可选的，所述焊料层包括与第二面接触的焊料顶面；所述焊料顶面的径向尺寸小于等于第一阻挡层和导电连接柱的总径向尺寸。
可选的，所述导电连接柱的数量为若干个，所述焊料层的数量为若干个，一个导电连接柱和所述载板表面之间的焊料层的数量为一个。
可选的，所述焊料层的高度为5微米～30微米。
与现有技术相比，本发明的技术方案具有以下优点：
本发明技术方案提供的封装结构包括第二阻挡层，第二阻挡层用于限制焊料层与载板表面接触的位置，使焊料层的材料沿载板表面延伸的尺寸较小。因此，焊料层与载板表面的接触面积较小，避免焊料层坍塌，满足工艺设计的要求，提高了封装结构的性能。
进一步，所述导电连接柱的数量为若干个，所述焊料层的数量为若干个，一个导电连接柱和所述载板表面之间的焊料层的数量为一个。由于避免焊料层坍塌，因此能够避免相邻的焊料层之间短路。
进一步，所述封装结构还包括位于所述导电连接柱的侧壁的第一阻挡层，且第一阻挡层未覆盖所述第二面。第一阻挡层对导电连接柱有保护作用，避免焊料层的材料与导电连接柱的侧壁表面接触。由于焊料层的位置受到第一阻挡层的限制，因此焊料层中不易形成空洞，焊料层的质量提高。
附图说明
图1至图2是一种倒装方法的结构示意图；
图3至图11是本发明一实施例中封装结构形成过程的结构示意图；
图12至图17是本发明另一实施例中封装结构形成过程的结构示意图。
具体实施方式
正如背景技术所述，现有的倒装芯片工艺形成的封装结构的性能较差。
图1至图2是一种倒装方法的结构示意图。
参考图1，提供半导体芯片100、导电连接柱110和载板130，所述导电连接柱110具有相对的第一面和第二面；将所述导电连接柱110固定在所述半导体芯片100表面，第一面朝向所述半导体芯片100；在导电连接柱110的第二面固定设置焊球140；之后，将半导体芯片100、导电连接柱110和焊球140放置于载板130表面上，焊球140与载板130表面接触。
参考图2，将半导体芯片100、导电连接柱110和焊球140放置于载板130表面上后，进行回流焊，使焊球140形成焊料层141。
在回流焊的过程中，焊球140的材料熔化成液体，在重力的作用下，焊球140的材料容易沿载板130表面水平流动，导致焊料层141坍塌，焊料层141的底部径向尺寸较大，相邻的焊料层141容易短路。
在此基础上，本发明提供一种封装结构，包括：半导体芯片；导电连接柱，所述导电连接柱具有相对的第一面和第二面，所述导电连接柱的第一面与半导体芯片的表面固定；载板，所述载板与所述半导体芯片相对设置，所述导电连接柱位于半导体芯片和所述载板之间，且第二面朝向载板；位于所述载板表面和所述第二面之间的焊料层；第二阻挡层，所述第二阻挡层位于焊料层周围的载板表面。所述封装结构的性能得到提高。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图3至图11是本发明一实施例中封装结构形成过程的结构示意图。
参考图3，提供半导体芯片200和导电连接柱210，所述导电连接柱210具有相对的第一面210a和第二面210b；将所述导电连接柱210固定在所述半导体芯片200表面，第一面210a朝向所述半导体芯片200。
本实施例中，所述导电连接柱210的数量为若干个。在其它实施例中，导电连接柱的数量为一个。
本实施例中，所述第一面210a和第二面210b平行于半导体芯片200表面，所述导电连接柱210的侧壁垂直于半导体芯片200表面。
所述导电连接柱210的材料为金属，如所述导电连接柱210为铜柱。
所述导电连接柱210的作用包括：用于电学连接半导体芯片200和后续的载板300。
参考图6，提供载板300；在所述载板300的表面形成焊料柱320。
本实施例中，所述焊料柱320的数量为若干个。所述焊料柱320的数量和所述导电连接柱210的数量相等。在其它实施例中，所述焊料柱320的数量为一个，所述导电连接柱210的数量为一个。
后续将所述焊料柱320与所述第二面210b接触后，一个焊料柱320仅和一个导电连接柱210连接。
本实施例中，所述载板300以基板(substrate)作为示例，所述基板例如为PCB板或BT板。
在其它实施例中，所述载板为引线框架(lead frame)。
所述焊料柱320的材料为锡、锡银合金、锡银铜合金或锡铅合金。
形成所述焊料柱320的方法包括：参考图4，在所述载板300的表面形成网板310，所述网板310中具有若干通孔，相邻的通孔的中心之间的距离等于相邻的导电连接柱210的中心之间的距离；参考图5，采用印刷工艺在所述通孔中分别形成焊料柱320；参考图6，进行所述印刷工艺后，去除所述网板310。
上述通过印刷工艺形成焊料柱320的好处包括：使得形成的多个焊料柱320的形状和尺寸较为一致，且能够使得多个焊料柱320的间距较小。
在后续回流焊的过程中，焊料柱320熔化，焊料层321的高度较焊料柱320的高度有所降低，焊料层321的径向尺寸容易变大。本实施例中，设计所述焊料柱320的径向尺寸小于所述导电连接柱210的径向尺寸，这样避免焊料层321的径向尺寸过大，减少相邻焊料层321之间连接在一起的风险，且减少了焊料材料的使用，降低了工艺成本。
在一个实施例中，所述焊料柱320的径向尺寸为所述导电连接柱210的径向尺寸的2/5～3/5，如1/2。
参考图7，形成第二阻挡层340，所述第二阻挡层340位于焊料柱320周围的载板300表面。
本实施例中，去除所述网板310后，在焊料柱320周围的载板300表面形成第二阻挡层340。
本实施例中，所述第二阻挡层340的材料为绝缘胶，形成所述焊料柱320后，形成所述第二阻挡层340。
在其它实施例中，所述第二阻挡层的材料为塑封材料；形成所述第二阻挡层的工艺为塑封工艺；在形成所述焊料柱之前，形成所述第二阻挡层。
第二阻挡层340能在回流焊的过程中阻止焊料柱320的材料沿着载板300表面水平流动，避免焊料层321坍塌，避免相邻的焊料层321之间短路。
所述第二阻挡层340的厚度小于所述焊料柱320的高度，避免将焊料柱320的材料在熔化后的流动空间全部封住，焊料柱320熔化过程中的热量能够及时散发至环境中，后续形成焊料层的表面较为光滑，提高了焊料层的质量。
在一个实施例中，所述第二阻挡层340的厚度为10微米～30微米，如10微米、15微米、20微米或30微米。所述第二阻挡层340的厚度选择此范围的意义在于：若第二阻挡层340的厚度大于30微米，导致第二阻挡层340的材料浪费，且第二阻挡层340过厚的话，对焊料柱320熔化过程中的热量散发不利；若第二阻挡层340的厚度小于10微米，导致第二阻挡层340在后续回流焊的过程中对焊料柱320材料的阻挡作用较差。
参考图8，形成第二阻挡层340后，将所述焊料柱320与所述第二面210b接触，所述导电连接柱210位于所述焊料柱320上。
所述导电连接柱210的中心和焊料柱320的中心对准。
所述导电连接柱210位于所述焊料柱320上的作用为：避免在后续回流焊的过程中，焊料柱320熔化的材料在重力的作用下流向半导体芯片200。
参考图9，将所述焊料柱320与所述第二面210b接触后，进行回流焊，且使焊料柱320形成焊料层321。
在一个实施例中，当所述焊料柱320的高度为20微米～100微米时，焊料层321的高度为5微米～30微米。
所述第二阻挡层340的厚度小于所述焊料层321的高度。
本实施例中，沿载板300表面法线方向且自导电连接柱210至载板300的方向，所述焊料层321的宽度逐渐减小。
参考图10，进行所述回流焊后，在所述载板300、半导体芯片200、第二阻挡层340、导电连接柱210和焊料层321上形成塑封层330。
需要说明的是，本实施例中，所述载板300为基板(substrate)，还需要在载板300背向半导体芯片200的表面进行植球，在载板300背向半导体芯片200的表面形成焊球322(参考图10)。
在其它实施例中，在其它实施例中，参考图11，载板301为引线框架(lead frame)，不需要在载板301背向半导体芯片200的表面进行植球。
相应的，本实施例还提供一种采用上述方法形成的封装结构，请参考图9，半导体芯片200；导电连接柱210，所述导电连接柱210具有相对的第一面210a(参考图3)和第二面210b(参考图3)，所述导电连接柱210的第一面210a与半导体芯片200的表面固定；载板300，所述载板300与所述半导体芯片200相对设置，所述导电连接柱210位于半导体芯片200和所述载板300之间，且第二面210b朝向载板300；位于所述载板300表面和所述第二面210b之间的焊料层321；第二阻挡层340，所述第二阻挡层340位于焊料层321周围的载板300表面。
所述第二阻挡层340的材料为绝缘胶或塑封材料。
第二阻挡层340用于限制焊料层321与载板300表面接触的位置，使焊料层321的材料沿载板300表面延伸的尺寸较小。因此，焊料层321与载板表面300的接触面积较小，避免焊料层321坍塌。
所述第二阻挡层340的厚度小于所述焊料层321的高度，避免第二阻挡层340将焊料层321全部封住，形成焊料层321过程中焊料层321中的热量能够及时散发至环境中，焊料层321的表面较为光滑，焊料层321与载板300表面和所述第二面210b的接触面光滑，提高了焊料层321的质量，进而提高了焊料层321与载板300的电学连接性能，提高了焊料层321与第二面210b的电学连接性能。
在一个实施例中，所述第二阻挡层340的厚度为10微米～30微米，如10微米、15微米、20微米或30微米。所述第二阻挡层340的厚度选择此范围的意义在于：若第二阻挡层340的厚度大于30微米，导致第二阻挡层340的材料浪费，且第二阻挡层340过厚的话，对形成焊料层321过程中焊料层321中热量的散发不利；若第二阻挡层340的厚度小于10微米，导致第二阻挡层340限制焊料层321与载板300表面接触的位置的作用较弱。
本实施例中，沿载板300表面法线方向且自导电连接柱210至载板300的方向，所述焊料层321的宽度逐渐减小。
本实施例中，所述导电连接柱210的数量为若干个，所述焊料层321的数量为若干个，一个导电连接柱210和所述载板300表面之间的焊料层321的数量为一个。在其它实施例中，导电连接柱210的数量为一个，焊料层321的数量为一个。
本实施例中，所述焊料层321的高度为5微米～30微米。
本实施例中，所述导电连接柱210的中心和焊料层321的中心对准，即导电连接柱210的中心在载板300表面的投影与焊料层321的中心在载板300表面的投影重合。
本实施例中，所述载板300以基板(substrate)作为示例，所述基板例如为PCB板或BT板。
在其它实施例中，参考图11，所述载板为引线框架(lead frame)。
当所述载板300为基板(substrate)时，所述封装结构还包括：焊球322(参考图10)，所述焊球位于载板300背向半导体芯片200的表面。
所述封装结构还包括：塑封层330(参考图10和图11)，所述塑封层330位于所述载板的表面，且所述塑封层330覆盖半导体芯片200、导电连接柱210、焊料层421和第二阻挡层340。
本发明另一实施例还提供一种封装结构的形成方法，本实施例与前一实施例的区别在于：在将焊料柱与所述第二面接触之前，还包括：在导电连接柱的侧壁形成第一阻挡层，且第一阻挡层暴露出导电连接柱的第二面。关于本实施例与前一实施例相同的内容，不再详述。
图12至图17是本发明另一实施例中封装结构形成过程的结构示意图。
参考图12，图12为在图3基础上的示意图，在所述导电连接柱210的第二面210b和侧壁形成阻挡材料层220。
本实施例中，阻挡材料层220的材料为绝缘胶，形成所述阻挡材料层220的方法为刷胶工艺。
本实施例中，而由于在导电连接柱210的第二面210b和侧壁均形成阻挡材料层220，刷胶工艺无需严格的控制刷胶的位置，因此使得形成阻挡材料层220的工艺难度降低。
在其它实施例中，所述阻挡材料层220的材料为金属氧化物，形成所述阻挡材料层220的工艺为氧化工艺，包括干法氧化或湿法氧化。例如，当导电连接柱210为铜柱时，阻挡材料层220的材料为氧化铜。
参考图13，去除第二面210b的阻挡材料层220，在所述导电连接柱210的侧壁形成第一阻挡层221。
去除第二面210b的阻挡材料层220的方法为打磨工艺。
所述第一阻挡层221的作用包括：在后续回流焊的过程中，阻止焊料柱的材料沿着导电连接柱210的侧壁向上流动。
本实施例中，第一阻挡层221的材料为绝缘胶，第一阻挡层221的材料类型和后续焊料柱的材料类型相差较大，第一阻挡层221能有效的阻止焊料柱的材料在后续回流焊的过程中沿着导电连接柱的侧壁向上流动，有效的避免焊料层的质量降低。且，由于第一阻挡层221的材料类型和后续焊料柱的材料类型相差较大，因此焊料柱的材料也不会沿第一阻挡层221的侧壁向上流动。
在其它实施例中，所述第一阻挡层的材料为金属氧化物。
在一个实施例中，所述第一阻挡层221的厚度为10微米～30微米，如10微米、15微米、20微米或30微米。所述第一阻挡层221的厚度选择此范围的意义在于：若第一阻挡层221的厚度大于30微米，导致工艺浪费，其次，若第一阻挡层221的厚度过大的话，后续相邻导电连接柱210之间的空间过小，在相邻导电连接柱210之间难以填充塑封层；若第一阻挡层221的厚度小于10微米，导致第一阻挡层221阻挡焊料柱的材料沿着导电连接柱210的侧壁向上流动的能力降低。
需要说明的是，在其它实施例中，采用刷胶工艺直接在所述导电连接柱的侧壁形成第一阻挡层，在此情况下，需要严格控制刷胶的位置，避免将第一阻挡层的材料刷在导电连接柱的第二面。
参考图14，形成第一阻挡层221和第二阻挡层340后，将所述焊料柱320与所述第二面210b接触，所述导电连接柱210位于所述焊料柱320上。
所述导电连接柱210的中心和焊料柱320的中心对准。
所述导电连接柱210位于所述焊料柱320上的作用为：避免在后续回流焊的过程中，焊料柱320熔化的材料在重力的作用下流向半导体芯片200。
参考图15，将所述焊料柱320与所述第二面210b接触后，进行回流焊，且使焊料柱320形成焊料层421。
在一个实施例中，当所述焊料柱320的高度为20微米～100微米时，焊料层421的高度为5微米～30微米。
本实施例中，沿载板300表面法线方向且自导电连接柱210至载板300的方向，所述焊料层421的宽度逐渐减小。
本实施例中，所述焊料层421包括与第二面接触的焊料顶面；所述焊料顶面的径向尺寸小于等于第一阻挡层221和导电连接柱210的总径向尺寸。
所述第一阻挡层221和导电连接柱210的总径向尺寸等于导电连接柱210的径向尺寸与2倍的第一阻挡层221的厚度之和。
参考图16，进行所述回流焊后，在所述载板300、半导体芯片200、导电连接柱210和焊料层421上形成塑封层430，且所述塑封层430覆盖所述第一阻挡层221和第二阻挡层340。
需要说明的是，本实施例中，所述载板300为基板(substrate)，还需要在载板300背向半导体芯片200的表面进行植球，在载板300背向半导体芯片200的表面形成焊球422(参考图16)。
在其它实施例中，参考图17，载板301为引线框架(lead frame)，不需要在载板301背向半导体芯片200的表面进行植球。
相应的，本实施例还提供一种采用上述方法形成的封装结构，请参考图15，半导体芯片200；导电连接柱210，所述导电连接柱210具有相对的第一面210a(参考图3)和第二面210b(参考图3)，所述导电连接柱210的第一面210a与半导体芯片200的表面固定；载板300，所述载板300与所述半导体芯片200相对设置，所述导电连接柱210位于半导体芯片200和所述载板300之间，且第二面210b朝向载板300；位于所述导电连接柱210的侧壁的第一阻挡层，且第一阻挡层未覆盖所述第二面；位于所述载板表面和所述第二面之间的焊料层421；第二阻挡层340，所述第二阻挡层340位于焊料层421周围的载板300表面。
所述第一面210a和第二面210b平行于半导体芯片200表面，所述导电连接柱210的侧壁垂直于半导体芯片200表面。
所述导电连接柱210的材料为金属，如所述导电连接柱210为铜柱。
所述导电连接柱210的作用包括：用于电学连接半导体芯片200和后续的载板300。
所述第一阻挡层221的作用包括：第一阻挡层221保护导电连接柱210的侧壁，第一阻挡层221阻挡焊料层421的材料附着在导电连接柱210的侧壁。
本实施例中，所述第一阻挡层221的材料为绝缘胶，第一阻挡层221的材料类型和焊料层421的材料类型相差较大，第一阻挡层221能有效的阻止焊料层421的材料附着在导电连接柱210的侧壁，有效的避免焊料层421的质量降低。且，由于第一阻挡层221的材料类型和焊料层421的材料类型相差较大，因此焊料层421的材料也不容易附着在第一阻挡层221的侧壁。
在其它实施例中，所述第一阻挡层的材料为金属氧化物。
当所述导电连接柱210为铜柱时，所述第一阻挡层221的材料为氧化铜。
本实施例中，所述第一阻挡层221的厚度为10微米～30微米，如10微米、15微米、20微米或30微米。所述第一阻挡层221的厚度选择此范围的意义在于：若第一阻挡层221的厚度大于30微米，导致工艺浪费，其次，若第一阻挡层221的厚度过大的话，相邻导电连接柱210之间的空间过小，在相邻导电连接柱210之间难以填充塑封层；若第一阻挡层221的厚度小于10微米，导致第一阻挡层221对导电连接柱210的侧壁的保护作用较弱。
本实施例中，所述导电连接柱210的数量为若干个，所述焊料层421的数量为若干个，一个导电连接柱210和所述载板300表面之间的焊料层421的数量为一个。在其它实施例中，导电连接柱的数量为一个，焊料层421的数量为一个。
本实施例中，所述焊料层421的高度为5微米～30微米。
本实施例中，所述焊料层421包括与第二面接触的焊料顶面；所述焊料顶面的径向尺寸小于等于第一阻挡层221和导电连接柱210的总径向尺寸。
所述第一阻挡层221和导电连接柱210的总径向尺寸等于导电连接柱210的径向尺寸与2倍的第一阻挡层221的厚度之和。
本实施例中，沿载板300表面法线方向且自导电连接柱210至载板300的方向，所述焊料层421的宽度逐渐减小。
本实施例中，所述载板300以基板(substrate)作为示例，所述基板例如为PCB板或BT板。
在其它实施例中，参考图17，所述载板为引线框架(lead frame)。
当所述载板300为基板(substrate)时，所述封装结构还包括：焊球422(参考图16)，所述焊球422位于载板300背向半导体芯片200的表面。
所述焊料层421的材料为锡、锡银合金、锡银铜合金或锡铅合金。
所述封装结构还包括：塑封层430(参考图16和图17)，所述塑封层430位于所述载板的表面，且所述塑封层430覆盖半导体芯片200、导电连接柱210、焊料层421和第一阻挡层221和第二阻挡层340。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (12)

1.一种封装结构，其特征在于，包括：
半导体芯片；
导电连接柱，所述导电连接柱具有相对的第一面和第二面，所述导电连接柱的第一面与半导体芯片的表面固定；
载板，所述载板与所述半导体芯片相对设置，所述导电连接柱位于半导体芯片和所述载板之间，且第二面朝向载板；
位于所述载板表面和所述第二面之间的焊料层，沿载板表面法线方向且自导电连接柱至载板的方向，所述焊料层的宽度逐渐减小；
第二阻挡层，所述第二阻挡层位于焊料层周围的载板表面，且与所述焊料层接触；
所述焊料层由位于所述载板表面的焊料柱与所述导电连接柱第二面接触后经回流焊而形成，且所述焊料柱的径向尺寸小于所述导电连接柱的径向尺寸，在所述回流焊之前，所述第二阻挡层位于所述焊料柱周围的载板表面且与所述焊料柱接触。
2.根据权利要求1所述的封装结构，其特征在于，所述第二阻挡层的材料为绝缘胶或塑封材料。
3.根据权利要求1所述的封装结构，其特征在于，所述第二阻挡层的厚度小于所述焊料层的高度。
4.根据权利要求1所述的封装结构，其特征在于，所述第二阻挡层的厚度为10微米~30微米。
5.根据权利要求1所述的封装结构，其特征在于，还包括：位于所述导电连接柱的侧壁的第一阻挡层，且第一阻挡层未覆盖所述第二面。
6.根据权利要求5所述的封装结构，其特征在于，所述第一阻挡层的材料为绝缘胶。
7.根据权利要求5所述的封装结构，其特征在于，所述第一阻挡层的材料为金属氧化物；当所述导电连接柱为铜柱时，所述第一阻挡层的材料为氧化铜。
8.根据权利要求5所述的封装结构，其特征在于，所述第一阻挡层的厚度为10微米~30微米。
9.根据权利要求5所述的封装结构，其特征在于，还包括：塑封层，所述塑封层位于所述载板的表面，且所述塑封层覆盖半导体芯片、导电连接柱、焊料层、第一阻挡层和第二阻挡层。
10.根据权利要求5所述的封装结构，其特征在于，所述焊料层包括与第二面接触的焊料顶面；所述焊料顶面的径向尺寸小于等于第一阻挡层和导电连接柱的总径向尺寸。
11.根据权利要求1所述的封装结构，其特征在于，所述导电连接柱的数量为若干个，所述焊料层的数量为若干个，一个导电连接柱和所述载板表面之间的焊料层的数量为一个。
12.根据权利要求1所述的封装结构，其特征在于，所述焊料层的高度为5微米~30微米。
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