JP4660643B2 - プリ半田構造を形成するための半導体パッケージ基板及びプリ半田構造が形成された半導体パッケージ基板、並びにこれらの製法 - Google Patents
プリ半田構造を形成するための半導体パッケージ基板及びプリ半田構造が形成された半導体パッケージ基板、並びにこれらの製法 Download PDFInfo
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- JP4660643B2 JP4660643B2 JP2004281751A JP2004281751A JP4660643B2 JP 4660643 B2 JP4660643 B2 JP 4660643B2 JP 2004281751 A JP2004281751 A JP 2004281751A JP 2004281751 A JP2004281751 A JP 2004281751A JP 4660643 B2 JP4660643 B2 JP 4660643B2
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- H01L2924/1025—Semiconducting materials
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- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
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- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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Description
取り入れている。ワイヤボンディング(wire bond)技術が半導体チップと基板との電気
接続を一般のボンディングワイヤで行うのに対し、このフリップチップ技術は半田バンプによって行うことを特徴としている。したがって、フリップチップ技術では、パッケージ密度を向上させて、パッケージ素子のサイズを低減できることが利点であるとともに、長い金属ワイヤを必要としないため、電気機能が向上する。このことに鑑みて、業界では複数にわたってセラミックス基板上に高温半田、即ちC4テクノロジ(Controlled Collapse Chip Connection technology)が使用されている。
熱膨張の差異によって生じる熱応力を減少させることは、すでに広く行われている。
ンプ・ソルダージョイント(Solder bump joint)は、さらに、チップ13と配線板16との
隙間にアンダーフィル剤材料18を充填することで、チップ13と配線板16との熱膨張差を抑制し、ソルダージョイント17の応力を低減させることが可能である。
。有機配線板2の絶縁層22は、有機材料、繊維混合された有機材料または顆粒混合された
有機材料など(例えばエポキシ樹脂、ポリイミド(Polyimide)、ビスメリイミド トリアジン(Bismeleimide triazine)、シアネート エステル(Cyanate ester)、ポリベンゾ
シクロブテン(Polybenzocyclobutene)またはそのガラス繊維(Glass fiber)である複
合材料等)からなる。電気接続パッド21は、一般的に金属材料(例えば銅)からなる。金属バリア層23は、電気接続パッド21に形成されたニッケル接着層、及びニッケル接着層に
形成された金保護層を備える。この金属バリア層23は、金、ニッケル、パラジウム、銀、スズ、ニッケル/パラジウム、クロム/チタン、パラジウム/金またはニッケル/パラジウム/金などからなり、電気メッキ(Electroplateing)、無電解メッキ(Electroless plating)または物理気相成長法(Physical vapor deposition)等の方法によって形成さ
れる。この後、配線板2の表面上に形成された配線層の保護やそれに絶縁性を付与するた
めに、該配線板2の表面上に有機絶縁保護層24、例えばソルダーレジスト(solder resist)が塗布されている。
上面にはフリップチップソルダージョイントが形成されるようにプリ半田バンプ25が形成されている。現在、業界においては、主に孔版印刷技術によって該電気接続パッド21表面に半田が沈積されプリ半田バンプが形成されている。中でも、該孔版印刷の技術で広く用いられている孔版版材は鋼板である。
ッド32が形成されている。該基板の表面には該電気接続パッド32に接続されるための複数の導電回路31が同時に形成されていてもよい。パッケージ基板3に導電回路31と電気接続
パッド32とを形成するため技術は極めて数が多く、かつ業界に周知された工程技術であり、本願の目的とする技術特徴ではないため、ここでは詳しい説明を省略する。
、スピンコーティング(spin coating)及び貼合のいずれかを利用して該有機絶縁保護層33が形成されている。該有機絶縁保護層33はソルダーマスク層であり、例えば緑ペイントであってよい。
貼合のいずれかによって絶縁膜を形成し、露光、現像等のパターニング工程によって絶縁膜34で導電回路31表面を被覆し、電気接続パッド32の上表面のみがパッケージ基板3の表
面に露出される。前記絶縁膜34としては、有機または無機の耐酸化膜を用いることができる。パッケージ基板3の最外層表面に導電回路31が形成されていない場合、絶縁膜34を形
成して被覆する必要がない(図3D'に示す)。また、導電回路31は絶縁膜34の形成によっ
て被覆(図3D"に示す)することなく、その後の電気メッキによるプリ半田工程において
直接レジスト層によって被覆を行ってもよい。
。導電膜35は、主に後述のようにプリ半田の電気メッキに必要な電流伝導ルートであって、金属、合金または複数の層が積層された金属層からなり、例えば銅、スズ、ニッケル、クロム、チタン、銅クロム合金またはスズ鉛合金等の組合せのいずれかからなる。物理気相成長法(PVD)、化学気相成長法(CVD)、無電解メッキまたは化学積層等の方式、例えばスパッタリング(sputtering)、蒸着(evaporation)、アーク気相成膜(arc vapor deposition)、イオンビームスパッタリング(ion beam sputtering)、レーザーアブレーション成膜(laser ablation deposition)、またはプラズマ促進の化学気相成長法(CVD)等の方法によって該配線板の表面に形成される。
板3の表面に導電回路31が形成されていない場合、該基板表面が絶縁膜で被覆されず基板
表面に直接導電膜35が形成されている状態を示す。図3E"は、表面に電気接続パッド32と
導電回路31とを有するパッケージ基板を直接導電膜35によって被覆し、該導電回路31の表面に絶縁膜34が被覆されていない状態を示す。
し導電回路に絶縁膜が形成されていない場合(図3E"に示す)においては、その工程はほ
ぼ同様であるが、主な差異は基板表面の導電回路に絶縁膜34が形成されていることにある。
ニング形成することにより、レジスト層36に複数の開孔360が形成され、電気接続パッド32の表面の導電膜35が露出される。レジスト層36は、ドライフィルムまたは液体フォトレ
ジスト等からなるフォトレジスト層(photoresist)であってよく、印刷、スピンコーテ
ィング(spin coating)または貼合のいずれかによってパッケージ基板3の表面に形成さ
れ、露光、現像等によってパターニングされ、またはレーザ技術によって開孔360が形成
される。
ッキを行う際に、導電膜35の有する導電特性によって、電流伝導ルートであるレジスト層の開孔360における電気接続パッド32上に、電気メッキによりプリ半田構造が形成される
。このように電気メッキすることで、従来の孔版印刷(Stencil printing)技術における問題、すなわち電気接続パッドのサイズやピッチが縮小される場合、該孔版の開孔も縮小させなければならず、該孔版の型開けが困難となり、製造コストが増加するとともに、該孔版の開孔のピッチの細微によってプリ半田材料が通過できず、孔版のクリーニングによる工程の煩雑さなどの様々な問題が改善されることとなり、回路と電気接続パッドとの微小なピッチを有するパッケージ基板に適用することが可能となる。プリ半田材料は、鉛、スズ、銀、銅、ビスマス、アンチモン、亜鉛、ニッケル、ジルコニウム、マグネシウム、インジウム、テルル及びガリウム等の元素の混合物からなる合金のいずれかを用いることができる。
分な温度条件下で、リフロー(reflow)工程を行うことで、電気接続パッド32上にプリ半田バンプ38が形成され、本発明に係るプリ半田構造が形成された半導体パッケージ基板が完成する。その後、半導体チップの金属バンプに接合され、ソルダージョイントが形成される。
ッド32が形成されている。該基板の表面には該電気接続パッド32に接続されるための複数の導電回路31が同時に形成されてもよい。
スピンコーティング(spin coating)及び貼合のいずれかを利用して該有機絶縁保護層33
が形成されている。有機絶縁保護層33はソルダーマスク層であり、例えば緑ペイントであってよい。
の耐酸化膜を用いることができる。露光、現像等のパターニング工程によって絶縁膜34により導電回路31表面が被覆され、電気接続パッド32の上表面がパッケージ基板3の表面に
露出される。パッケージ基板3の最外層表面に導電回路31が形成されていない場合、絶縁
膜34を形成して被覆する必要がない(図4D'に示す)。該導電回路31には絶縁膜34の形成
によって被覆(図4D"に示す)を行うこともない。本実施例の図面においては、基板表面
に導電回路31と電気接続パッド32が形成され、導電回路31に絶縁膜34が形成されることを説明する。
気接続パッド32に半田材料が沈積され、該沈積された半田材料が溶融するに十分な温度条件下で、リフロー(reflow)工程を行い、リフローによって電気接続パッド32上に半田バンプ38を形成し、本発明に係るプリ半田構造が形成された半導体パッケージ基板が完成する。絶縁膜34の膜厚はわずか2〜5ミクロンであり、電気接続パッド32の周囲に被覆されないのみならず、絶縁膜34の膜厚が薄いため、基板3の表面に孔版印刷によって電気接続パ
ッド32上に半田材料を沈積する実施可能性が影響を受けることはなく、位置合わせの問題が低減する。当然のように、基板の表面に絶縁膜34が形成されていなければ、それらの問題が生じないのは言うまでもなく、広い接触面積を有する電気接続パッド32上にプリ半田バンプ38が形成されるように孔版印刷技術に有効的に提供される。さらに、前記孔版印刷技術によく見られる孔版版材は鋼板である。
柱37の位置に対応し、半導体チップ41がパッケージ基板3に電気的に接続されるように設
置される。
半導体チップに接合することが可能である。図6Aに示すように、半導体チップ51には複数の電極パッド52が半導体チップ51の作用表面に形成され、電極パッド52は複数の金属バンプ53を有する。半導体チップ51は、金属バンプ53がそれぞれパッケージ基板3のプリ半田
バンプ38の位置に対応することによって、パッケージ基板3に電気的に接続されるように
設置される。そして、図6Bに示すように、プリ半田バンプ38が金属バンプ53にリフローされることによって、半導体チップ51とパッケージ基板3との間にフリップチップソルダー
ジョイント54が形成される。半導体チップ51における金属バンプ53は、金属、合金または複数の金属が積層されたものからなり、例えば半田パンプ、金バンプ、銅バンプまたはソルダーキャップ(Solder Caps)によって被覆された銅柱等である。金属バンプ53は任意
の形状であってよく、例えば釘柱状バンプ、球形バンプ、柱状バンプまたはその他の形状のバンプである。
ルダージョイント及び配線板と基板との間に板対板のソルダージョイントを同時に形成するように応用することが可能である。図7Aに示すように、配線板6において適当な位置に
チップ62が設置される。配線板6としては、有機またはセラミックス配線板を用いること
もできる。配線板6において、チップ62の周辺に複数の電気接続パッド61が形成される。
複数の金属バンプ64、65は、それぞれ配線板6の電気接続パッド61表面、及びチップ62の
電極パッド63表面に形成される。そして、配線板6を、その金属バンプ64、65がパッケー
ジ基板3に形成されたプリ半田バンプ38に向くようにすることによって、パッケージ基板3に接合される。図7Bに示すように、金属バンプ64、65がそれぞれ対応したプリ半田バンプ38にリフローすることによって、チップ62とパッケージ基板3との間にフリップチップリ
フロージョイント66が形成され、配線板6とパッケージ基板3との間に板対板のソルダリングジョイント67が形成される。
装70を形成する半導体パッケージ基板として用いられる。図8に示すように、基板はその
第一、第二表面に、複数の電気接続パッドがそれぞれ形成され、前記の方法によって、該基板の第一表面の電気接続パッドに複数のプリ半田バンプ38が形成され、該基板の第二表面の電気接続パッドに複数の半田ボール39が形成され、半導体チップ71を、フリップチップ方式によってパッケージ基板3に設置する。このフリップチップの設置方式は、チップ71に形成された電極パッド72における金属バンプ73がパッケージ基板3に形成されたプリ半田バンプ38に半田付けされ、アンダーフィル剤74がチップ71とパッケージ基板3との間の
隙間に充填されることで、フリップチップ実装70が形成される。
3 パッケージ基板
11、53、64、65、73 金属バンプ
12、42、52、63、72 電極パッド
13、41、51、62、71 半導体チップ
14、25、38 プリ半田バンプ
15、21、61 電気接続パッド
17、54、66、67 ソルダージョイント
18、74 アンダーフィル剤
22 絶縁層
23 金属バリア層
24 絶縁保護層
26 隙間
31 導電回路
32 電気接続パッド
33 有機絶縁保護層
34 絶縁膜
35 導電膜
36 レジスト層
37 導電柱
39 半田ボール
70 フリップチップ実装
360 開孔
Claims (4)
- プリ半田構造が形成された半導体パッケージ基板の製法であって、
少なくとも表面に電気接続パッド及び導電回路が複数形成されたパッケージ基板を準備するステップ(A)と、
前記パッケージ基板の表面に有機絶縁保護層を形成し、前記有機絶縁保護層、前記電気接続パッド及び前記導電回路の上表面の高さが同じになるように前記有機絶縁保護層の膜厚を薄くすることによって、前記有機絶縁保護層の表面に前記電気接続パッド及び前記導電回路の上表面を露出させるステップ(B)と、
前記パッケージ基板の表面に、印刷、スピンコーティング(spin coating)及び貼合のいずれかによって絶縁膜を被覆し、次いでパターニング工程によって、前記絶縁膜が前記導電回路を被覆して前記電気接続パッドの上表面及びその周縁の前記有機絶縁保護層の部分的な表面を露出させるステップ(C)と、
前記パッケージ基板の表面に、順に導電膜とレジスト層を形成し、次いで前記レジスト層に複数の開孔を形成して前記電気接続パッド表面の導電膜を完全に露出させるステップ(D)と、
電気メッキを行い、前記電気接続パッドの上方の前記導電膜の上にプリ半田材料を沈積するステップ(E)と、
プリ半田材料を前記電気接続パッドの上方の前記導電膜の露出表面に電気メッキした後、前記レジスト層及びその被覆された導電膜を除去するステップ(F)と、
を順次実施することを特徴とする、プリ半田構造が形成された半導体パッケージ基板の製法。 - ステップ(E)において、前記電気メッキによりプリ半田材料を沈積させて導電柱を形成することを特徴とする請求項1に記載のプリ半田構造が形成された半導体パッケージ基板の製法。
- ステップ(F)の後に、さらに、前記電気メッキにより沈積されたプリ半田材料を、リフロー(Reflow)工程によってプリ半田バンプを形成することを特徴とする請求項1に記載のプリ半田構造が形成された半導体パッケージ基板の製法。
- プリ半田構造を形成するための半導体パッケージ基板において、
少なくとも表面に電気接続パッド及び導電回路が複数形成されたパッケージ基板と、
前記パッケージ基板の表面に形成され、前記電気接続パッドの周縁と緊密に接合するとともに、前記電気接続パッド及び前記導電回路の上表面の高さと同じになるように前記電気接続パッド及び前記導電回路の上表面が完全に露出している有機絶縁保護層と、
前記電気接続パッドの上表面及びその周縁の前記有機絶縁保護層の部分的な表面を露出させるように前記導電回路を被覆する絶縁膜と、
前記複数の電気接続パッドの上表面の全体に形成される導電膜と、
電気メッキによって前記電気接続パッドの上方の前記導電膜の上表面に形成されるプリ半田バンプと、
を備えることを特徴とする、プリ半田構造を形成するための半導体パッケージ基板。
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TW92126792A TWI251919B (en) | 2003-09-29 | 2003-09-29 | Semiconductor package substrate for forming presolder material thereon and method for fabricating the same |
TW92126790A TWI238507B (en) | 2003-09-29 | 2003-09-29 | Integrated circuit package substrate with presolder structure and method for fabricating the same |
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