TWI534971B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI534971B
TWI534971B TW102111094A TW102111094A TWI534971B TW I534971 B TWI534971 B TW I534971B TW 102111094 A TW102111094 A TW 102111094A TW 102111094 A TW102111094 A TW 102111094A TW I534971 B TWI534971 B TW I534971B
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Taiwan
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pad
width
region
semiconductor die
conductive
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TW102111094A
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TW201344867A (zh
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陳憲偉
陳英儒
于宗源
陳玉芬
王宗鼎
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台灣積體電路製造股份有限公司
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Description

半導體裝置及其製造方法
本發明係有關一種半導體裝置，且特別是有關一種可降低積體電路封裝的應變之半導體裝置。
積體電路(integrated circuit,IC)的封裝係其製造過程中，有助於總成本、效能與可靠度的一個步驟。隨著半導體裝置的整合達到更高的水平，IC晶片的封裝被視為生產成本的一大花費，而封裝的失敗導致良率下降而付出昂貴代價。
若干個封裝技術可用。例如，打線接合(wire bonding)技術利用將晶片朝上並接合線至晶片上的每一接墊。在覆晶(flip chip)技術中，一個覆晶微電子組件，包括朝下的(即是，翻覆(flipped))晶片直接電性連接至一基板上，例如，印刷電路板(printed circuit board,PCB)或使用此晶片之導電墊的載板。
覆晶通常係藉由在矽晶片上置放焊球而製成。焊球的破裂通常係因封裝組件中，材料之間的熱膨脹係數(coefficient of thermal expansion,CTE)差所造成的應變而產生的。例如，晶片的矽基板通常具有高於約3ppm/℃的熱膨脹係數，晶片的低介電常數材料通常具有高於約19ppm/℃的熱膨脹係數，而封裝基板通常具有高於約16ppm/℃的熱膨脹係數。當熱改變發生時，熱膨脹係數差對結構產生應變。
一種磁電阻式隨機存取記憶體裝置之製造方法，磁電阻式隨機存取記憶體裝置具有多個磁性穿隧接點單位，且該製造方法包括：形成一底導電層；形成一反鐵磁層；形成一穿隧層於底導電層與反鐵磁層上方；形成一磁性自由層於穿隧層上，磁性自由層具有對齊於一方向的磁距，且方向可藉由施加外部電磁力來調整；形成一頂導電層於磁性自由層上；進行至少一微影製程，以移除未被一光阻層遮蓋的底導電層、反鐵磁層、穿隧層、磁性自由層及該頂導電層，直到露出底導電層；以及移除至少一部份的磁性穿隧接點單位之側壁。
一種磁電阻式隨機存取記憶體裝置，隨機存取記憶體裝置包含一磁性穿隧接點單位，且該磁性穿隧接點單位包括：一底導電層；一反鐵磁層；一穿隧層，位於底導電層與該反鐵磁層上；一磁性自由層，位於穿隧層上；以及一頂導電層，位於磁性自由層上，其中頂導電層之直徑大於介於頂導電層與底導電層之間的膜層之直徑。
158、200‧‧‧基板
160‧‧‧電子電路
162、168‧‧‧層間介電層
164‧‧‧插塞
166‧‧‧底金屬層
170‧‧‧頂插塞
172‧‧‧頂金屬層
174‧‧‧鈍化保護層
176‧‧‧開口
178、182‧‧‧聚合物層
180‧‧‧重分佈層
184‧‧‧頂部導電墊
186‧‧‧導電材料
188‧‧‧底部導電墊
184a、184b‧‧‧頂導電墊
140‧‧‧中心點
r1、r2‧‧‧半徑
202a、202b‧‧‧接合墊
第1a~1c圖係根據本發明不同實施例所繪示的半導體晶粒結構之剖面示意圖。
第1d~1h圖繪示出第1a~1c圖中的半導體晶粒結構之半導體區域的上視圖。
第2圖係根據本發明不同實施例所繪示的基板結構之剖面示意圖。
第3圖係根據本發明不同實施例所繪示的帶有基板的半導體晶粒之一部份的剖面示意圖。
第4圖係本發明不同實施例中封裝半導體晶粒與基板的方法流程圖。
覆晶通常係由在矽晶片上置放焊球而製成。焊球係置放於半導體晶粒或封裝用基板的陣列中。也可使用焊球以外的導電材料，導電材料包括微凸塊(micro bumps)、銅柱(pillar)、金屬柱、金柱釘(stud)、銅柱釘、及上述之組合。已發現在不同位置的導電材料會遭受到不同量與型態的應變。例如，位於半導體晶粒外圍區域的導電材料在熱循環過程中遭受比位於晶粒中心的材料較高的應變。本發明不同實施例藉由改變半導體晶粒與封裝基板之間的界面(interface)或結合(bond)而抵銷了上述額外的應變。具體來說，在裝置的不同區域中，改變半導體晶粒上的結合寬度與基板上的結合寬度的比例。
第1a圖繪示出對應到本發明不同實施例的半導體晶粒結構之剖面圖。請參照第1a圖，半導體晶粒100包括基板158。某些實施例中，半導體晶粒100為矩形或正方形。基板158可為矽基板。某些實施例中，基板158可為矽基覆絕緣體(silicon-on-insulator)、碳化矽、III-V族材料或藍寶石。基板158可更包括多種電子電路160。形成於基板158上的電子電路160可為適合特定應用的任何類型的電路。某些特定實施例中，電子電路160可包括使用高介電常數材料製作的各式n型金屬氧化物半導體(NMOS)及/或p型金屬氧化物半導體(PMOS)裝置， 或使用複合閘電晶體設計(例如鰭狀場效電晶體(finFET))，高介電常數材料可包括矽酸鉿、矽酸鋯、二氧化鉿及二氧化鋯。電子電路160也可包括不同的n型金屬氧化物半導體及/或p型金屬氧化物半導體，例如電晶體，電容器，電阻器，二極體、光二極體(photo-diodes)、熔絲(fuses)及上述之相似物。可內連接電子電路160以呈現一或多種包括記憶結構、處理結構、感測器、放大器、電力分佈、輸入/輸出電路或上述之相似的功能。
在電子電路160上形成層間介電層162。層間介電層162可為低介電常數材料(例如，摻雜氟的氧化矽，其介電常數為3.5~3.9)所形成。另一些實施例中，低介電常數材料為氫矽鹽酸類(hydrogen silsesquioxane,HSQ)或甲基矽鹽酸類(methylsilsesquioxane,MSQ)，其介電常數約為3.0。一些實施例中，低介電常數材料為摻雜碳的氧化矽，其具有介電常數約為3.0。其他實施例中，低介電常數材料為多孔性摻雜碳的氧化矽，其介電常數約為2.5。又一些實施例中，低介電常數材料為市售SiLKTM商標下的介電材料或多孔介電材料，其介電常數低於約2.6。另一些實施例中，低介電常數材料也可為多孔氧化矽，其介電常數低於約2.0。
請參照第1a圖，插塞164形成於層間介電層162中並連接至電子電路160，插塞164為金屬所形成，其可為鈦、氮化鈦、鎢、鋁、鉭、鋁或上述之組合。插塞164連接至底金屬層166，底金屬層166為鋁、鉭、鈦、氮化鈦、鎢或上述之組合所形成並設置於層間介電層162。在底金屬層166上配置另一個 層間介電層168，其係由相似於上述層間介電層162的低介電常數材料所形成。在層間介電層168中配置頂塞插170，且其電性連接至底金屬層166。頂插塞170係由金屬所形成，其可為鎢、銅、氮化鈦、鉭、鋁、或上述之合金。頂插塞170連接至頂金屬層172，頂金屬層172係由鋁、銅、鈦、氮化鈦、鎢、或上述之合金所組成。儘管第1a圖僅顯示底金屬層166及頂金屬層172，此技藝人士將理解可在底金屬層166與頂金屬層172之間形成一或多個層間介電層(未顯示)、以及相關的插塞與金屬層(未顯示)。
在頂金屬層172上形成鈍化保護(passivation)層174。一些實施例中，鈍化保護層174係由無機材料所形成，例如未摻雜的矽酸鹽玻璃、氮化矽、氧化矽、氮氧化矽、摻雜硼的氧化矽、摻雜磷的氧化矽及上述之相似物。形成開口176，以提供外部電性連接。可由微影及蝕刻形成開口176。在鈍化保護層174上形成聚合物層178。聚合物層178係由如環氧樹脂(epoxy)、聚亞醯胺樹脂(polyimide)等聚合物所形成。可由任何合適的習知方法製作聚合物層178，例如旋轉塗佈。在聚合物層178上形成重分佈層180。可由金屬製造重分佈層180，例如鈦、氮化鈦、鋁、鉭、銅及上述之組合物。可由任何合適的習知方法製作重分佈層180，例如濺鍍、化學氣相沈積或電鍍。重分佈層180在頂金屬層172與半導體晶粒100的上表面之間提供傳導路徑。在重分佈層180與聚合物層178上形成另一層聚合物層182。聚合物層182係由如環氧樹脂(epoxy)、聚亞醯胺樹脂(polyimide)等聚合物所形成。可由任何合適的習知方法製作聚 合物層182，例如旋轉塗佈或積層(lamination)法。聚合物層182經圖案化，以形成多個開口。暴露出重分佈層180之底部導電墊188。在聚合物層182上形成頂部導電墊184，且其電性連接至底部導電墊188。進行無電解(electro-less,E-less)電鍍以形成頂部導電墊184。頂部導電墊184可具有單層結構或複合結構，複合結構包括不同材料形成的多個次層(sub-layer)，且可包括(多個)擇自鈦、鎳層、鈀層、金層、及上述之組合。形成方法可包括浸鍍。一些實施例中，頂部導電墊184係由無電鍍鎳鈀化金(Electro-less Nickel Electro-less Palladium Immersion Gold,ENEPIG)所形成，其包括鎳層、鎳層上的鈀層、鈀層上的金層。可使用浸鍍形成金層。在其他實施例中，頂部導電墊184可由其他材料及方法所形成，包括，但不限於，無電鍍鎳化金(Electro-less Nickel Immersion Gold,ENIG)、無電鍍鎳鈀(Electro-less Nickel Electro-less Palladium,ENEP)、直接浸金(direct immersion gold,DIG)等。請參照第1a圖，在導電墊184上形成導電材料186。導電材料係由焊球、焊料(solder)、微凸塊、銅柱、金屬柱、金柱釘、銅柱釘、及上述之組合物。一些實施例中，可由常用的方法形成焊球，如球轉移(ball transfer)或植球(ball placement)。其他實施例中，導電材料186係由微凸塊所製作，例如銅、錫、鎳、鈦、鉭、焊料、上述之組合且可以微影和電鍍(electroplating)或鍍(plating)形成微凸塊。在其他實施例中，導電材料186係由金屬柱所製作，例如鈦、錫、焊料、銅、鈀、鎳、上述之組合，且金屬柱可使用微影和電鍍(electroplating)或鍍(plating)所形成。第1b圖顯示另一個實施 例。第1b圖中，省去了第1a圖的頂部導電墊184。導電材料186直接與導電墊188之底部接觸。第1c圖顯示在同一半導體晶粒上的兩種不同的頂部導電墊與導電材料之組合，其具有不同的尺寸。請參照第1c圖，在半導體晶粒100之區域A1中，頂導電墊184a具有寬度W1a，而在半導體晶粒100之區域A2中，頂導電墊184b具有寬度W1b。寬度W1a不同於寬度W1b，且差距可介於約4%~35%之間。區域A1與區域A2中，相鄰的導電材料可具有相同或不同的寬度W1a與W1b。某些實施例中，導電材料包括焊球，焊球包括約94%~97%的錫、約3%~5%的銀、及約0.5%~2%的銅。焊球的大小約為200um~300um。相鄰的球可具有相同或不同的球體大小。焊球之間距約為400um~600um。寬度W1a與寬度W1b約為100um~300um。其他實施例中，導電材料包括金屬柱，其包括鈦、錫、焊料、銅、鉭、鎳、或上述之組合。金屬柱的大小，例如銅柱，約為20um~100um，而銅柱之間距約為40um~200um。寬度W1a與寬度W1b約為20um~100um。又在其他實施例中，導電材料包括微凸塊，其包括銅、錫、鎳、鈦、鉭、焊料、上述之組合。微凸塊之大小約為20um~40um。微凸塊之間距約為40um~80um。寬度W1a與寬度W1b約為20um~40um。
第1d圖顯示半導體晶粒上的頂部導電材料之佈置圖。請參照第1d圖，區域D1為內部區域而區域D2為外部區域。半導體晶粒具有側邊d1與d2。寬度d3、d4、d5、以及d6為區域D2之寬度。某些實施例中，d3相等於d5而d4相等於d6。特定的實施例中，d3、d4、d5、以及d6皆不同。又一些實施例中，d3、 d4、d5、以及d6各自約小於d1與d2對應長度的20%。區域D2中的頂部導電材料(凸塊、柱或球)之數量可少於半導體晶粒中的頂部導電材料之總數量的30%。
第1e圖顯示另一個半導體晶粒上的頂部導電材料之佈置圖。請參照第1e圖，半導體晶粒具有側邊e1與e2。區域E1為內部區域而區域E2為外部區域。區域E2包括半導體晶粒之四個角。外部區域E2各自具有寬度e3與e4，其約等於或小於e1與e2對應長度的20%。一些實施例中，四個外部區域E2包括不同的面積，且甚至可具有不同的形狀。例如，外部區域E2甚至可具有不同的寬度e3與e4。其他實施例中，一個外部區域E2中的頂部導電材料之數量約少於半導體晶粒中的頂部導電材料之總數量的10%。又在其他實施例中，所有外部區域E2中的頂部導電材料之總數量約少於半導體晶粒中的頂部導電材料之總數量的30%。
第1f圖顯示又一個半導體晶粒上的頂部導電材料之佈置圖。請參照第1f圖，區域F1為內部區域而區域F2為外部區域。最大半徑r2坐落於半導體晶粒之中心點140至半導體晶粒之最外圍的頂部導電材料處。半徑r1坐落於半導體晶粒之中心點至一預定導電材料處，其可位於小於半導體晶粒之中心點140至r2之任何距離處。區域F2位於具有半徑r2的圓與具有半徑r1的圓之間。一些實施例中，r1約等於或小於r2的2/3。一些實施例中，區域F2中的頂部導電材料之數量約少於半導體晶粒中的頂部導電材料之總數量的30%。而具有半徑r1的圓所產生的邊界切過一些頂部導電材料，這樣的頂部導電材料係屬於區 域F1與F2任一方且不被劃分。一些實施例中，在r1邊界上的所有頂部導電材料被視為區域F1之一部份。其他實施例中，在r1邊界上的頂部導電材料係屬於區域F2。
第1g圖顯示又一個半導體晶粒上的頂部導電材料之佈置圖。請參照第1g圖，半導體晶粒具有側邊g1與g2。區域G1為內部區域而區域G2為外部區域。區域G2包括四個L型的角。角各自具有寬度g3與g4，其約等於或小於g1與g2對應長度的20%。一些實施例中，在每一角中，g3與g4具有不同的長度。其他實施例中，區域G2中的頂部導電材料之數量約少於半導體晶粒中的頂部導電材料之總數量的30%。又在其他實施例中，一個角中的頂部導電材料之總數量少於半導體晶粒中的頂部導電材料之總數量的約10%。
第1h圖顯示又一個半導體晶粒上的頂部導電材料之佈置圖。請參照第1h圖，隔離的導電材料(196、197、198、或199)設置於低密度的導電材料隔離區域內。換句話說，導電材料隔離區域中的間距大於導電材料密集區域中的間距。某些實施例中，隔離的導電材料係那些“缺少”鄰近導電材料的導電材料。換句話說，若使用最高密度區域的間距而將整個導電材料陣列佈滿，將在鄰近且環繞著隔離的導電材料的空缺區內填入額外所缺少的一或多個鄰近導電材料。每一個隔離的導電材料196在整個四側“缺少”鄰近導電材料。一些實施例中，隔離的導電材料196與197也被定義為隔離區域的一部分，因為他們“缺少”三個或更多的鄰近導電材料。另一些實施例中，缺少”一或兩個鄰近導電材料的其他導電材料，例如導電 材料198(“缺少”兩個鄰近導電材料)或導電材料199(“缺少”一個鄰近導電材料)，被視為隔離的區域的一部分。
第2圖係對應到不同實施例的基板結構之剖面圖。第2圖的基板結構可連同第1a~1h圖的一或多個半導體晶粒一起形成一個裝置。一些實施例中，基板200係印刷電路板(print circuit board,PCB)且係由環氧樹脂、聚合物、陶瓷、苯環丁烯(benzocyclobutene,BCB)、聚苯噁唑(polybenzoxazole,PBO)及上述之相似物所形成。另一實施例中，基板200可為中介片(interposer)，其可包括矽、玻璃、或上述之組合。又另一實施例中，基板200可為相同於或不同於半導體晶粒100的半導體晶粒。基板200包括接合墊(bonding pad)202a與202b，其包括鈦、銅、鎳、焊料、錫、鋁及上述之合金。在區域B1中，接合墊202a具有寬度D1a，而在區域B2中，接合墊202b具有寬度D1b。寬度D1a相同於寬度D1b。一些實施例中，寬度D1a不同於寬度D1b。
整合第1a~1h圖的一或多個半導體晶粒100與第2圖所示的基板200以形成一個裝置。如半導體晶粒100相關的敘述，基板200具有對應的內部與外部區域。因此，整合的裝置也具有所述的內部與外部區域及/或隔離與密集區域。半導體晶粒100以面朝下的方式組合。如第3圖所示，導電材料186不但連接著導電墊184a與接合墊202a，也連接著導電墊184b與接合墊202b。在組裝半導體晶粒100與基板200之前，可在上述其一之上施加助焊劑(flux)。於溫度200~300℃下實施迴焊(reflow)作業以形成晶粒上的導電墊與基板上對應的接合墊之間的結 合。
低介電常數材料作為金屬間介電(inter-metal dielectric)材料而廣泛地用於積體電路中。低介電常數材料通常具有較低的強度且有時為多孔狀，而因此他們較易被破壞與分層，特別係與高強度的材料一起使用時。在半導體晶粒中使用低介電常數材料會讓高強度填充材料之使用受到限制。經發現，一批樣品在熱循環測試過程中失效，且在具有較小的界面尺寸的尾端產生裂痕。導電材料之應變與介電材料之應變實質上平衡的樣品在進行測試時，則可發現顯著的改善。
請參照表1，比例R係導電墊之金屬寬度對接合墊之金屬寬度的比。以第3圖之裝置來看，第一個比例R為半導體晶粒100的導電墊184a之寬度W1a比上基板200之接合墊202a的寬度D1a。第二個比例R為半導體晶粒100的導電墊184b之寬度W1b比上基板200之接合墊202b的寬度D1b。表1顯示以ANSYS 工具模擬的導電材料之應變與介電材料之應變，且將比例R標準化為1.000。經發現，比例R與導電材料之應變及介電材料之應變有密切關係。當比例R從0.955升至1.364，導電材料之應變從1.22降至0.71而介電材料之應變從0.99升至1.18。在容許的導電材料之應變與介電材料之應變的一區域內，可指定比例R的有效範圍。在操作裝置的過程中，高導電材料之應變，例如超過1.22，可能會引發疲勞(fatigue)或裂痕。因此，指定一個較小的導電材料之應變，約等於或小於1.22。較高的介電材料之應變也可能會引發裝置的失靈，而較小的介電材料之應變，約等於或小於1.14，可呈現較佳的裝置效能。因此，指定比例R約為1.0~1.3能呈現較佳的裝置效能。
可相信的是，半導體晶粒之外部區域的導電材料具有高於半導體晶粒之內部區域的導電材料的應變。在外部區域與內部區域排列不同的比例R能平衡導電材料之應變。根據不同的實施例，只要介電材料之應變維持在能接受的範圍內，在內部區域的比例R比在外部區域的比例R小，以對抗較高的導電材料之應變的主要影響。
請參照第1d圖，在D1區域的結合之比例R1小於在區域D2的結合之比例R2以平衡在半導體晶粒上的導電材料之應變與介電材料之應變，比例R2約為1.0~1.3而比例R1小於R2且約為1.0。一些實施例中，比例R1可為梯度(gradient)，往半導體晶粒之外部區域增加。其他實施例中，比例R2可為梯度，從靠近導電材料之內部區域朝向導電材料最外部增加。
請參照第1e圖，在E1區域的結合之比例R3小於在 區域E2的結合之比例R4，以平衡在半導體晶粒上的導電材料之應變與介電材料之應變。比例R4大於R3且約為1.0~1.3。比例R3約為1.0。一些實施例中，在四個角中的比例R4可具有相同或不同的值。另一些實施例中，在各個角的R4之值各自不同。
請參照第1f圖，在F1區域的結合之比例R5小於在區域F2的結合之比例R6，以平衡在半導體晶粒上的導電材料之應變與介電材料之應變。比例R6約大於1.0~1.3而比例R約為1.0。
請參照第1g圖，在G1區域的結合之比例R7小於在區域G2的結合之比例R8，以平衡在半導體晶粒上的導電材料之應變與介電材料之應變。R8約為1.0~1.3而R7約為1.0。一些實施例中，四個角中的比例R8可具有相同或不同的值。另一些實施例中，在各個角的R8之值各自不同。
請參照第1h圖，隔離區域(此區域包括一些實施例中的導電材料196，以及另一些實施例中的一或多個導電材料197、198、及199)的結合之比例R9大於在隔離區域外圍的密集區域中的結合之比例。比例R9約為1.0~1.3。一些實施例中，各個隔離的導電材料之比例R9可為相同或不同。
第4圖為上述方法400結合第1~3圖之流程圖。方法從步驟401開始，在半導體晶粒上形成導電墊，導電墊包括第一導電墊及第二導電墊。第一導電墊與第二導電墊分別具有第一寬度與第二寬度。在步驟403，在基板上形成接合墊，接合墊包括第三接合墊與第四接合墊。第三接合墊與第四接合墊具有第三寬度與第四寬度。在步驟405，導電材料在第一導電墊 與第三接合墊之間以及第二導電墊與第四接合墊之間做連結。第一導電墊之第一寬度與第三接合墊之第三寬度的比例不同於第二導電墊之第二寬度與第四接合墊之第四寬度之比例。
一些實施例中，一裝置包括一半導體晶粒以及一基板。半導體晶粒包括在半導體晶粒第一區域上的第一墊，其具有第一寬度，以及在半導體晶粒第二區域上的第二墊，其具有第二寬度。基板包括在基板上之第三區域上的第三墊，其具有第三寬度，以及在基板上之第四區域上的第四墊，其具有第四寬度。導電材料在第一墊與第三墊之間以及第二墊與第四墊之間做連結。第一墊之第一寬度與第三墊之第三寬度的比例小於第二墊之第二寬度與第四墊之第四寬度之比例。
一些實施例中，一裝置包括一半導體晶粒以及一基板。半導體包括在半導體晶例的隔離區域上的第一墊，其具有第一寬度。基板包括在基板的隔離區域上的第二墊，其具有第二寬度。導電材料在第一墊與第二墊之間做連結。第一墊之第一寬度與第二墊之第二寬度的比例約為1.0~1.3。
一些實施例中，提供一方法，以將半導體晶粒與基板形成一裝置。在半導體晶粒上形成導電墊。導電墊包括在半導體晶粒的第一區域上的第一導電墊，其具有第一寬度，以及在半導體晶粒的第二區域上的第二導電墊，其具有第二寬度。在基板上形成接合墊。接合墊包括在基板的第三區域上的第三接合墊，其具有第三寬度，以及在基板的第四區域上的第四接合墊，其具有第四寬度。導電材料在第一導電墊與第三接合墊之間以及第二導電墊與第四接合墊之間做連結。第一導電 墊之第一寬度與第三接合墊之第三寬度的比例不同於第二導電墊之第二寬度與第四接合墊之第四寬度之比例。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。舉例來說，任何所屬技術領域中具有通常知識者可輕易理解此處所述的許多特徵、功能、製程及材料可在本發明的範圍內作更動。
再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。另外，每一申請專利範圍構成個別的實施例，且本發明之保護範圍也包括各個申請專利範圍及實施例的組合。
158‧‧‧基板
160‧‧‧電子電路
162、168‧‧‧層間介電層
164‧‧‧插塞
166‧‧‧底金屬層
170‧‧‧頂插塞
172‧‧‧頂金屬層
174‧‧‧鈍化保護層
176‧‧‧開口
178、182‧‧‧聚合物層
180‧‧‧重分佈層
184‧‧‧頂部導電墊
186‧‧‧導電材料
188‧‧‧底部導電墊

Claims (10)

  1. 一種半導體裝置，包括：一半導體晶粒，其中該半導體晶粒包括：一第一墊，在該半導體晶粒之一第一區域上，該第一墊具有一第一寬度；一第二墊，在該半導體晶粒之一第二區域上，該第二墊具有一第二寬度；以及一基板，其中該基板包括：一第三墊，在該基板之一第三區域上，該第三墊具有一第三寬度；以及一第四墊，在該基板之一第四區域上，該第四墊具有一第四寬度；以及一導電材料，連結在該第一墊與該第三墊之間、及該第二墊與該第四墊之間；其中該第一墊之該第一寬度與該第三墊之該第三寬度的一比例A小於該第二墊之該第二寬度與該第四墊之該第四寬度之比例B。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該比例B約為1.0~1.3之間且其中該比例A約為1.0。
  3. 如申請專利範圍第1項所述之半導體裝置，其中：該第一區域係該半導體晶粒的一內部區域；以及該第二區域係該半導體晶粒的一外部區域。
  4. 如申請專利範圍第3項所述之半導體裝置，其中該外部區域設置於該半導體晶粒之一最大半徑與該最大半徑之2/3 處之間。
  5. 如申請專利範圍第3項所述之半導體裝置，其中該外部區域包括該半導體晶粒之四角。
  6. 如申請專利範圍第1項所述之半導體裝置，其中該半導體晶粒係矩形且該外部區域係沿著該矩形半導體晶粒之外圍排列。
  7. 一種半導體裝置的製造方法，包括：形成多個導電墊在一半導體晶粒上，上述導電墊包括：在該半導體晶粒之一第一區域上的一第一導電墊，其具有一第一寬度；以及在該半導體晶粒之一第二區域上的一第二導電墊，其具有一第二寬度；形成多個接合墊在一基板上，上述接合墊包括：在該基板之一第三區域上的一第三接合墊，其具有一第三寬度；以及在該基板之一第四區域上的一第四接合墊，其具有一第四寬度；以及形成一導電材料，其連結於該第一導電墊與該第三接合墊之間及該第二導電墊及該第四接合墊之間；其中該第一墊之該第一寬度與該第三墊之該第三寬度的一比例A不同於於該第二墊之該第二寬度與該第四墊之該第四寬度之比例B。
  8. 如申請專利範圍第7項所述之半導體裝置的製造方法，其中該比例B約為1.0~1.3之間且該比例B大於該比例A。
  9. 如申請專利範圍第7項所述之半導體裝置的製造方法，其中該導電材料包括至少一焊球，其係由植球(ball placement)、球轉移(ball transfer)、或前述之組合所形成。
  10. 如申請專利範圍第7項所述之半導體裝置的製造方法，其中該第二區域係該半導體晶粒的一隔離區域；以及該第四區域係該基板的一隔離區域，其對應到該半導體晶粒的該隔離區域。
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