CN103050447A - 半导体器件的封装方法及其结构 - Google Patents

半导体器件的封装方法及其结构 Download PDF

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Publication number
CN103050447A
CN103050447A CN2012101949895A CN201210194989A CN103050447A CN 103050447 A CN103050447 A CN 103050447A CN 2012101949895 A CN2012101949895 A CN 2012101949895A CN 201210194989 A CN201210194989 A CN 201210194989A CN 103050447 A CN103050447 A CN 103050447A
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China
Prior art keywords
tube core
tube
carrier wafer
core groove
cores
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CN2012101949895A
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Inventor
林俊成
洪瑞斌
林义航
董簪华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN103050447A publication Critical patent/CN103050447A/zh
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Abstract

本发明公开了半导体器件的封装方法及其结构。在一个实施例中，一种封装半导体器件的方法包括提供载具晶圆；提供多个管芯；以及在载具晶圆的上方形成管芯凹槽材料。在该管芯凹槽材料中形成了多个管芯凹槽。将多个管芯中的至少一个放置在管芯凹槽材料的多个管芯凹槽的每个中。形成多个封装件，该多个封装件的每个均形成在多个管芯中的相应的至少一个管芯上方。

Description

半导体器件的封装方法及其结构
技术领域
本发明一般地涉及半导体领域，更具体地来说，涉及半导体器件的封装方法及其结构。
背景技术
半导体器件被广泛应用于各种电子设备(诸如，个人电脑、手机、数码相机、和其他电子器材)中。半导体行业通过不断缩小部件尺寸来不断改进各种电子元件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，从而将更多的元件集成到指定区域中。在一些应用方式中，这些较小的电子元件也需要更小的封装件，这种更小的封装件所占用的面积比原来的封装件更小。
已经开发的一种更小的半导体器件封装类型是晶圆级封装(WLP)，其中，集成电路管芯被封装在通常包括再分配层(RDL)的封装件中，该再分配层用于集成电路管芯的接触焊盘扇出布线(fan out wiring)，从而使得可以以比管芯的接触焊盘更大的间距来制造电接触件。在整个说明书中，术语“管芯”指的是单数和复数。
在将管芯设置于WLP载具晶圆上方并且将模塑料形成在管芯上方时，管芯会产生非预期的运动。由于随后形成的WLP材料层(诸如，RDL)，尤其是在两个或多个管芯被封装在单个封装件的多芯片封装件中时，管芯旋转或管芯移位可能导致对准问题，所以管芯运动经常是很明显的。在封装件形成中的这种管芯运动会导致成品率降低。
因此，本领域需要解决的问题是改进半导体器件的封装设计。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种封装半导体器件的方法，所述方法包括：提供载具晶圆；提供多个管芯；将管芯凹槽材料形成在所述载具晶圆上方；将多个管芯凹槽形成在所述管芯凹槽材料中；将所述多个管芯中的至少一个放置在所述管芯凹槽材料中的所述多个管芯凹槽的每个中；以及形成多个封装件，所述多个封装件中的每个均形成在所述多个管芯的相应的至少一个管芯上方。
在该方法中，形成所述管芯凹槽材料包括形成感光材料。
在该方法中，形成所述管芯凹槽材料包括形成聚合物基材料。
在该方法中，形成所述管芯凹槽材料包括形成聚酰亚胺。
在该方法中，将所述多个管芯中的至少一个放置在所述管芯凹槽材料的所述多个管芯凹槽的每个中包括：使用自动拾取和放置装置将所述多个管芯放置在所述载具晶圆上方。
该方法进一步包括：在形成所述管芯凹槽材料之前，在所述载具晶圆上方形成粘合剂层。
该方法进一步包括：在形成所述多个封装件之后，去除所述载具晶圆。
根据本发明的另一方面，提供了一种封装半导体器件的方法，所述方法包括：提供载具晶圆；在所述载具晶圆的上方形成粘合剂层；在所述粘合剂层上方形成材料；将所述材料图案化为图案，所述图案用于将多个管芯放置在所述载具晶圆上方；将所述多个管芯放置位于所述材料的相应的图案中所述载具晶圆上方的所述粘合剂层上方；将封装件形成在所述多个管芯上方；以及分离所述封装件。
在该方法中，将所述封装件形成在所述多个管芯上方包括：在每个所述管芯上方均形成一个封装件。
在该方法中，将所述封装件形成在所述多个管芯上方包括：在多个所述管芯上方形成一个封装件。
在该方法中，放置所述多个管芯包括：将所述多个管芯正面朝下放置所述材料的所述图案中所述载具晶圆上方的所述粘合剂层上方。
在该方法中，放置所述多个管芯包括：将所述多个管芯正面朝上放置所述材料的所述图案中所述载具晶圆上方的所述粘合剂层上方。
在该方法中，将所述封装件形成在所述多个管芯的上方包括：在所述多个管芯的上方沉积模塑料。
在该方法中，所述多个管芯包括：位于所述管芯表面上的接触焊盘，并且进一步包括：在所述多个管芯上方形成再分配层(RDL)，其中，形成所述RDL包括：将所述RDL的导电部分连接至所述多个管芯的接触焊盘；在所述RDL的上方形成多个凸块下金属化层(UBM)结构；以及在所述多个UBM结构上方形成多个焊球。
在该方法中，形成所述材料包括形成光刻胶。
在该方法中，形成所述材料包括：形成WLCSP-HD8820、WLCSP-HD8930、或者JSR-WPR-5100。
根据本发明的又一方面，提供了一种封装的半导体器件，包括：至少一个集成电路，所述至少一个集成电路具有多个侧面；感光材料，设置在所述至少一个集成电路周围，所述感光材料基本上与所述至少一个集成电路的所述多个侧面上的所述至少一个集成电路邻接；以及封装件，设置在所述至少一个集成电路和所述感光材料的上方。
在该封装的半导体器件中，所述封装件包括：设置在所述至少一个集成电路上方的模塑料；设置在所述至少一个集成电路和所述模塑料上方的再分配层(RDL)；以及多个设置在所述RDL上方的焊球。
在该封装的半导体器件中，所述至少一个集成电路包括：紧邻所述集成电路的表面设置的多个接触焊盘，其中，与所述多个接触焊盘紧邻的所述至少一个集成电路的所述表面与所述模塑料紧邻。
在该封装的半导体器件中，所述至少一个集成电路包括：紧邻所述集成电路的表面设置的多个接触焊盘，其中，与所述多个接触焊盘紧邻的所述至少一个集成电路的所述表面与所述感光材料紧邻。
附图说明
为了更全面地理解本发明及其优点，现在，将结合附图所进行的以下描述作为参考，其中：
图1和图2示出了根据本发明的实施例封装半导体器件方法的截面图，其中，管芯凹槽材料形成在载具晶圆的上方，并且将管芯凹槽材料图案化成具有多个管芯凹槽；
图3A示出了图2中所示的实施例的多个管芯凹槽的俯视图，其中，根据实施例将管芯分别地封装到WLP中；
图3B示出了图2中所示的实施例的多个管芯凹槽的俯视图，其中，根据另一个实施例将多个管芯封装在单个WLP中；
图4至图8示出了根据实施例封装半导体器件的方法的截面图，其中，将管芯正面朝上放置在载具晶圆上方；
图9示出了是在切割封装的管芯之后，封装的半导体器件的更详细的截面图；以及
图10和图11示出了根据另一个实施例封装半导体器件的方法的截面图，其中，将管芯正面朝下放置在载具晶圆上方；
除非另有说明，在不同的附图中的相应的数字和符号通常指的是相应的部件。这些图示仅仅用于清楚地说明实施例的相关方面，不一定按比例绘制。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
本公开的实施例涉及封装设计和半导体器件的系统。此处将对新型封装方法和结构进行描述。
首先，参考图1，图1示出了根据本公开的实施例封装半导体器件方法的截面图。提供了载具晶圆100。例如，该载具晶圆100可以包括：玻璃、硅、氧化硅、氧化铝等。载具晶圆100的厚度可以在大约几密耳到几十密耳之间，并且在一些实施例中，也可以包括大约300mm的直径。可选地，载具晶圆100可以包括其他材料和尺寸。
将粘合剂102层应用在在载具晶圆100上方。例如，应用时，粘合剂102可以包括胶，并且可以包括液体。根据本发明的实施例，该粘合剂102包括适用于将多个管芯108(未在图1中示出；参见图5)粘附至载具晶圆100的材料。
如图1所示，将管芯凹槽材料104形成在粘合剂102层的上方。该管芯凹槽材料104在此处也被称为感光材料，或者在一些实施例中被称为材料。在一些实施例中，管芯凹槽材料104可以包括感光材料，例如，光刻胶。例如，在其他实施例中，管芯凹槽材料104可以包括聚合物基材料。例如，管芯凹槽材料104可以包括非感光材料层(诸如，聚酰亚胺或其他的材料)，例如，在一些实施例中，使用感光材料对该管芯凹槽材料进行图案化，然后，将感光材料去除。例如，管芯凹槽材料104可以包括WLCSP-HD8820、WLCSP-HD8930、或JSR-WPR-5100，该管芯凹槽材料的厚度尺寸d1为大约几μm到几百μm，但是可选地，管芯凹槽材料104可以包括其他材料和尺寸。例如，管芯凹槽材料104包括在半导体制造和封装工艺中使用的可接受的材料(即，与性能，诸如，温度、其他材料层的污染、收缩率、和伸长率相关的材料)。
如图2所示的截面图所示，利用光刻将管芯凹槽材料104图案化成具有多个管芯凹槽106。在一些实施例中，由于管芯凹槽材料104包括感光材料，所以优选地，可以直接对该管芯凹槽材料104进行图案化。可以通过利用穿过光刻掩膜(未示出)的能量或光线将管芯凹槽材料104曝光，并且可以对管芯凹槽材料104进行显影来图案化该管芯凹槽材料104。可选地，可以直接图案化管芯凹槽材料104。然后，例如，使用灰化工艺、蚀刻工艺、或其组合去除管芯凹槽材料104的曝光(或未曝光)部分，留下包括管芯凹槽106的图案。管芯凹槽106包括位于管芯凹槽材料104中的孔径，这些孔径使粘合剂102层曝光。如图3A和3B所示，例如，每个管芯凹槽106或图案可能均包括与管芯108的尺寸基本上相同的尺寸，在俯视图中，将该管芯放置在载具晶圆100上方。
图3A示出了图2所示的实施例的多个管芯凹槽106的俯视图，其中，单个的管芯108将根据实施例被分别封装到封装件中。图3B示出了图2所示的多个管芯凹槽106a，106b和106c的俯视图，其中，根据另一个实施例，将多个管芯108封装到多个单独的封装件中。
图4至图8示出了在图2所示的制造或封装步骤之后，根据实施例封装半导体器件108(此处也称为管芯108或集成电路108)的方法的截面图。如图4所示，在该实施例中，将多个管芯108正面朝上(例如，具有暴露接触焊盘110)放置在载具晶圆100上方。例如，每个芯片108均包括集成电路，该集成电路具有形成在其上的电路。例如，根据管芯108的应用和尺寸，可能存在形成在每个管芯108上方的几十、几百、或数以千计的电子器件。管芯108可以包括形成在其上的电路和/或电子功能器件的一层或多层，并且例如(未示出)，可以包括：导线、通孔、电容器、二极管、晶体管、电阻器、电感器、存储器件、逻辑器件、和/或其他电气元件。管芯108包括之前已经在半导体晶圆上制造并且已经与半导体晶圆分离(例如，与相邻的管芯108分离)的半导体器件或芯片。自动拾取和放置装置的一部分已经由111示出，该装置可以用于将管芯108附接至载具晶圆100(例如，附接至通过图案化的管芯凹槽材料104而暴露出来的粘合剂102层)。
管芯108可以包括：形成在其表面上方(例如，在图4所示的实施例中的管芯顶面上方)的多个接触焊盘110。如本实施例所示，将管芯108正面朝上放置在管芯凹槽106或所示实施例中的图案内的载具晶圆100上方的粘合剂102层上方。如图所示，每个管芯108均放置在管芯凹槽106中，该管芯凹槽在管芯凹槽材料104中形成。
如图3A和3B，在俯视图中，多个管芯108可以包括正方形或矩形的形状，该俯视图示出了管芯凹槽106、106a、106b、106c的图案。在俯视图中，管芯108可以包括多个侧面116。例如，如图所示，管芯108可以包括四个侧面。在将管芯108拾取和放置到管芯凹槽106中以后，管芯凹槽材料104可以基本上与管芯108邻接(例如，相邻)或在一些实施例中，基本上与管芯108的多个侧面116上的集成电路邻接。
接下来，如图5所示，将模塑料112形成在管芯108和管芯凹槽材料104的上方。例如，模塑料112包括封装材料并且可以包括环氧树脂、硅胶填充物和/或正型抗蚀剂材料，但也可以将其他材料用于模塑料112。可以将模塑料112沉积或模制在管芯108和管芯凹槽材料104上方。模塑料112的顶面可以高于(如图5所示)管芯108的顶面，与管芯108的顶面基本上齐平(如图6所示)，或稍低于管芯108的顶面。如图所示，将模塑料112填充到多个管芯108之间的空隙中。
由于在将模塑料112沉积到多个管芯108上的过程中，阻止或减少了多个管芯108在载具晶圆100上的运动，所以将多个管芯108放置到位于管芯凹槽材料104中的管芯凹槽106内的载具晶圆100上方是有利的。例如，根据此处描述的实施例，通过使用包括了感光材料或其他材料的新型管芯凹槽材料104，阻止了管芯108的移动，管芯108的旋转和/或管芯108的浮动。例如，在形成模塑料112的过程中，该模塑料112在管芯108上方向外对载具晶圆100的边缘施加作用力114。在一些封装过程中，管芯108在载具晶圆100的边缘处的运动可能会更明显，然而，新型管芯凹槽材料104包括感光材料或其他材料，该新型管芯凹槽材料104可以通过将管芯108保持在管芯凹槽106内的载具晶圆100上方的期望方位和定位来减少或消除这种管芯108的运动。
接下来，可以进行可选的研磨工艺，从而将多个管芯108的顶面平整化，从而使得至少可以减少并且可能基本上消除管芯108的顶面的任何不均匀性。如图6所示，如果模塑料112包括管芯108的顶面上方的部分，则模塑料112的这些部分通过研磨工艺去除。因此，模塑料112的剩余部分的顶面可以与多个管芯108的顶面齐平。此外，在研磨工艺过程中，多个管芯108的高度或厚度也可以减少到期望高度。
此外，如图6所示，包括RDL 118的布线层形成在多个管芯108的顶面上方。RDL 118可以包括：绝缘材料120a和多个导电部件122，形在该绝缘材料120a的中和顶面上方。导电部件122可以提供管芯108的接触焊盘110向已经封装的半导体器件130的其他部分的扇出(fan out)(例如，参见图8和图9)。如图7所示，另一种绝缘材料120b可以形成在绝缘材料120a和导电部件122的上方。RDL 118的绝缘材料120a和120b可以包括聚合物或其它绝缘材料。RDL 118的导电部件122的部分与管芯108上的接触焊盘110连接并且进行电接触。例如，导电部件122的部分可以包括电扇出结构。如图7所示，可选的凸块下金属化(UBM)结构124可以形成在RDL 118的部分和绝缘层120b的部分上方。如在图7所示，多个焊球126形成在RDL 118的部分上方。例如，UBM结构124便于焊球126的连接和形成。
例如，图7所示的结构实际上包括载具晶圆100上方的重建晶圆，该重建晶圆包括多个管芯108。在所示的实施例中，模塑料112、RDL 118、焊球126和管芯凹槽材料104包括用于多个管芯108的封装件，该封装件包括FO-WLP。
接下来，如图8所示，从封装的多个管芯108至少去除载具晶圆100。例如，在将载具晶圆100与封装的管芯108分离工艺中，模塑料112和RDL118支撑管芯108。例如，当利用光(即，激光)或热工艺去除载具晶圆100或载具晶圆100处于分离处理步骤中时，也可以去除粘合剂102层。然后，如在图9中以更详细的示图所示，在切割线128处分离或分开封装的多个管芯108，从而形成了单个的封装管芯108，此处也被称为封装半导体器件130。为了将封装的管芯108与相邻的封装的管芯108分离，可以将胶带(未示出)应用于管芯108。该胶带可以包括切割胶带，该切割胶带在分离工艺中支撑封装的管芯108。然后，从胶带上去除封装的多个管芯108，保留封装的半导体器件130。
图9示出了将封装的管芯108分离以后，封装的半导体器件130的更详细的截面图。图9还示出了管芯108和RDL 118的更详细的截面图。管芯108和RDL 118的更详细的视图为示例性的；可选地，管芯108和RDL118可以包括其他的结构、布局和/或设计。在所示的实施例中，管芯108包括衬底131，该衬底包括硅或其他半导体材料。绝缘层132a和132b可以包括沉积在衬底131上方的钝化层。管芯108的接触焊盘110可以形成在导电部件134的上方，该导电部件134设置在衬底131的上方或设置在衬底131的上部材料层中。该导电部件134可以包括金属和/或半导体焊盘、接触塞、通孔或导线，该导电部件实现与衬底131的有源部件(未显示)的电接触。接触焊盘110可以形成在绝缘层132a和/或132b中，该绝缘层可以包括聚合物层或其他绝缘材料。
在图1、图2、图4至图9所示的实施例中，管芯108正面朝上放置在载具晶圆100上方，其中，管芯108的接触焊盘110背向载具晶圆100。值得注意的是，虽然在附图中仅示出了每个管芯108的一个接触焊盘110；然而，例如，多个接触焊盘110，即，几十个或几百个接触焊盘110都可以形成在每个管芯108的表面上(未示出)。在图5至图9所示的实施例中，管芯108紧邻接触焊盘110的表面紧邻模塑料112。
图10和图11是根据另一个实施例封装半导体器件方法的截面图，其中，管芯正面朝下放置在载具晶圆100上方。在图10和图11中的各种部件使用与在图1至图9中相同的标号来表示，并且为了避免重复，图10和图11中的每个参考标号这里没有进行再次进行详细描述。
如图10所示，在本实施例中，封装的半导体器件140包括管芯108，该管芯108正面朝下放置在载具晶圆110上方，其中，管芯108的接触焊盘110面向载具晶圆100。在图10至图11所示的实施例中，管芯108的紧邻接触焊盘110的表面紧邻管芯凹槽材料104(例如，感光材料104)。如图11所示，可以形成具有导电部件122的RDL 118，在本实施例中，导电部件可以与管芯108的接触焊盘110进行电接触。
本发明的实施例的优点包括：提供了新型的封装方法和结构，该方法和结构在形成模塑料112和封装件的其他后续工艺期间阻止或减少了管芯108的移动、管芯108的旋转和/或管芯108的浮动和/或其他非预期的管芯108运动。此处所述的新型封装方法在半导体器件108的制造和封装工艺流程中容易实施。通过此处所述的新型管芯凹槽材料104在横向或水平方向上固定管芯108，同时粘合剂102层在垂直方向上固定管芯108，从而使该封装方法和结构可以实现更高的成品率和更好的可靠性。模塑工艺可以实现以下改进的结果，即，形成封装件的模塑料112。与随后形成的封装件层(例如，与RDL 118)的连接变得更可靠。例如，如图3B的俯视图所示，本发明的实施例尤其适用于具有一个以上管芯108的多芯片封装件，管芯在该多芯片封装件中的运动可以是确定的。
本发明的实施例包括此处所述的半导体器件或管芯108的封装方法，还包括封装的半导体器件130和140，已经使用此处所述的方法和材料封装该封装的半导体器件130和140。
虽然本发明的实施例已参考FO-WLP作出了详细的描述，但是各种不同的封装类型将得益于使用此处所述的管芯凹槽材料104，该管芯凹槽材料104协助放置管芯108并且确保管芯108在随后的工艺中保持原位。新型的封装技术和管芯凹槽材料104可以在其他的WLP设计中实施，例如，三维集成电路(3DIC)封装设计、硅通孔(TSV)封装设计、凸块导线直连(BOT)封装或晶圆上芯片装配封装(chip-on-wafer assembly package)。
根据本发明中的一个实施例，一种半导体器件的封装方法包括：提供载具晶圆；提供多个管芯；以及在载具晶圆的上方形成管芯凹槽材料。在管芯凹槽材料中形成多个管芯凹槽。将多个管芯中的至少一个放置在管芯凹槽材料中的多个管芯凹槽每个内部。形成多个封装件，该多个封装件中的每个均形成在多个管芯中的相应的至少一个管芯上方。
根据另一个实施例，一种半导体器件的封装方法包括：提供载具晶圆以及在载具晶圆的上方形成粘合剂层。在粘合剂层上方形成一种材料，并且通过用于要设置在载具晶圆上方的多个管芯的图案对该材料进行图案化。该方法包括：将多个管芯放置在位于材料中的相应的图案中的载具晶圆上的粘合剂层上方；在多个管芯上方形成封装件；以及将该封装件分离。
根据又一个实施例，封装的半导体器件包括：至少一个集成电路和设置在该至少一个集成电路周围的感光材料。该感光材料基本上与该至少一个集成电路的多个侧面的上的至少一个集成电路邻接。封装件设置在该至少一个集成电路和感光材料的上方。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。例如，本领域技术人员应理解，本文所述的多种特征、功能、工艺和材料可以进行改变，而保持在发明的范围内。而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明所采用的所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造、材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (10)

1.一种封装半导体器件的方法，所述方法包括：
提供载具晶圆；
提供多个管芯；
将管芯凹槽材料形成在所述载具晶圆上方；
将多个管芯凹槽形成在所述管芯凹槽材料中；
将所述多个管芯中的至少一个放置在所述管芯凹槽材料中的所述多个管芯凹槽的每个中；以及
形成多个封装件，所述多个封装件中的每个均形成在所述多个管芯的相应的至少一个管芯上方。
2.根据权利要求1所述的方法，其中，形成所述管芯凹槽材料包括形成感光材料。
3.根据权利要求1所述的方法，其中，形成所述管芯凹槽材料包括形成聚合物基材料。
4.根据权利要求1所述的方法，其中，形成所述管芯凹槽材料包括形成聚酰亚胺。
5.根据权利要求1所述的方法，其中，将所述多个管芯中的至少一个放置在所述管芯凹槽材料的所述多个管芯凹槽的每个中包括：使用自动拾取和放置装置将所述多个管芯放置在所述载具晶圆上方。
6.根据权利要求1所述的方法，进一步包括：在形成所述管芯凹槽材料之前，在所述载具晶圆上方形成粘合剂层。
7.根据权利要求1所述的方法，进一步包括：在形成所述多个封装件之后，去除所述载具晶圆。
8.一种封装半导体器件的方法，所述方法包括：
提供载具晶圆；
在所述载具晶圆的上方形成粘合剂层；
在所述粘合剂层上方形成材料；
将所述材料图案化为图案，所述图案用于将多个管芯放置在所述载具晶圆上方；
将所述多个管芯放置位于所述材料的相应的图案中所述载具晶圆上方的所述粘合剂层上方；
将封装件形成在所述多个管芯上方；以及
分离所述封装件。
9.根据权利要求8所述的方法，其中，将所述封装件形成在所述多个管芯上方包括：在每个所述管芯上方均形成一个封装件。
10.一种封装的半导体器件，包括：
至少一个集成电路，所述至少一个集成电路具有多个侧面；
感光材料，设置在所述至少一个集成电路周围，所述感光材料基本上与所述至少一个集成电路的所述多个侧面上的所述至少一个集成电路邻接；以及
封装件，设置在所述至少一个集成电路和所述感光材料的上方。
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US20160343615A1 (en) 2016-11-24
US9406581B2 (en) 2016-08-02
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