CN106057760A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

Info

Publication number
CN106057760A
CN106057760A CN201510757656.2A CN201510757656A CN106057760A CN 106057760 A CN106057760 A CN 106057760A CN 201510757656 A CN201510757656 A CN 201510757656A CN 106057760 A CN106057760 A CN 106057760A
Authority
CN
China
Prior art keywords
conductive component
conductive
face
height
dielectric material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510757656.2A
Other languages
English (en)
Other versions
CN106057760B (zh
Inventor
林孟良
黄震麟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN106057760A publication Critical patent/CN106057760A/zh
Application granted granted Critical
Publication of CN106057760B publication Critical patent/CN106057760B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明描述了半导体器件及其形成方法。实施例是包括衬底上的焊盘的一种器件。钝化膜位于衬底上并且覆盖焊盘的至少部分。第一导电部件位于焊盘上并且具有平坦顶面，其中第一导电部件具有从焊盘至第一导电部件的平坦顶面测得的第一高度。第二导电部件位于钝化膜上并且具有非平坦顶面，其中第二导电部件具有从钝化膜至第二导电部件的非平坦顶面测得的第二高度。

Description

半导体器件及其形成方法
技术领域
本发明的实施例涉及集成电路器件，更具体地，涉及半导体器件及其形成方法。
背景技术
半导体器件用于各种电子应用中，作为实例，诸如个人计算机、手机、数码相机和其他电子设备。通常通过在半导体衬底上方依次沉积绝缘或介电层、导电层和半导体材料层以及使用光刻图案化各个材料层以在材料层上形成电路组件和元件来制造半导体器件。通常在单个半导体晶圆上制造数十或数百个集成电路。通过沿着划线锯切集成电路来分割单独的管芯。然后例如以多芯片模块或其他类型的封装分别封装单独的管芯。
通过不断减小最小部件尺寸，半导体工业不断改进各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成度，这允许更多的组件集成到给定区域内。在一些应用中，诸如集成电路管芯的这些较小的电子组件可能也需要比之前的封装件利用更小区域的较小的封装件。
发明内容
本发明的实施例提供了一种器件，包括：焊盘，位于衬底上；钝化膜，位于所述衬底上并且覆盖所述焊盘的至少部分；第一导电部件，位于所述焊盘上并且具有平坦顶面，所述第一导电部件具有从所述焊盘至所述第一导电部件的所述平坦顶面测得的第一高度；以及第二导电部件，位于所述钝化膜上并且具有非平坦顶面，所述第二导电部件具有从所述钝化膜至所述第二导电部件的所述非平坦顶面测得的第二高度。
本发明的另一实施例提供了一种器件，包括：焊盘，位于半导体衬底上；共形钝化膜，位于所述半导体衬底上并且覆盖所述焊盘的至少部分；导电通孔，位于所述焊盘上并且具有从所述焊盘至所述导电通孔的顶面测得的第一高度；导电线，位于所述共形钝化膜上并且具有从所述共形钝化膜至所述导电线的顶面测得的第二高度，所述第一高度大于所述第二高度；以及介电材料，位于所述共形钝化膜上方并且具有与所述导电通孔的顶面共面的顶面，所述介电材料包封所述导电线。
本发明的又一实施例提供了一种方法，包括：实施第一形成工艺以在衬底上方形成第一高度的第一导电部件和第二高度的第二导电部件，所述第一高度从所述第一导电部件的底面至所述第一导电部件的顶面测得，并且所述第二高度从所述第二导电部件的底面至所述第二导电部件的顶面测得，所述第一高度大于所属第二高度；以及以介电材料包封所述第一导电部件的侧壁以及所述第二导电部件的顶面和侧壁，所述第一导电部件的顶面与所述介电材料的顶面共面。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图9是根据一些实施例的在用于形成半导体器件的工艺期间的中间步骤的截面图。
图10至图13示出了根据一些实施例的在用于形成和测试半导体器件的工艺期间的中间步骤的截面图。
图14、图15和图16示出了根据一些实施例的半导体器件的截面图。
图17至图24示出了根据一些实施例的在用于形成叠层封装件(PoP)结构的工艺期间的中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作相应的解释。
本文中讨论的实施例可以在特定上下文中讨论，即，可以是扇出型或扇入型晶圆级封装件中的组件的半导体器件。其他实施例预期其他应用，诸如对阅读本发明之后的本领域普通技术人员将显而易见的不同封装件类型或不同配置。应该注意，本文中讨论的实施例可以不必示出可以存在于结构中的每个组件或部件。例如，诸如当一个组件的讨论可能足以表达实施例的各方面时，从图中可以省略多倍的组件。此外，本文中讨论的方法实施例可以讨论为以特定顺序实施；然而，其他方法实施例可以以任何逻辑顺序实施。
在特定地公开示出的实施例之前，通常将公开特定有利特征和本发明的实施例的方面。一般来说，本发明是半导体器件及其形成方法以增加晶圆生产量，降低处理成本，改进介电材料的间隙填充以及减小晶圆上的应力和翘曲。特别地，诸如以下公开的那些的实施例通过最小化形成半导体器件的互连结构所需的处理步骤的数量来增加晶圆生产量以及减小处理成本。通过控制电镀工艺以对于不同导电部件尺寸具有不同镀速来实现处理步骤的数量的这种减少，对于不同导电部件尺寸具有不同镀速可以提供在相同的电镀步骤中形成的导电部件的部件高度差异。
例如，在一些实施例中，较大的导电部件具有更快的镀速并且将在相同电镀工艺期间电镀至比较小的导电部件更大的高度(厚度)。例如，这允许较大的导电部件用作下一层级的互连结构的通孔，而较小的部件可以是位于当前互连层级内的导电线/导电结构。在该实例中，导电通孔和导电线同时在相同的工艺中形成，并且因此不需要额外的图案化和钝化层形成步骤。通孔和线的简化的形成和轮廓允许围绕那些部件的介电材料的改进的间隙填充能力。此外，因为许多钝化层需要固化步骤，固化步骤可以在晶圆上引起应力和翘曲，晶圆上的应力和翘曲的减小是由于钝化层形成步骤的最小化。
图1至图9示出了根据一些实施例的在用于形成管芯100的工艺期间的中间步骤的截面图。图1示出了包括衬底50、焊盘52和钝化膜54的处于处理的中间阶段的管芯100。在图1中示出的步骤之前，可以根据适用的制造工艺处理管芯100以在管芯100中形成集成电路，从而形成集成电路管芯100。衬底50可以包括块状半导体衬底、绝缘体上半导体(SOI)衬底、多层衬底或梯度衬底等。衬底50的半导体可以包括任何半导体材料，诸如硅、锗等的元素半导体；包括SiC、GaAs、GaP、InP、InAs、锑化铟、SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP等的化合物或合金半导体；或它们的组合。
衬底50可以包括集成电路器件(未示出)。作为本领域普通技术人员将认识到，可以在衬底50中和/或上形成诸如晶体管、二极管、电容器、电阻器等或它们的组合的各种集成电路器件以生成用于管芯100的设计的结构和功能需求。可以使用任何合适的方法形成集成电路器件。
衬底50也可以包括互连结构(未示出)。互连结构可以形成在集成电路器件上方并且设计为连接各种集成电路器件以形成功能电路。互连结构可以由介电材料(例如，低k介电材料)和导电材料(例如，铜)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。导电层和介电层可以包括金属线和通孔(未示出)以将集成电路器件电连接至焊盘52。在图中仅示出衬底50的部分，由于这足以完全描述示出的实施例。
管芯100还包括位于衬底50上方的焊盘52。焊盘52可以形成在衬底中的互连结构上方并且与衬底中的互连结构电接触以帮助提供至集成电路器件的外部连接。焊盘52位于可以称为管芯100的有源侧的一侧上。在一些实施例中，通过在介电层(未示出)或衬底50内形成凹槽(未示出)来形成焊盘52。凹槽可以形成为允许焊盘52嵌入在介电层和/或衬底50内。在其他实施例中，由于焊盘52可以形成在介电层或衬底50上，所以省略了凹槽。焊盘52可以包括由铜、钛、镍、金、锡等或它们的组合制成的薄晶种层(未示出)。焊盘52的导电材料可以沉积在薄晶种层上方。可以通过电化学镀工艺、化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)等或它们的组合形成导电材料。在实施例中，焊盘52的导电材料是铜、钨、铝、银、金、锡等或它们的组合。焊盘52可以形成为具有介于约0.5μm和约4μm之间的厚度。
为了清楚和简化，在管芯100中示出了一个焊盘52，并且本领域普通技术人员将容易理解，可以存在多于一个的焊盘52。
如图1所示，可以在衬底50上和焊盘52上方形成钝化膜54。钝化膜54可以由一种或多种合适的介电材料制成，诸如氧化硅、氮化硅、低k电介质(诸如碳掺杂的氧化物)、极低k电介质(诸如多孔碳掺杂的二氧化硅)、聚合物(诸如聚酰亚胺、阻焊剂、聚苯并恶唑(PBO)、苯并环丁烯(BCB)、模塑料等)或它们的组合。钝化膜54可以通过诸如CVD、PVD、ALD、旋涂电介质工艺等或它们的组合的工艺形成，并且可以具有介于约0.5μm和约30μm之间的厚度。在一些实施例中，焊盘52的顶面和钝化膜54的底面的部分齐平。
形成穿过钝化膜54的开口以暴露焊盘52的部分。例如，可以通过蚀刻、研磨、激光技术等或它们的组合形成该开口。
图2示出了在衬底50、钝化膜54和焊盘52上方形成晶种层56。晶种层56直接接触钝化膜54的开口中的焊盘52的顶面。在一些实施例中，晶种层56是金属层，金属层可以是单层或包括由不同材料形成的多个子层的复合层。晶种层56可以由铜、钛、镍、金等或它们的组合形成。在一些实施例中，晶种层56包括钛层和位于钛层上方的铜层。例如，可以使用PVD等形成晶种层56。
图3示出了晶种层56上方的光刻胶58的形成和图案化。在一些实施例中，在晶种层56上方形成光刻胶58并且图案化光刻胶58，然后在图案化的光刻胶58中形成导电部件62和64(见图4)。可以通过诸如旋涂工艺的湿工艺或通过干工艺(诸如通过施加干膜)来形成光刻胶58。可以在光刻胶58中形成多个开口60以暴露下面的晶种层56。在焊盘52上方形成开口60A，而在钝化膜54上方形成开口60B。
图4示出了分别在开口60A和60B中形成导电部件62和64。图4中示出的导电部件62和64分别具有凸形顶面62A和64A。在另一实施例中，导电部件62和64的顶面62A和64A可以是基本上平坦(未示出)或凹形(未示出)的。导电部件62和64的顶面62A和64A的形状/轮廓可以受到用于形成导电部件62和64的工艺的参数的控制。此外，可以控制形成工艺参数以基于它们的尺寸(例如，部件直径、部件顶面面积)的不同而对于导电部件62和导电部件64具有不同的形成速率。对于在相同的形成步骤中形成的导电部件62和64，形成速率的这些不同可以提供部件高度差异(例如，H1相对于H2)。
在一些实施例中，通过诸如电镀或化学镀等的镀形成导电部件62和64。导电部件62和64可以由金属形成，如铜、铝、镍、金、银、钯、锡等或它们的组合，并且可以具有包括多个层的复合结构。在一些实施例中，导电部件62的直径D1大于约40μm。在实施例中，直径D1在从约40μm至约100μm的范围内。在一些实施例中，导电部件64的直径D2小于约20μm。在实施例中，直径D2在从约1μm至约20μm的范围内。在一些实施例中，直径D1/D2的比率在从约1至约100的范围内。导电部件62形成为具有高度H1，并且导电部件64形成为具有高度H2。在一些实施例中，高度H1比高度H2大至少50％。例如，如果导电部件64形成为具有约20μm的高度H2，则导电部件62形成为具有至少约30μm的高度H1。
在一些实施例中，可以基于导电部件的配置，将称为加速剂、抑制剂和流平剂的添加剂化学物质添加到镀液中。
在通过电镀形成导电部件62和64的实施例中，可以通过改变镀工艺的参数(诸如电流密度、镀液、镀液温度、镀时间跨度、镀工具室流、光刻胶58的高度或它们的组合)来实现导电部件62和64的高度差异(H1相对于H2)。例如，在较低电流密度(例如，10mA/cm2及以下)下，电镀工艺的镀速受到镀液和光刻胶58之间的流体摩擦的较大影响。该流体摩擦减慢和/或遣散光刻胶58附近的镀源离子，从而使得用于导电部件64的光刻胶58中的窄开口显著地减少可以到达这些窄开口中的阴极(例如，晶种层56和导电部件64)的镀源离子的量。类似地，流体摩擦减慢和/或遣散用于导电部件62的较宽开口的光刻胶58附近的镀源离子，但是较宽开口的较大区域不受流体摩擦的影响(例如，开口的中间部分)，从而使得镀源离子可以更快和更容易到达导电部件62。此外，在镀工艺期间，在导电部件(62和64)附近形成梯度离子浓度的区域(有时称为扩散层)，并且用于导电部件62的较宽开口中的扩散层可以更薄，这可以引起电流拥挤效应。此外，导电部件62和64的中间部分比边缘部分镀得更快，这可能是由于流体摩擦和/或加速剂添加剂，其引起凸形顶面62A和64A。因此，在较低的电流密度下，导电部件62可以以比导电部件64更快的速率进行电镀，并且因此可以在相同的时间量(例如，相同的时间跨度)内达到比导电部件64更大的高度。此外，在较高的电流密度(例如，20mA/cm2及以下)下，电镀工艺的镀速受到镀工艺的磁场的较大影响，从而使得较小的部件可以由于光刻胶58附近的电流拥挤而更快地镀。
图5示出了在去除位于导电部件62和64外部的光刻胶58和晶种层56之后的导电部件62和64。可以通过诸如灰化、蚀刻工艺等或它们的组合的合适的去除工艺去除光刻胶58和晶种层56。
为了清楚和简化，在管芯100中示出了一个导电部件62和两个导电部件64，并且本领域普通技术人员将容易理解，可以存在多于一个的导电部件62和两个以上或以下的导电部件64。
图6示出了集成电路管芯100的有源侧上(诸如钝化膜54以及导电部件62和64上)的介电材料70的形成。介电材料70可以包封导电部件62和64。在一些实施例中，介电材料70与管芯100横向相连。介电材料70可以是诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物。在其他实施例中，介电材料70由以下材料形成：诸如氮化硅的氮化物；诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)等的氧化物；等等。可以通过诸如旋涂、CVD、层压等或它们的组合的任何可接受的沉积工艺形成介电材料70。
在一些实施例中，导电部件62和64掩埋在介电材料70中，并且如图7所示，对介电材料70实施诸如研磨的平坦化步骤。平坦化步骤用于去除介电材料70的过量部分，该过量部分位于导电部件62的顶面62A上方。在一些实施例中，导电部件62的顶面62A被暴露和平坦化，并且与介电材料70的顶面70A齐平。在这些实施例中，导电部件62平坦化为具有高度H3。虽然高度H3可以小于高度H1(平坦化之前的导电部件62的高度)，平坦化之后的导电部件62的高度H3大于导电部件64的高度H2。高度H3和H2之间的差足以将导电部件64与形成在介电材料70的顶面70A上的另一导电部件(例如，导电部件80)隔离。如图所示，导电部件62延伸至介电材料70的顶面70A，并且可以用作至下一导电层(见图9中的78和80)的通孔并且此后可以称为导电通孔62。此外，导电部件64嵌入在介电材料70内并且与下一导电层(见图9中的78和80)隔离，并且可以用作导电线且此后可以称为导电线64。导电部件62也可以称为柱或微凸块。
在平坦化步骤之后，导电通孔62和导电线64位于管芯100的互连结构的相同的导电层中，其中导电通孔62具有平坦顶面，而导电线64具有非平坦(凸形)顶面。
图8示出了介电材料70、导电通孔62和导电线64上方的晶种层72的形成以及光刻胶74的形成和图案化。晶种层72直接接触导电通孔62。在一些实施例中，晶种层72是金属层，金属层可以是单层或包括由不同材料形成的多个子层的复合层。晶种层72可以由铜、钛、镍、金等或它们的组合形成。在一些实施例中，晶种层72包括钛层和位于钛层上方的铜层。例如，可以使用PVD等形成晶种层72。
在一些实施例中，在晶种层72上形成并且图案化光刻胶74，然后在图案化的光刻胶74中形成导电部件78和80(见图9)。可以通过诸如旋涂工艺的湿工艺或通过干工艺(诸如通过施加干膜)来形成光刻胶74。可以在光刻胶74中形成多个开口76以暴露下面的晶种层72。在导电通孔62上方形成开口76A，而在介电材料70上方形成开口76B。在一些实施例中，省略开口76B。
图9示出了导电部件78和80的形成以及位于导电部件78和80外部的光刻胶74和部分晶种层72的去除。在一些实施例中，通过CVD、ALD、PVD、溅射等或诸如电镀或化学镀的镀等形成导电部件78和80。导电部件78和80可以由金属形成，如铜、铝、镍、金、银、钯、锡等或它们的组合，并且可以具有包括多个层的复合结构。在一些实施例中，通过与导电部件62和64类似的工艺形成导电部件78和80，从而使得导电部件78的高度可以比导电部件80的高度高至少50％。在一些实施例中，导电部件78和80形成为具有相同的高度或平坦化为具有相同的高度。
虽然未示出，可以在导电部件78和80上方形成另一介电材料(类似于介电材料70)，之后可以形成另一层导电部件。该工艺重复的次数可以与管芯100的互连结构的设计所需的次数一样多。
通过将镀工艺控制为对于不同的导电部件尺寸具有不同的镀速，可以实现在相同的处理步骤中形成的导电部件的高度差异。该部件高度差异允许较大的导电部件例如用作至下一层级互连结构的通孔，而较小的部件可以是位于当前互连层级内的导电线/结构。由于导电通孔和导电线同时在相同的工艺中形成，减少了图案化步骤和钝化/介电层的数量。由于许多钝化/介电层需要固化步骤，固化步骤可以引起管芯上的应力和翘曲，所以图案化步骤和钝化/介电层的该减少可以进一步引起管芯上的应力和翘曲的减小。
图10至图13示出了根据一些实施例的在用于形成和测试半导体器件的工艺期间的中间阶段的截面图。图10示出的管芯100处于与图5中示出的步骤类似的处理的中间步骤。关于该实施例的细节类似于先前描述的实施例的那些，本文中将不再重复。
图10中的实施例包括分别位于导电通孔62和导电线64的顶面62A和64A上的金属覆盖层90。金属覆盖层90可以包括镍、锡、锡铅、金、银、钯、铟、镍钯金、镍金等或它们的组合并且可以通过镀工艺形成。在一些实施例中，用于形成金属覆盖层90的镀工艺的时间跨度小于用于形成导电部件62和64的镀工艺的时间跨度。在实施例中，形成金属覆盖层90的镀工艺的实施时间小于100秒，诸如在从约30秒至约75秒的范围内。金属覆盖层90的顶面90A分别与导电通孔62和导电线64的顶面62A和64A共形。在一些实施例中，金属覆盖层90具有凸形顶面90A。
图11A和图11B示出了在处理期间使用具有探针接触件96的测试结构94以对管芯100实施测试。该测试可以与管芯100的形成原位实施并且可以允许监测管芯100的良率。金属覆盖层90允许测试结构94的探针接触件96具有平坦端部96A(与尖端相反)，平坦端部96A不会损坏导电部件62和/或金属覆盖层90。金属覆盖层90也允许探针接触件96和导电通孔62之间的快速且可靠的连接。在一些实施例中，金属覆盖层90不被氧化，这允许探针接触件96和导电通孔62之间的更可靠的接触。与在铝焊盘上使用尖锐的探针接触件相比，平坦端部的探针接触件96、具有金属覆盖层90的导电通孔62允许测试速率(每小时的晶圆)增加约7-8倍。
图12示出了集成电路管芯100的有源侧上(诸如钝化膜54、导电部件62和64以及金属覆盖层90上)的介电材料70的形成。介电材料70可以包封导电部件62和64以及金属覆盖层90。在一些实施例中，介电材料70与管芯100横向相连。介电材料70可以是诸如PBO、聚酰亚胺、BCB等的聚合物。在其他实施例中，介电材料70由以下材料形成：诸如氮化硅的氮化物；诸如氧化硅、PSG、BSG、BPSG等的氧化物；等等。可以通过诸如旋涂、CVD、层压等或它们的组合的任何可接受的沉积工艺形成介电材料70。
在一些实施例中，导电部件62和64以及金属覆盖层90掩埋在介电材料70中，并且如图13所示，对介电材料70实施诸如研磨的平坦化步骤。平坦化步骤用于去除介电材料70的过量部分，该过量部分位于导电部件62的顶面62A上方。在一些实施例中，导电部件62上的金属覆盖层90的至少部分保留并且被平坦化为具有平坦顶面并且与介电材料70的表面70A齐平。
在平坦化步骤之后，可以形成晶种层72以及导电部件78和80。以上已经描述了这些结构的形成，并且本文中不再重复该描述。
通过在导电通孔62上方具有金属覆盖层90，探针接触件96的端部可以是平坦的(与尖端相反)，平坦端部不损坏导电通孔62和/或金属覆盖层90。此外，与在铝焊盘上使用尖锐的探针接触件相比，平坦端部的探针接触件96、具有金属覆盖层90的导电通孔62允许测试速率(每小时的晶圆)增加约7-8倍。
图14、图15和图16示出了根据一些实施例的半导体器件的截面图。图14中的实施例类似于图13中示出的实施例，除了在图14中的实施例中，去除了导电部件62中的基本上所有的金属覆盖层90，从而使得导电部件62的顶面62A被暴露和平坦化，并且与介电材料70的表面70A齐平。
图15示出的实施例与图13中的先前描述的实施例类似，除了在图15中，金属覆盖层90延伸至导电通孔62和导电线64的侧壁。关于该实施例的细节与先前描述的实施例的那些类似，本文中将不再重复。
图15中的金属覆盖层90可以形成为类似于图13中的金属覆盖层90，除了形成图15中的金属覆盖层90的镀工艺的实施时间周期长于图13的实施例的时间周期以允许形成在导电通孔62和导电线64的侧壁上。
图16示出的实施例与图15中示出的实施例类似，除了在图16中的实施例中，去除了导电部件62的顶面上的基本上所有的金属覆盖层90，从而使得导电部件62的顶面62A被暴露和平坦化，并且与介电材料70的表面70A齐平。在平坦化步骤之后，金属覆盖层90仅位于导电通孔62的侧壁上，同时金属覆盖层90位于导电线64的顶面和侧壁上。
图17至图24示出了根据一些实施例的在用于形成叠层封装(PoP)结构的工艺期间的中间步骤的截面图。图17示出了在第一封装件300的形成中的中间步骤，第一封装件300包括载体衬底200、位于载体衬底200上方的粘合层202和位于粘合层202上方的介电层204。载体衬底200可以是为载体衬底200上方的层提供(在制造工艺的中间操作期间)机械支撑的任何合适的衬底。载体衬底200可以是包括玻璃、硅(例如，硅晶圆)、氧化硅、金属板、陶瓷材料等的晶圆。
可以在载体衬底200上设置(例如，层压)粘合层202。粘合层202可以由胶形成，诸如当暴露于UV光时失去其粘性的紫外(UV)胶、当加热时失去其粘性的光热转换(LTHC)材料等。粘合层202可以作为液体分配并且被固化，可以是层压在载体衬底200上的层压膜等。粘合层202的顶面可以是齐平的并且可以具有高度的共面性。
在粘合层202上方形成介电层204。介电层204可以是氮化硅、碳化硅、氧化硅、低k电介质(诸如碳掺杂的氧化物)、极低k电介质(诸如多孔碳掺杂的二氧化硅)、聚合物(诸如环氧树脂、聚酰亚胺、BCB、PBO等)或它们的组合，但是也可以使用其他相对较软的通常为有机物的介电材料。可以通过CVD、PVD、ALD、旋涂电介质工艺等或它们的组合形成介电层204。
在一些实施例中，介电层204可以是背侧再分布结构204。背侧再分布结构204可以由介电材料(例如，低k介电材料)和导电材料(例如，铜)的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双镶嵌等)形成。导电层和介电层可以包括金属线和通孔(未示出)。
此外，在图17中，电连接件208可以形成在晶种层(未示出)上方并且在基本上垂直于介电层204的表面的方向上从晶种层延伸。在一些实施例中，通过镀工艺形成电连接件208。在这些实施例中，电连接件208由铜、铝、镍、金、银、钯、锡等或它们的组合制成并且可以具有包括多个层的复合结构。在这些实施例中，可以在载体衬底200上方形成光刻胶(未示出)。在一些实施例中，在晶种层上形成并且图案化光刻胶，然后在图案化的光刻胶中形成电连接件208。可以通过诸如旋涂工艺的湿工艺或通过干工艺(诸如通过施加干膜)来形成光刻胶。在光刻胶中形成多个开口以暴露下面的晶种层。然后实施镀步骤以镀电连接件208。
在可选实施例中，电连接件208可以是柱凸块，通过介电层204上方的引线接合以及切割接合引线来形成柱凸块，其中接合引线的部分仍附接至相应的接合球。例如，电连接件208可以包括下部和上部，其中，下部可以是以引线接合形成的接合球(未示出)，而上部可以是剩余的接合引线(未示出)。电连接件208的上部可以具有在上部的顶部、中间部分和底部均为均匀的均匀的宽度和均匀的形状。电连接件208可以由可以通过引线接合件接合的非焊料金属材料形成。在一些实施例中，电连接件208由铜线、金线等或它们的组合制成，并且可以具有包括多个层的复合结构。在引线接合的实施例中，可以省略晶种层和牺牲层。
此外，在图17中，集成电路管芯100通过粘合层206粘合至介电层204。在粘合至介电层204之前，可以根据适用的制造工艺处理集成电路管芯100以形成集成电路管芯100中的集成电路(见图1至图16)。粘合层206可以是诸如管芯附接膜等的任何合适的粘合剂。管芯100可以是单个管芯或可以是两个以上的管芯。管芯100可以包括诸如中央处理单元(CPU)、图形处理单元(GPU)等或它们的组合的逻辑管芯。在一些实施例中，管芯100包括管芯堆叠件(未示出)，管芯堆叠件可以包括逻辑管芯和存储管芯。管芯100可以包括输入/输出(I/O)管芯，诸如在第一封装件300和随后附接的第二封装件240之间提供连接的宽I/O管芯(见图23和图24)。管芯100可以包括利用以上在图1至图16中描述的近似镀高度差异形成的导电通孔62和导电线64。
管芯100的导电通孔62可以用作用于管芯100的焊盘。为了简化，示出了用于管芯100的一个互连层，但是可以存在多于一个的互连层。
图18示出了管芯100和电连接件208的包封。在一些实施例中，管芯100和电连接件208由模制材料210包封。例如，可以使用压缩模制将模制材料210模制在管芯100和电连接件208上。在一些实施例中，模制材料210由模塑料、聚合物、环氧树脂、氧化硅填充材料等或它们的组合制成。可以实施固化步骤以固化模制材料210，其中，固化可以是热固化、UV固化等或它们的组合。
如图18所示，在一些实施例中，管芯100、导电通孔62和电连接件208掩埋入模制材料210中，并且在模制材料210的固化之后，对模制材料210实施诸如研磨的平坦化步骤。平坦化步骤用于去除模制材料210的过量部分，过量部分位于导电通孔62和电连接件208的顶面上方。在一些实施例中，导电通孔62的表面和电连接件208的表面暴露，并且与模制材料210的表面齐平。电连接件208可以称为模制通孔(TMV)、封装件通孔(TPV)和/或集成扇出型(InFO)通孔(TIV)并且此后将称为TIV 208。
图19示出了在管芯100、TIV 208和模制材料210上方形成再分布层216和导电连接件218。再分布层216可以包括一个或多个金属层，有时称为M1和/或MN，其中，金属层M1是紧邻管芯100的金属层，并且金属层MN(有时称为顶部金属层MN)是最远离管芯100的金属层。贯穿说明书，术语“金属层”指的是相同层中的金属线212的集合。再分布层216可以包括一个或多个钝化层214，其中，在一个或多个钝化层214中设置一个或多个金属层(M1至MN)。
钝化层214可以是氮化硅、碳化硅、氧化硅、诸如碳掺杂的氧化物的低k电介质、诸如多孔碳掺杂的二氧化硅的极低k电介质、诸如环氧树脂、聚酰亚胺、BCB、PBO、阻焊剂(SR)的聚合物等或它们的组合，但是也可以使用其他相对较软的通常为有机物的介电材料，并且通过CVD、PVD、ALD、旋涂电介质工艺、层压工艺等或它们的组合沉积。钝化层214可以经受固化工艺以固化钝化层214，其中，固化可以是热固化、UV固化等或它们的组合。
可以使用单镶嵌和/或双镶嵌工艺、先通孔工艺或先金属工艺形成金属层212。金属层或通孔212可以由诸如铜、铝、钛等或它们的组合的导电材料形成，具有或不具有阻挡层。
在示例性实施例中，使用双镶嵌工艺形成金属层212。在该实例中，M1层的形成可以开始于在最下的钝化层214上形成蚀刻停止层(未示出)和在蚀刻停止层上形成下一钝化层214。一旦沉积下一钝化层214，可以蚀刻掉下一钝化层214的部分以形成凹进的部件，诸如沟槽和通孔，凹进的部件可以填充有导电材料以连接再分布层216的不同区域并且容纳金属线212和通孔。可以对剩余的金属层至MN重复该工艺。
再分布层216可以称为用于第一封装件300的正侧再分布层(见图23和图24)。该正侧再分布层216可以用于通过连接件218将第一封装件300连接至一个或多个封装件、封装衬底、组件等或它们的组合(见图24)。
金属层212的数量和钝化层214的数量仅用于说明的目的并且不限制。可以存在多于或少于示出的一个金属层的其他数量的层。可以存在与图19中示出的那些不同的其他数量的钝化层和其他数量的金属层。
图19还示出了位于再分布层216上方并且电连接至再分布层216的一组导电连接件218的形成。导电连接件218可以是焊料凸块、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件218可以包括诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合的导电材料。在导电连接件218是焊料凸块的实施例中，通过诸如蒸发、电镀、化学镀、印刷、焊料转移、植球等的这些常用的方法首先形成焊料层来形成导电连接件218。一旦在结构上已经形成焊料层，可以实施回流以将材料成形为期望的凸块形状。在另一实施例中，导电连接件218是通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本上垂直的侧壁。在一些实施例中，在金属柱连接件218的顶部上形成金属覆盖层(未示出)。金属覆盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍钯金、镍金等或它们的组合并且可以通过镀工艺形成。
虽然未示出，可以存在连接至再分布层216的UBM，其中，导电连接件218连接至UBM(未示出)。可以通过首先形成一组开口(未示出)来形成UBM，该一组开口可以形成为穿过最顶部的钝化层214以暴露金属层MN中的金属线212的表面。UBM可以延伸穿过钝化层214中的这些开口并且也沿着钝化层214的表面延伸。UBM可以包括三层导电材料，诸如钛层、铜层和镍层。然而，本领域普通技术人员将认识到，可以存在材料和层的许多合适的布置，诸如适合于形成UBM的铬/铬铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于UBM的任何合适的材料和材料层完全旨在包括在本申请的范围内。
图20A示出了根据实施例的去除载体衬底200和粘合层202以暴露介电层204。在该实施例中，在去除载体衬底200和粘合层202的同时，将第一封装件300放置在框架220上，其中导电连接件218邻接框架220。
图20B示出了根据另一实施例的去除载体衬底200和粘合层202以暴露介电层204。在该实施例中，在去除载体衬底200和粘合层202的同时，将第一封装件300放置在第二载体衬底222上，其中导电连接件218邻接第二载体衬底222。该实施例可以包括位于第二载体衬底222上的可剥性胶224，其中导电连接件218嵌入在可剥性胶224中。可剥性胶224可以有助于将第一封装件300固定至第二载体衬底222。在去除载体衬底200之后，可以通过剥离方法去除可剥性胶224，剥离方法包括热工艺、化学剥离工艺、激光去除、UV处理等或它们的组合。
在图21中，形成穿过介电层204的至少部分的开口以暴露背侧再分布结构204和/或TIV 208中的导电部件的部分。例如，可以使用激光钻孔、蚀刻等形成开口。
在图22中，使用导电连接件242将封装件240附接至背侧再分布结构204和/或TIV 208。封装件240可以是和/或包括任何封装件组件。例如，如图所示，每个封装件240包括衬底、位于衬底上的两个堆叠的集成电路管芯、将集成电路管芯电连接至衬底的引线接合以及包封堆叠的集成电路管芯和引线接合的包封剂。在实例中，封装件240的集成电路管芯是诸如动态随机存取存储器(DRAM)管芯的存储管芯。封装件240通过导电连接件242电连接和机械连接至背侧再分布结构204和/或TIV 208。在一些实施例中，导电连接件242可以是焊料凸块、金属柱、C4凸块、微凸块、ENEPIG形成的凸块等。在一些实施例中，可以回流导电连接件242以将封装件240附接至第一封装件300。封装件240的集成电路管芯通过例如封装件240中的引线接合和衬底、导电连接件242、背侧再分布结构204、TIV 208和正侧再分布结构216电连接和通信连接至集成电路管芯100。
此外，在图22中，通过沿着封装件240之间的划线区锯切244来实施分割工艺。锯切244将第一封装件300分割成单独的第一封装件300。图23示出了产生的分割的叠层封装(PoP)结构。分割产生了第一封装件300，该第一封装件300可以由分割的图22中的其中一个第一封装件300形成。如图所示，封装件240附接至第一封装件300的背侧再分布结构204。
在图24中，PoP结构附接至衬底302。外部导电连接件218电连接和机械连接至衬底302上的焊盘304。例如，衬底302可以是印刷电路板(PCB)等。
通过控制镀工艺以对于不同的导电部件尺寸具有不同的镀速，可以实现在相同的镀步骤中形成的导电部件的高度差异。该部件高度差异允许较大的导电部件例如用作至下一层级的互连结构的通孔，而较小的部件可以是当前的互连层级内的金属线/结构。由于同时在相同的工艺中形成导电通孔和导电线，减少了图案化步骤和钝化/介电层的数量。图案化步骤和钝化/介电层的该减少可以进一步引起管芯上的应力和翘曲的减小，因为许多钝化/介电层需要固化步骤，固化步骤可以引起管芯上的应力和翘曲。此外，由于位于导电通孔上方的金属覆盖层，测试探针接触件的端部可以是平坦的(与尖端相反)，这最小化对导电通孔和/或金属覆盖层的损坏。此外，与在铝焊盘上使用尖锐的探针接触件相比，平坦端部的测试探针接触件和具有金属覆盖层的导电通孔允许测试速率(例如，每小时的晶圆)增加约7-8倍。
实施例是包括衬底上的焊盘的一种器件。钝化膜位于衬底上并且覆盖焊盘的至少部分。第一导电部件位于焊盘上并且具有平坦顶面，其中第一导电部件具有从焊盘至第一导电部件的平坦顶面测得的第一高度。第二导电部件位于钝化膜上并且具有非平坦顶面，其中第二导电部件具有从钝化膜至第二导电部件的非平坦顶面测得的第二高度。
在上述器件中，其中，所述第一高度大于所述第二高度。
在上述器件中，其中，所述第一导电部件比所述第二导电部件具有更大的直径，在与所述衬底的主要表面平行的平面中测量所述第一导电部件和所述第二导电部件的直径。
在上述器件中，其中，所述非平坦顶面是凸形顶面。
在上述器件中，还包括：介电材料，位于所述钝化膜上方，所述介电材料横向包封所述第一导电部件和包封所述第二导电部件，所述介电材料的顶面与所述第一导电部件的所述平坦顶面共面。
在上述器件中，还包括：介电材料，位于所述钝化膜上方，所述介电材料横向包封所述第一导电部件和包封所述第二导电部件，所述介电材料的顶面与所述第一导电部件的所述平坦顶面共面；第一金属覆盖层，位于所述第一导电部件上，所述第一金属覆盖层的至少部分与所述介电材料的顶面共面，所述第一金属覆盖层的材料组分与所述第一导电部件的材料组分不同；以及第二金属覆盖层，位于所述第二导电部件上，所述第二金属覆盖层的材料组分与所述第二导电部件的材料组分不同。
在上述器件中，还包括：介电材料，位于所述钝化膜上方，所述介电材料横向包封所述第一导电部件和包封所述第二导电部件，所述介电材料的顶面与所述第一导电部件的所述平坦顶面共面；第一金属覆盖层，位于所述第一导电部件上，所述第一金属覆盖层的至少部分与所述介电材料的顶面共面，所述第一金属覆盖层的材料组分与所述第一导电部件的材料组分不同；以及第二金属覆盖层，位于所述第二导电部件上，所述第二金属覆盖层的材料组分与所述第二导电部件的材料组分不同，其中，所述第一金属覆盖层位于所述第一导电部件的侧壁上，并且所述第二金属覆盖层位于所述第二导电部件的侧壁上。
在上述器件中，还包括：介电材料，位于所述钝化膜上方，所述介电材料横向包封所述第一导电部件和包封所述第二导电部件，所述介电材料的顶面与所述第一导电部件的所述平坦顶面共面；第三导电部件，位于所述介电材料的顶面上方，所述第三导电部件接触所述第一导电部件；以及第四导电部件，位于与所述第三导电部件处于相同层级的所述介电材料的顶面上方，所述第四导电部件的至少部分与所述第二导电部件重叠，所述第四导电部件与所述第二导电部件电隔离。
在上述器件中，还包括：介电材料，位于所述钝化膜上方，所述介电材料横向包封所述第一导电部件和包封所述第二导电部件，所述介电材料的顶面与所述第一导电部件的所述平坦顶面共面；第三导电部件，位于所述介电材料的顶面上方，所述第三导电部件接触所述第一导电部件；以及第四导电部件，位于与所述第三导电部件处于相同层级的所述介电材料的顶面上方，所述第四导电部件的至少部分与所述第二导电部件重叠，所述第四导电部件与所述第二导电部件电隔离；第三金属覆盖层，位于所述第二导电部件上，所述第三金属覆盖层的材料组分与所述第二导电部件的材料组分不同。
在上述器件中，还包括：介电材料，位于所述钝化膜上方，所述介电材料横向包封所述第一导电部件和包封所述第二导电部件，所述介电材料的顶面与所述第一导电部件的所述平坦顶面共面；第一封装件，包括：第一集成电路管芯，包括所述衬底、所述钝化膜、所述第一导电部件、所述第二导电部件和所述介电材料，所述第一导电部件电连接至所述第一封装件的正侧再分布结构；包封剂，围绕所述第一集成电路管芯；和封装件通孔，延伸穿过所述包封剂，所述封装件通孔连接至所述正侧再分布结构；以及第二封装件，包括第二集成电路管芯，所述第二封装件通过一组连接件接合至所述第一封装件，所述一组连接件中的至少一个连接至所述封装件通孔。另一实施例是包括位于半导体衬底上的焊盘和位于衬底上并且覆盖焊盘的至少部分的共形钝化膜的一种器件。导电通孔位于焊盘上并且具有从焊盘至导电通孔的顶面测得的第一高度。导电线位于共形钝化膜上并且具有从共形钝化膜至导电线的顶面测得的第二高度，第一高度大于第二高度。介电材料位于共形钝化膜上方并且具有与导电通孔的顶面共面的顶面，介电材料包封导电线。
在上述器件中，其中，所述导电通孔具有平坦顶面，并且其中，所述导电线具有非平坦顶面。
在上述器件中，其中，所述导电通孔具有平坦顶面，并且其中，所述导电线具有非平坦顶面，所述导电线的所述非平坦顶面是凸形顶面。
在上述器件中，其中，所述导电通孔具有比所述导电线更大的直径，在与所述半导体衬底的主要表面平行的平面中测量所述导电通孔和所述导电线的直径。
在上述器件中，其中，所述导电通孔是从所述焊盘至所述导电通孔的顶面的连续的导电材料。
在上述器件中，其中，每个所述导电通孔和所述导电线均包括铜、铝、镍、金、银、钯、锡或它们的组合。
又一实施例是一种方法，包括：实施第一形成工艺以在衬底上方形成第一高度的第一导电部件和第二高度的第二导电部件。第一高度从第一导电部件的底面至第一导电部件的顶面测得，并且第二高度从第二导电部件的底面至第二导电部件的顶面测得。第一高度大于第二高度。该方法还包括以介电材料包封第一导电部件的侧壁以及第二导电部件的顶面和侧壁，第一导电部件的顶面与介电材料的顶面共面。
在上述方法中，其中，所述第一导电部件具有比所述第二导电部件更大的直径，在与所述衬底的主要表面平行的平面中测量所述第一导电部件和所述第二导电部件的直径。
在上述方法中，其中，实施所述第一形成工艺还包括在所述衬底上方实施电镀工艺并且持续第一时间量，其中，在所述第一时间量的最后，所述第一导电部件处于所述第一高度，并且所述第二导电部件处于所述第二高度。
在上述方法中，还包括：在所述介电材料和所述第一导电部件上方形成第三导电部件，所述第三导电部件接触所述第一导电部件；以及在与所述第三导电部件相同的层级处的所述介电材料的顶面上方形成第四导电部件，所述第四导电部件的至少部分与所述第二导电部件重叠，所述第四导电部件与所述第二导电部件电隔离。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种器件，包括：
焊盘，位于衬底上；
钝化膜，位于所述衬底上并且覆盖所述焊盘的至少部分；
第一导电部件，位于所述焊盘上并且具有平坦顶面，所述第一导电部件具有从所述焊盘至所述第一导电部件的所述平坦顶面测得的第一高度；以及
第二导电部件，位于所述钝化膜上并且具有非平坦顶面，所述第二导电部件具有从所述钝化膜至所述第二导电部件的所述非平坦顶面测得的第二高度。
2.根据权利要求1所述的器件，其中，所述第一高度大于所述第二高度。
3.根据权利要求1所述的器件，其中，所述第一导电部件比所述第二导电部件具有更大的直径，在与所述衬底的主要表面平行的平面中测量所述第一导电部件和所述第二导电部件的直径。
4.根据权利要求1所述的器件，其中，所述非平坦顶面是凸形顶面。
5.根据权利要求1所述的器件，还包括：
介电材料，位于所述钝化膜上方，所述介电材料横向包封所述第一导电部件和包封所述第二导电部件，所述介电材料的顶面与所述第一导电部件的所述平坦顶面共面。
6.根据权利要求5所述的器件，还包括：
第一金属覆盖层，位于所述第一导电部件上，所述第一金属覆盖层的至少部分与所述介电材料的顶面共面，所述第一金属覆盖层的材料组分与所述第一导电部件的材料组分不同；以及
第二金属覆盖层，位于所述第二导电部件上，所述第二金属覆盖层的材料组分与所述第二导电部件的材料组分不同。
7.根据权利要求6所述的器件，其中，所述第一金属覆盖层位于所述第一导电部件的侧壁上，并且所述第二金属覆盖层位于所述第二导电部件的侧壁上。
8.根据权利要求5所述的器件，还包括：
第三导电部件，位于所述介电材料的顶面上方，所述第三导电部件接触所述第一导电部件；以及
第四导电部件，位于与所述第三导电部件处于相同层级的所述介电材料的顶面上方，所述第四导电部件的至少部分与所述第二导电部件重叠，所述第四导电部件与所述第二导电部件电隔离。
9.一种器件，包括：
焊盘，位于半导体衬底上；
共形钝化膜，位于所述半导体衬底上并且覆盖所述焊盘的至少部分；
导电通孔，位于所述焊盘上并且具有从所述焊盘至所述导电通孔的顶面测得的第一高度；
导电线，位于所述共形钝化膜上并且具有从所述共形钝化膜至所述导电线的顶面测得的第二高度，所述第一高度大于所述第二高度；以及
介电材料，位于所述共形钝化膜上方并且具有与所述导电通孔的顶面共面的顶面，所述介电材料包封所述导电线。
10.一种方法，包括：
实施第一形成工艺以在衬底上方形成第一高度的第一导电部件和第二高度的第二导电部件，所述第一高度从所述第一导电部件的底面至所述第一导电部件的顶面测得，并且所述第二高度从所述第二导电部件的底面至所述第二导电部件的顶面测得，所述第一高度大于所属第二高度；以及
以介电材料包封所述第一导电部件的侧壁以及所述第二导电部件的顶面和侧壁，所述第一导电部件的顶面与所述介电材料的顶面共面。
CN201510757656.2A 2015-04-16 2015-11-10 半导体器件及其形成方法 Active CN106057760B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/688,883 2015-04-16
US14/688,883 US10446522B2 (en) 2015-04-16 2015-04-16 Methods of forming multiple conductive features in semiconductor devices in a same formation process

Publications (2)

Publication Number Publication Date
CN106057760A true CN106057760A (zh) 2016-10-26
CN106057760B CN106057760B (zh) 2019-08-30

Family

ID=57129255

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510757656.2A Active CN106057760B (zh) 2015-04-16 2015-11-10 半导体器件及其形成方法

Country Status (4)

Country Link
US (1) US10446522B2 (zh)
KR (1) KR101784570B1 (zh)
CN (1) CN106057760B (zh)
TW (1) TWI667760B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786360A (zh) * 2017-11-15 2019-05-21 台湾积体电路制造股份有限公司 半导体封装件和方法
CN111757590A (zh) * 2019-03-28 2020-10-09 奥特斯奥地利科技与系统技术有限公司 使嵌入的轨道突出直到不同的高度的部件承载件
CN112018061A (zh) * 2019-05-31 2020-12-01 台湾积体电路制造股份有限公司 半导体器件和形成半导体器件方法

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9842831B2 (en) 2015-05-14 2017-12-12 Mediatek Inc. Semiconductor package and fabrication method thereof
US10685943B2 (en) 2015-05-14 2020-06-16 Mediatek Inc. Semiconductor chip package with resilient conductive paste post and fabrication method thereof
US9837359B1 (en) * 2016-09-30 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10037957B2 (en) * 2016-11-14 2018-07-31 Amkor Technology, Inc. Semiconductor device and method of manufacturing thereof
US10186462B2 (en) * 2016-11-29 2019-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10541228B2 (en) 2017-06-15 2020-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Packages formed using RDL-last process
US10658281B2 (en) * 2017-09-29 2020-05-19 Intel Corporation Integrated circuit substrate and method of making
US10283461B1 (en) 2017-11-22 2019-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Info structure and method forming same
US10790161B2 (en) * 2018-03-27 2020-09-29 Amkor Technology, Inc. Electronic device with adaptive vertical interconnect and fabricating method thereof
TWI681528B (zh) * 2018-05-28 2020-01-01 力成科技股份有限公司 重佈線結構及其製造方法
KR102666153B1 (ko) * 2018-06-15 2024-05-17 삼성전자주식회사 반도체 장치
US11942334B2 (en) * 2018-12-21 2024-03-26 Intel Corporation Microelectronic assemblies having conductive structures with different thicknesses
US11387191B2 (en) * 2019-07-18 2022-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11742309B2 (en) * 2020-08-21 2023-08-29 Micron Technology, Inc. Bump coplanarity for semiconductor device assembly and methods of manufacturing the same
US11817361B2 (en) * 2021-02-12 2023-11-14 Taiwan Semiconductor Manufacturing Co., Ltd. Passivation structure with planar top surfaces
CN115513274A (zh) * 2021-06-07 2022-12-23 联华电子股份有限公司 避免翘曲的半导体结构及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020076908A1 (en) * 2000-12-19 2002-06-20 Fujitsu Limited Semiconductor device manufacturing method having a step of forming a post terminal on a wiring by electroless plating
US20030080431A1 (en) * 2001-10-27 2003-05-01 Cyprian Uzoh Method and structure for thru-mask contact electrodeposition
TW201409588A (zh) * 2012-08-31 2014-03-01 Taiwan Semiconductor Mfg 封裝結構
CN104282649A (zh) * 2013-07-03 2015-01-14 台湾积体电路制造股份有限公司 半导体器件及其制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007194436A (ja) 2006-01-19 2007-08-02 Elpida Memory Inc 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法
JP2008211078A (ja) 2007-02-27 2008-09-11 Sharp Corp ドライバｉｃおよび表示パネル
JP4364258B2 (ja) * 2007-05-15 2009-11-11 株式会社東芝 半導体装置及び半導体装置の製造方法
US7880297B2 (en) * 2007-12-31 2011-02-01 Mediatek Inc. Semiconductor chip having conductive member for reducing localized voltage drop
JP5154271B2 (ja) 2008-03-17 2013-02-27 日本特殊陶業株式会社 はんだバンプを有する配線基板及びその製造方法
US8227924B2 (en) * 2010-07-13 2012-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate stand-offs for semiconductor devices
US8450049B2 (en) * 2011-02-10 2013-05-28 Chipbond Technology Corporation Process for forming an anti-oxidant metal layer on an electronic device
US10096540B2 (en) * 2011-05-13 2018-10-09 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming dummy pillars between semiconductor die and substrate for maintaining standoff distance
JP2012256737A (ja) * 2011-06-09 2012-12-27 Sony Corp 半導体装置及び半導体装置の製造方法
US9224643B2 (en) * 2011-09-19 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for tunable interconnect scheme
US9425121B2 (en) 2013-09-11 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure with guiding trenches in buffer layer
US9159671B2 (en) * 2013-11-19 2015-10-13 International Business Machines Corporation Copper wire and dielectric with air gaps

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020076908A1 (en) * 2000-12-19 2002-06-20 Fujitsu Limited Semiconductor device manufacturing method having a step of forming a post terminal on a wiring by electroless plating
US20030080431A1 (en) * 2001-10-27 2003-05-01 Cyprian Uzoh Method and structure for thru-mask contact electrodeposition
US6815354B2 (en) * 2001-10-27 2004-11-09 Nutool, Inc. Method and structure for thru-mask contact electrodeposition
TW201409588A (zh) * 2012-08-31 2014-03-01 Taiwan Semiconductor Mfg 封裝結構
CN104282649A (zh) * 2013-07-03 2015-01-14 台湾积体电路制造股份有限公司 半导体器件及其制造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786360A (zh) * 2017-11-15 2019-05-21 台湾积体电路制造股份有限公司 半导体封装件和方法
US11031342B2 (en) 2017-11-15 2021-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US11948890B2 (en) 2017-11-15 2024-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
CN111757590A (zh) * 2019-03-28 2020-10-09 奥特斯奥地利科技与系统技术有限公司 使嵌入的轨道突出直到不同的高度的部件承载件
CN111757590B (zh) * 2019-03-28 2024-08-16 奥特斯奥地利科技与系统技术有限公司 部件承载件及其制造方法
CN112018061A (zh) * 2019-05-31 2020-12-01 台湾积体电路制造股份有限公司 半导体器件和形成半导体器件方法

Also Published As

Publication number Publication date
TWI667760B (zh) 2019-08-01
CN106057760B (zh) 2019-08-30
TW201639103A (zh) 2016-11-01
US20160307862A1 (en) 2016-10-20
US10446522B2 (en) 2019-10-15
KR101784570B1 (ko) 2017-10-11
KR20160123967A (ko) 2016-10-26

Similar Documents

Publication Publication Date Title
CN106057760A (zh) 半导体器件及其形成方法
US10720409B2 (en) Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
US11417643B2 (en) Package-on-package with redistribution structure
US11195816B2 (en) Integrated circuit packages comprising a plurality of redistribution structures and methods of forming the same
CN109786268B (zh) 半导体封装件中的金属化图案及其形成方法
US11018113B2 (en) Memory module, semiconductor package including the same, and manufacturing method thereof
US9502391B2 (en) Semiconductor package, fabrication method therefor, and package-on package
TWI630664B (zh) 封裝結構及其形成方法
US10269619B2 (en) Wafer level chip scale packaging intermediate structure apparatus and method
US11329008B2 (en) Method for manufacturing semiconductor package for warpage control
CN107689333A (zh) 半导体封装件及其形成方法
TW201739008A (zh) 半導體元件、半導體封裝及其製造方法
TW201727826A (zh) 積體晶片的系統及其形成方法
CN107731786B (zh) 重配置线路结构、封装体及导电特征的制造方法
CN106409810A (zh) 具有堆叠通孔的再分布线
CN111613612A (zh) 包括嵌入式表面贴装器件的半导体封装件及其形成方法
KR20130118757A (ko) 3차원 집적 회로를 제조하는 방법
US12068173B2 (en) Package structure and manufacturing method thereof
US11658097B2 (en) Manufacturing method for semiconductor device including through die hole
TW201906127A (zh) 半導體封裝及其製造方法
TW201820464A (zh) 半導體裝置的製造方法
TWI587464B (zh) 封裝結構及其製造方法
CN109786274A (zh) 半导体器件及其制造方法
US9842827B2 (en) Wafer level system in package (SiP) using a reconstituted wafer and method of making
US10032662B2 (en) Packaged semiconductor devices and packaging methods thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant