CN104282649A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN104282649A
CN104282649A CN201310421738.0A CN201310421738A CN104282649A CN 104282649 A CN104282649 A CN 104282649A CN 201310421738 A CN201310421738 A CN 201310421738A CN 104282649 A CN104282649 A CN 104282649A
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Prior art keywords
stress
buffer layer
moulding compound
conductive plunger
lining
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CN201310421738.0A
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CN104282649B (zh
Inventor
林俊成
洪瑞斌
蔡柏豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了一种半导体器件及其制造方法，其中，扇出型封装件包括模塑料、导电插塞和应力缓冲层。导电插塞位于模塑料中。应力缓冲层位于导电插塞和模塑料之间。应力缓冲层具有热膨胀系数（CTE）。应力缓冲层的CTE介于模塑料的CTE和导电插塞的CTE之间。制造三维半导体封装件的方法包括：在衬底上镀柱形件，并且在柱形件的侧壁上设置应力缓冲层。该方法进一步包括：用模塑料围绕应力缓冲层。

Description

半导体器件及其制造方法
技术领域
本发明涉及一种半导体器件，更具体地，涉及三维集成扇出型封装件。
背景技术
在多种应用中广泛采用半导体器件。随着用户对性能和功能的要求提高，几何尺寸倾向于快速减小。例如，市场中出现的3G移动电话被期望能够进行远程通信、捕捉图像并且处理高流量数据。为了实现这些要求，3G移动电话需要中有限空间中装配有不同器件，诸如处理器、存储器和图像传感器。
将多个半导体器件组合在一个封装件中是通过将具有不同功能的器件集成到单个组件中来增强性能的方法。该领域的蓝图设计示出具有多级结构的三维封装件用于高级和微型尺寸的半导体元件。
三维集成半导体封装件包含多个不同的子结构。子结构以堆叠方式布置，并且相互接触或通过互连件连接。然而，另一方面，子结构的不同特性也向设计者产生了挑战。与二维半导体封装件相比，相对更加复杂的三维集成半导体封装件的故障模式增加。因此，继续寻求对用于三维半导体封装件的结构和方法进行改进。
发明内容
根据本发明的一个方面，提供了一种扇出型封装件，包括：模塑料；导电插塞，位于模塑料中；以及应力缓冲层，位于导电插塞和模塑料之间，应力缓冲层的热膨胀系数（CTE）介于模塑料的CTE和导电插塞的CTE之间。
优选地，应力缓冲层是复合膜。
优选地，复合膜的应力缓冲层的CTE随着远离导电插塞而增加。
优选地，应力缓冲层的厚度介于约0.2μm和约5μm之间。
优选地，导电插塞的顶面位于模塑料的顶面下方。
优选地，导电插塞的一部分接触模塑料。
优选地，该扇出型封装件进一步包括：位于导电插塞上方并且与导电插塞接触的互连件，其中，互连件接触导电插塞的顶面的一部分。
根据本发明的另一方面，提供了一种半导体结构，包括：模塑料；填充通孔，位于模塑料中；以及衬里，位于模塑料和填充通孔之间，衬里是锡、钨、锆、金、钯、聚酰亚胺、ENEPIG、ENEP、或PBO。
优选地，衬里进一步设置在模塑料的底面上。
优选地，衬里的厚度介于约0.2μm和约5μm之间。
优选地，衬里的CTE介于约9ppm和约80ppm之间。
优选地，填充通孔在衬里的顶部拐角处凹进。
优选地，填充通孔的凹槽的形状是环形。
根据本发明的又一方面，提供了一种制造三维半导体封装的方法，包括：在衬底上镀柱形件；在柱形件的侧壁上设置第一应力缓冲层；以及用模塑料围绕第一应力缓冲层。
优选地，设置第一应力缓冲层包括：用第一应力缓冲层覆盖衬底。
优选地，该方法进一步包括：从衬底去除第一应力缓冲层。
优选地，该方法进一步包括：研磨模塑料，以暴露柱形件的顶面。
优选地，该方法进一步包括：去除柱形件的一部分。
优选地，设置第一应力缓冲层包括：在柱形件的侧壁上旋涂或汽相沉积第一应力缓冲层。
优选地，该方法进一步包括：在第一应力缓冲层上形成第二应力缓冲层。
附图说明
当结合附图进行阅读时，根据以下详细描述可以最好地理解本发明的各个方面。应该强调的是，根据工业中的标准实践，各种部件不必按比例绘制。事实上，为了论述的清楚起见，多种部件的尺寸可以任意增大或减小。
图1是三维半导体结构的示意图；
图2是在模塑料200和导电插塞之间具有复合应力缓冲层的3D半导体结构；
图3是包括作为应力缓冲层的衬里的半导体结构；
图4是包括作为应力缓冲层的衬里并且衬里位于模塑料的底面下方的半导体结构；
图5是包括位于导电插塞的顶部拐角上的凹槽的半导体结构；
图6是包括位于导电插塞的顶部拐角上的凹槽的半导体结构；
图7A至图7M是制造三维半导体结构的方法的操作；
图8A至图8D是制造三维半导体结构的方法的操作；以及
图9是根据本发明的集成3D IC封装件600。
具体实施方式
在本发明中，三维（3D）半导体结构被设计成用于防止3D半导体结构中的位置处产生破裂。3D半导体结构提供用于半导体芯片的封装件。半导体芯片被密封在3D半导体结构内，并且通过该结构中的互连件电连接至外部电路。在一些实施例中，3D半导体结构是扇出型封装件。在一些实施例中，3D半导体结构是集成的扇出型叠层封装（POP）器件。
由两个以上不同的子结构组成3D半导体结构。在一些实施例中，子结构是电介质、模塑料、电互连件、填充的通孔或插塞、以及接触焊盘。在一些实施例中，电介质设置在两个导电层之间并且通过诸如环氧树脂、聚酰亚胺、聚苯并恶唑（PBO）等的聚合物材料形成。在一些实施例中，电介质设置在置于3D半导体结构中的半导体芯片上。电介质还可以包括旋涂玻璃（SOG）、氧化硅、氮氧化硅等，并且可以通过诸如旋涂或汽相沉积的任何合适的方法形成。
模塑料是化合物并且由包括环氧树脂、酚类固化剂、硅石、催化剂、颜料和脱模剂的复合材料形成。用于形成模塑料的材料具有高热导率、低吸湿率、板安装温度下的高抗弯强度、或这些的结合。
电互连件是布置在3D半导体结构内的导电线或者膜。在一些实施例中，电互连件是重分布层（RDL）。RDL用于扇入或扇出工艺。在一些实施例中，通过诸如金、银、铜、镍、钨、铝和/或它们的合金的导电材料形成电互连件。
在一些实施例中，本发明中的填充通孔或导电插塞是导电柱。填充通孔或插塞具有导电性，并且设置在诸如载体、衬底或模塑料的子结构中。导电填充通孔或插塞被配置为延伸穿过子结构，并且在子结构的顶面和底表面之间提供电通信。
在一些实施例中，接触焊盘设置在3D半导体结构的顶面上。接触焊盘的顶面接收焊球或焊膏，并且用作将3D半导体结构连接到外部电路的端子。接触焊盘的底表面连接至诸如RDL的互连件。在一些实施例中，接触焊盘是凸块下金属化层（UBM）。将焊球或焊膏放置在UBM的顶面上，使得3D结构可以电连接至外部器件。在一些实施例中，通过诸如金、银、铜、镍、钨、铝和/或它们的合金的导电材料形成UBM。
在一些实施例中，3D半导体结构具有设置在半导体芯片上的导电柱。半导体芯片被放置在3D半导体结构中。导电柱的一端与半导体的接合焊盘电连接。导电柱的另一端与诸如RDL的互连件电连接。在一些实施例中，导电柱是导电凸块。由诸如金、银、铜、镍、钨、铝、锡和/或它们的合金的导电材料形成导电柱。可以通过诸如蒸发、电镀、汽相沉积、溅射或丝网印刷的工艺形成导电柱。
在一些实施例中，使用晶圆级封装（WSP）操作制造3D半导体结构。在一些实施例中，使用芯片级封装操作制造3D半导体结构。在一些实施例中，使用倒装芯片操作制造3D半导体结构。
3D半导体结构具有设置在两个不同的子结构之间的层。该层是应力缓冲层（stress buffer），还被称为衬里。应力缓冲层或衬里被设计成避免由内部应力所引起的破裂。在一些实施例中，内部应力来源于两个不同子结构之间的热膨胀的差。热膨胀差是因为两个不同子结构之间的子结构材料的热膨胀系数（CTE）不同而引起的。
本发明中的术语“CTE”是物体被加热或冷却时的特性。物体的长度变化量与原始长度和温度的变化成正比。CTE的单位是ppm/K，其代表10-6m/mK。下文中，将CTE单位缩写为“ppm”。在本公开中，纯铜的CTE是16.6ppm，并且纯硅的CTE是3ppm。根据材料中杂质的浓度，每种材料的CTE可以在一个范围中。对于模塑料材料，CTE取决于模塑料的组成，并且可以是达到上百ppm的宽范围。
在一些实施例中，3D半导体结构具有位于至少两个子结构之间的应力缓冲层或衬里。应力缓冲层或衬里具有在一个子结构的CTE和另一个子结构的CTE之间的CTE。可以通过导电或电绝缘材料形成应力缓冲层或衬里。在本发明中，应力缓冲层或衬里是但不限于浸镀锡、化学镀镍钯浸金（ENEPIG）、化学镀镍化学镀钯（ENEP）、聚苯并噁唑（PBO）、聚酰亚胺等。在一些实施例中，应力缓冲层或衬里是包括至少两个不同膜的复合膜。
图1是3D半导体结构12。3D半导体结构12具有半导体芯片100。半导体芯片100位于结构12的底部。在特定实施例中，半导体芯片100位于管芯附着膜（DAF）上。半导体结构12是半导体芯片100的封装件。半导体芯片100具有正面和背面。半导体芯片100的接合焊盘154设置在正面上。在一些实施例中，半导体的背面与散热层、粘附层或缓冲层接合。半导体芯片100在正面上具有围绕接合焊盘154的钝化层152。由诸如旋涂玻璃（SOG）、氧化硅、氮氧化硅、氮化硅等的介电材料形成钝化层152。钝化层152向半导体芯片100提供电隔离和防潮。由汽相沉积或旋涂工艺形成钝化层。
形成围绕半导体芯片100侧壁的模塑料200。模塑料200具有顶面202和底面204。在一些实施例中，底面204和半导体芯片100的背面形成半导体结构12的表面。对于在半导体芯片下方具有DAF的实施例，底面204和DAF形成半导体结构12的表面。模塑料200可以是单层膜或复合膜堆叠件。对于特定实施例，3D半导体结构12具有位于半导体芯片100和模塑料200下方的基底缓冲层。
3D半导体结构12具有位于模塑料200中的导电填充通孔或插塞300。在一些实施例中，导电填充通孔或插塞300从模塑料200的顶面202延伸至模塑料200的底面204。导电填充通孔或插塞300在导电填充通孔或插塞300的一端处与互连件472连接。对于导电填充通孔或插塞300的另一端，导电填充通孔或插塞300可用作用于将3D半导体结构12与位于3D半导体结构的背面处的外部电路电连接的端子。在特定实施例中，填充通孔30的一端连接至覆盖物40，而另一端与位于缓冲层处的外部电路连接。缓冲层设置在半导体结构12的底面上。
导电柱410设置在接合焊盘154的顶面上。导电柱410的一端电连接至半导体芯片100的接合焊盘154。导电柱410的另一端与互连件471电连接。第一电介质501设置在半导体芯片100上。导电柱410被第一电介质501围绕。在一些实施例中，第一电介质501是位于钝化层152和第一电介质501上方的其他介电层之间的缓冲层。
诸如471和472的互连件包括在半导体结构12中。相同附图中用相同数字标记的互连件形成在相同的操作期间。互连件471和472是针对半导体芯片100和外部电路和/或半导体芯片100和外部电路之间的电连接件。在图1中，第一电介质501上的互连件471在一端处与导电柱410电连接。互连471在另一端处与互连件472电连接。对于如图1的特定实施例，互连件471和472具有晶种层475。
UBM480位于半导体结构12的顶面上。UBM480具有与RDL472连接的底部。UBM480具有容纳焊球或焊膏的顶面482。
在图1中，3D半导体结构12具有第二电介质502和第三电介质503。第二电介质502位于电介质501、导电填充通孔或插塞300以及模塑料200上。第二电介质502提供RDL471和RDL472之间的隔离。第二电介质502具有被互连件472和第三电介质503填充的穿通结构。RDL472在通孔512中与RDL471电连接。第三电介质503形成在第二电介质502和RDL472上。第三电介质503防止RDL472暴露于环境条件。第三电介质503具有被UBM480填充的穿通结构513。UBM480形成在穿通结构513中，并且与RDL472电连接。
3D半导体结构12具有插入在模塑料200和导电插塞300之间的衬里50。衬里50用作模塑料200和导电填充通孔或插塞300之间的应力缓冲层。衬里50具有介于模塑料200和导电插塞300的CTE之间的CTE。当对3D半导体结构12施加热处理（加热或冷却）时，模塑料200的尺寸变化大于导电插塞300的尺寸变化。例如，在一些实施例中，3D半导体结构具有由CTE为55ppm的环氧树脂形成的模塑料以及由CTE为16ppm的铜形成的导电插塞。模塑料和导电填充通孔或插塞之间的大CTE失配（超过3倍）在半导体结构中，特别是在模塑料和导电插塞之间的界面处，产生内部应力。通过在模塑料和导电插塞之间设置应力缓冲层（诸如锡，其CTE约为23.4ppm），减小了界面上的CTE梯度。因为应力缓冲层的CTE在模塑料和导电插塞的CTE之间，所以应力缓冲层的尺寸变化在模塑料和导电插塞的尺寸变化之间。因为相邻膜之间的CTE失配减小，所以内部应力减小。在一些实施例中，应力缓冲层的CTE介于约9ppm和约90ppm之间。在一些实施例中，应力缓冲层的CTE介于约25ppm和约70ppm之间。
在一些实施例中，作为模塑料和导电填充通孔或插塞之间的应力缓冲层的衬里是复合膜。复合应力缓冲层具有两个以上的应力缓冲层。在一些实施例中，在所有的应力缓冲层中，最接近导电填充通孔或插塞设置的应力缓冲层具有最小的CTE。在图2中，3D半导体结构12具有位于模塑料200和导电插塞300之间的复合应力缓冲层。复合应力缓冲层具有第一应力缓冲层51和第二应力缓冲层52。第二应力缓冲层52位于模塑料200和第一应力缓冲层51之间。第一应力缓冲层51位于第二应力缓冲层52和导电插塞300之间。第二应力缓冲层52具有介于模塑料200的CTE和第一应力缓冲层51的CTE之间的CTE。第一应力缓冲层51具有介于第二应力缓冲层52和导电填充通孔或插塞300的CTE之间的CTE。
在一些实施例中，第二应力缓冲层52是CTE约为37ppm的碲。第一应力缓冲层51是CTE约为22.5ppm的锶。在一些实施例中，第一应力缓冲层是镍，并且第二应力缓冲层是浸金、钯、或它们的组合。模塑料200是CTE约为75ppm的环氧树脂，并且导电插塞300是CTE约为16.6ppm的铜。通过设计复合应力缓冲层，进一步降低了模塑料200和导电插塞300之间的CTE变化的梯度。在一些实施例中，复合应力缓冲层在模塑料和导电插塞之间具有两个以上的不同应力缓冲层，以改变从模塑料至导电填充通孔或插塞的CTE的梯度。
在一些实施例中，3D半导体结构具有复合应力缓冲层，并且复合应力缓冲层具有由导电材料形成的一个应力缓冲层和由电绝缘材料形成的另一个应力缓冲层。例如，在一些实施例中，复合应力缓冲层具有由聚丙烯形成的应力缓冲层和由银制成的另一个应力缓冲层。在特定的一些实施例中，3D半导体结构具有复合应力缓冲层，并且复合应力缓冲层的所有应力缓冲层均由电绝缘材料形成。
在一些实施例中，设置在模塑料和导电插塞之间的衬里或应力缓冲层不是连续层。衬里或应力缓冲层可以具有多个分离部分。在图3中，3D半导体结构12具有模塑料200、导电插塞300和衬里50。衬里50位于模塑料200和导电插塞300之间。衬里50具有用于每一侧的两个分离部分。在一些实施例中，衬里50具有延伸至模塑料200的顶面202的至少一部分。在一些实施例中，衬里具有用于每一侧的至少三个分离部分。
在各个实施例中，衬里或应力缓冲层设置在模塑料和导电插塞之间。衬里或应力缓冲层不覆盖模塑料和导电插塞之间的部分界面。从而，导电插塞的一部分与模塑料接触。
在一些实施例中，作为应力缓冲层的衬里进一步设置在模塑料的底面上。在图4中，衬里50位于模塑料200和导电插塞300之间。衬里50进一步设置在模塑料200的底面204和管芯100的底部上。在特定实施例中，衬里50设置在DAF的背面上。在又一些其他实施例中，衬里50设置在基底缓冲层上。基底缓冲层设置在模塑料的背面和DAF的背面上。
在一些实施例中，衬里或应力缓冲层的厚度介于约0.2μm和约5μm之间。在一些实施例中，衬里或应力缓冲层的厚度介于约1μm和4μm之间。在一些实施例中，衬里或应力缓冲层的厚度介于1.5μm和3.5μm之间。
对于如图5的一些实施例，3D半导体结构12具有位于模塑料200和导电填充通孔或插塞300之间的应力缓冲层50。导电通孔或插塞300的顶面凹进在模塑料200的顶面下方。导电通孔或插塞300的顶面位于模塑料200的顶面下方。在特定实施例中，导电填充通孔或插塞300具有围绕导电填充通孔或插塞300的顶部拐角的凹进顶面310。由第二电介质502填充凹进顶面310。在一些实施例中，从俯视图看，凹进顶面310的形状为环形。在特定实施例中，衬里或应力缓冲层50的顶面与模塑料200的顶面共面。在特定实施例中，衬里或应力缓冲层50的顶面与导电插塞300的凹进顶面的顶面共面。在特定实施例中，衬里或应力缓冲层50的顶面位于模塑料200的顶面和导电插塞的凹进顶面之间。在如图5的特定实施例中，导电柱410的顶面凹进。导电柱410的顶面低于第一电介质501的顶面。
对于如图6的一些实施例，3D半导体结构12具有位于模塑料200和导电填充通孔或插塞300之间的衬里或应力缓冲层50。半导体管芯100放置在3D半导体结构12的底部。衬里或应力缓冲层50进一步设置在模塑料200的底面和半导体管芯100的底部上。导电通孔或插塞300的顶面凹进在模塑料200的顶面下方。导电通孔或插塞300的顶面位于模塑料200的顶面下方。导电插塞300具有围绕导电插塞300的顶部拐角的凹进顶面310。由第二电介质502填充凹进顶面310。在一些实施例中，从俯视图看，凹进顶面310的形状是环形。在特定实施例中，衬里或应力缓冲层50的顶面与模塑料200的顶面202共面。在特定实施例中，衬里或应力缓冲层50的顶面与导电插塞300的凹进顶面的顶面共面。在特定实施例中，衬里或应力缓冲层50的顶面位于模塑料200的顶面和导电插塞300的凹进顶面之间。
在制造3D半导体结构和半导体结构的方法中，在两个不同的子结构之间设计作为应力缓冲层的衬里。该方法包括多个操作，而描述和说明不被认为是对操作顺序的限制。
在本发明中使用术语“图案化”或“被图案化的”，以描述在表面上形成预定图案的操作。图案化操作包括多个步骤和工艺，并且根据实施例的特征而改变。在一些实施例中，采用图案化操作来图案化已有的膜或层。图案化操作包括：在已有的膜或层上形成掩膜，并且通过蚀刻或其他去除工艺来去除未被掩蔽的膜或层。掩膜是光刻胶、或硬掩膜。在一些实施例中，采用图案化操作在表面上直接形成图案化层。图案化操作包括：在表面上形成感光膜，进行光刻工艺和显影工艺。保留剩余的感光膜并且将其集成到3D半导体结构中。
在本发明中使用术语“镀”或“镀后的”，以描述在表面上形成膜或层的操作。镀操作包括多个步骤和工艺，并且根据实施例的特征而改变。已镀在表面上的膜或层是单层膜或复合堆叠件。在一些实施例中，采用镀操作形成金属膜。在一些实施例中，镀操作包括形成晶种层，并且在晶种层上镀金属膜。在一些实施例中，镀操作是汽相沉积工艺。在一些实施例中，镀操作是溅射工艺。
在本发明中使用术语“填充”或“填充后的”，以描述在孔中形成材料的操作。填充操作包括多个步骤和工艺，并且根据实施例的特征而改变。在一些实施例中，填充操作包括在孔中形成导电材料。在一些实施例中，填充操作包括在通孔的侧壁上形成衬里，并且在衬里上形成导电膜。在一些实施例中，填充操作包括镀工艺。在一些实施例中，填充操作包括汽相沉积工艺。在一些实施例中，填充操作包括溅射工艺。
在图7A中，提供载体700，以在其上形成3D半导体结构。载体700是被设计成在其上形成3D半导体结构的衬底。载体的形状可以根据设计而不同。在一些实施例中，载体的形状是圆形。在一些实施例中，载体是硅或氧化硅。在一些实施例中，在形成3D半导体结构之后，去除载体。对于如图7A的一些实施例，粘合层702设置在载体700上。粘合层702用作将膜或结构粘合至载体700上的可拆卸粘结层。可以通过分解粘合层702，从附着在其上的结构中去除载体700。基底缓冲层704设置在粘合层702上。通过诸如聚酰亚胺、PBO、SR、LTHC（光热转化膜）、晶圆背面涂布带、以及ABF等的材料形成基底缓冲层704。在一些实施例中，基底缓冲层704包括具有不同材料的至少两层。
在图7B中，在载体700的顶面上方形成晶种层705。晶种层705是单层或复合堆叠件，并且由诸如铜、钽、锡、钛/铜、锡/铜、钽/铜等的材料形成。晶种层705提供生长点以促进电镀操作。在一些实施例中，采用溅射或汽相沉积工艺以在载体700上方形成晶种层。
图7C是在晶种层705上形成图案化层708的操作。在一些实施例中，由诸如聚酰亚胺的光刻胶通过旋涂工艺形成图案化层708。图案化层708具有两个以上穿通结构718。
在图7D中，由导电材料710填充穿通结构718。可以采用电镀或溅射工艺在穿通结构中形成导电材料。
图7E是从晶种层705的顶面剥离图案化层的操作。剥离操作是在不破坏导电材料的情况下仅去除图案化层的选择性清洁工艺。在剥离操作之后，保留柱状导电材料710。图7F是去除位于导电柱之间的晶种层并且仅保留导电柱下方的那部分的操作。在一些实施例中，晶种层是金属；去除导电插塞之间的晶种层可以防止导电插塞之间的电通信。保留的晶种层和导电柱在基底缓冲层704上形成多个导电插塞300。
图7G是在导电插塞300和基底缓冲层704上形成衬里或应力缓冲层50的操作。衬里或应力缓冲层50是应力缓冲层。在一些实施例中，通过化学镀工艺形成衬里或应力缓冲层50。在化学镀衬里或应力缓冲层50之前，在导电插塞300和基底缓冲层704上形成金属层。在一些实施例中，金属层是锡。在一些实施例中，通过汽相沉积工艺形成衬里或应力缓冲层50。在一些实施例中，衬里或应力缓冲层50是聚合物。对于一些实施例，采用旋涂以在导电插塞上形成衬里。采用诸如旋涂玻璃或聚酰亚胺的材料形成衬里。
在一些实施例中，衬里被设计成包括至少两层不同膜的应力缓冲层。如图7H所示，衬里是包括第一应力缓冲层51和第二应力缓冲层52的复合膜。第一应力缓冲层51设置在导电插塞300和基底缓冲层704的顶面上。第二应力缓冲层52设置在第一应力缓冲层51上。在一些实施例中，由不同工艺形成每一个应力缓冲层。例如，通过在导电插塞和基底缓冲层上化学镀锡层来形成第一应力缓冲层。通过在第一应力缓冲层上旋涂PBO层来形成第二应力缓冲层。在一些实施例中，在相同工艺中形成第一应力缓冲层和第二应力缓冲层。例如，通过汽相沉积形成第一应力缓冲层和第二应力缓冲层。通过在导电插塞和基底缓冲层上设置钛来形成第一应力缓冲层。通过在第一应力缓冲层上设置氮化钛形成第二应力缓冲层。在一些实施例中，设计原位方法以在相同的制造设备上形成两个不同的缓冲层。
对于具有导电衬里或应力缓冲层的实施例，额外的去除操作是必须的，以防止导电插塞之间的短路。例如，如果衬里是锡膜，则引入如图7I中的操作，以去除设置在导电插塞300之间的衬里或应力缓冲层的一部分。该操作包括在去除一部分衬里50之前掩蔽导电插塞300的步骤。对于具有诸如PBO衬里的电绝缘衬里的实施例，如图7I中的去除操作是可选的。
对于特定实施例，在载体700上没有设置晶种层的情况下，在导电插塞300上形成衬里或应力缓冲层。通过化学镀在导电插塞300上形成衬里或应力缓冲层。在导电插塞300上选择性地形成衬里或应力缓冲层。从而，跳过如图7I中的去除操作。
在图7J中，半导体芯片100被放置在载体700上并且位于导电插塞300之间。对于特定实施例，管芯附着膜（DAF）设置在半导体芯片100和基底缓冲层704之间。第一电介质501覆盖半导体芯片100。在半导体芯片100上设置导电柱410，以与互连件电通信。在一些实施例中，在将半导体芯片放置在载体700上之后，在半导体芯片100上形成第一电介质501。在一些实施例中，在将芯片100放置在载体700上之前，在半导体芯片100上预先形成第一电介质501。
图7K是将模塑料设置在载体上的操作。模塑料200通过涂覆、注入、或压缩形成，并且被放在载体700上。模塑料200还覆盖导电插塞300。对于一些实施例，如果导电插塞具有小间距，则选择液体模塑料（LMC）以将其填充在小间隙中。在形成模塑料之后，可以实施固化工艺，以使模塑料变硬。
制造3D半导体结构的方法包括如图7L中的研磨工艺，以暴露导电柱410。研磨工艺是毯式去除工艺，从而使模塑料200、导电插塞300被放置在与导电柱410相平齐的平面上。
在一些实施例中，用柔软材料而不是模塑料200制造导电插塞300。被去除的导电填充通孔或插塞材料的碎片陷入模塑料200中。采用清洁操作以选择性地去除特定量的导电插塞，以确保没有导电残留物嵌入模塑料200中。如图7M所示，导电填充通孔或插塞300具有凹进顶面，其在模塑料200的顶面下方。
图8A是根据本发明的3D半导体结构。3D半导体结构具有多个导电填充通孔或插塞300，并且每一个导电插塞都具有凹进顶面。在模塑料200和第一电介质501上形成第二电介质502。第二电介质502还填充在导电插塞300的凹槽中。在一些实施例中，由与第一电介质501相同的材料形成第二电介质502。在一些实施例中，第二电介质502的材料与第一电介质501的材料不同。
在图8B中，第二电介质502被图案化，以具有多个穿通结构512。在穿通结构512的底部开口处暴露导电填充通孔或插塞300的顶面。在图8C中，在第二电介质502、导电填充通孔或插塞300上以及穿通结构512中形成导电膜725。导电插塞300包括位于导电插塞300的顶部拐角处的凹槽310。由第二电介质502填充凹槽310。凹槽310具有环形形状。
如图8D所示，导电膜被图案化为RDL571，。在一些实施例中，3D半导体结构包括分布在不同层中的RDL。
图9是集成3D IC封装件600。集成3D IC封装件600包括如图1中的3D半导体结构12和存储芯片11。3D半导体结构12具有衬里或应力缓冲层50。存储芯片11与3D半导体结构12电连接。
扇出型封装件包括模塑料、导电插塞和应力缓冲层。导电插塞位于模塑料中。应力缓冲层位于导电插塞和模塑料之间。应力缓冲层具有热膨胀系数（CTE）。应力缓冲层的CTE介于模塑料的CTE和导电插塞的CTE之间。制造三维半导体封装件的方法包括：在衬底上镀柱形件，并且在柱形件的侧壁上设置应力缓冲层。该方法进一步包括：用模塑料围绕应力缓冲层。
半导体结构包括模塑料、填充通孔和衬里。填充通孔位于模塑料中。衬里位于模塑料和填充通孔之间。衬里是锡、钨、锆、金、钯、聚酰亚胺、ENEPIG、ENEP、或PBO。
制造三维半导体封装件的方法。该制造方法包括：在衬底上镀柱形件，并且在柱的侧壁上设置应力缓冲层。该方法进一步包括：用模塑料围绕应力缓冲层。
在以上实例和说明中已经充分描述了本发明的方法和特征。应该理解，在不脱离本发明的精神内的任何修改或变化都旨在包含在本发明的保护范围内。

Claims (10)

1.一种扇出型封装件，包括：
模塑料；
导电插塞，位于所述模塑料中；以及
应力缓冲层，位于所述导电插塞和所述模塑料之间，所述应力缓冲层的热膨胀系数（CTE）介于所述模塑料的CTE和所述导电插塞的CTE之间。
2.根据权利要求1所述的扇出型封装件，其中，所述应力缓冲层是复合膜。
3.根据权利要求2所述的扇出型封装件，其中，所述复合膜的应力缓冲层的CTE随着远离所述导电插塞而增加。
4.根据权利要求3所述的扇出型封装件，其中，所述应力缓冲层的厚度介于约0.2μm和约5μm之间。
5.根据权利要求1所述的扇出型封装件，其中，所述导电插塞的顶面位于所述模塑料的顶面下方。
6.根据权利要求1所述的扇出型封装件，其中，所述导电插塞的一部分接触所述模塑料。
7.根据权利要求1所述的扇出型封装件，进一步包括：位于所述导电插塞上方并且与所述导电插塞接触的互连件，其中，所述互连件接触所述导电插塞的所述顶面的一部分。
8.一种半导体结构，包括：
模塑料；
填充通孔，位于所述模塑料中；以及
衬里，位于所述模塑料和所述填充通孔之间，所述衬里是锡、钨、锆、金、钯、聚酰亚胺、ENEPIG、ENEP、或PBO。
9.根据权利要求8所述的半导体结构，其中，所述衬里进一步设置在所述模塑料的底面上。
10.一种制造三维半导体封装的方法，包括：
在衬底上镀柱形件；
在所述柱形件的侧壁上设置第一应力缓冲层；以及
用模塑料围绕所述第一应力缓冲层。
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