CN106373930A - 晶圆级封装件及其形成方法 - Google Patents

晶圆级封装件及其形成方法 Download PDF

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Publication number
CN106373930A
CN106373930A CN201610549737.8A CN201610549737A CN106373930A CN 106373930 A CN106373930 A CN 106373930A CN 201610549737 A CN201610549737 A CN 201610549737A CN 106373930 A CN106373930 A CN 106373930A
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layer
damp
semiconductor device
proof layer
device structure
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CN201610549737.8A
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CN106373930B (zh
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郑心圃
刘献文
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种半导体器件结构及其形成方法。该半导体器件结构包括衬底和形成在衬底上的导电焊盘。该半导体器件结构包括形成在所述导电焊盘的上方的保护层和至少形成在所述保护层内的钝化后互连(PPI)结构。PPI结构电连接至所述导电焊盘。该半导体器件结构还包括形成在所述保护层的上方的第一防潮层，并且所述保护层和所述第一防潮层由不同的材料制成。该半导体器件结构还包括形成在所述第一防潮层上方并且连接至所述PPI结构的凸块下金属(UBM)层。

Description

晶圆级封装件及其形成方法
相关申请的交叉引用
本申请要求于2015年6月20提交的、标题为“wafer level package(wlp)andmethod for forming the same”的权益，其全部内容结合于此作为参考。
技术领域
本发明总体涉及半导体领域，更具体地，涉及晶圆级封装件及其形成方法。
背景技术
半导体器件用于诸如个人电脑、手机、数码相机和其他电子设备的种电子应用中。半导体器件通常通过以下步骤制造：在半导体衬底上方顺序沉积绝缘或介电层、导电层和半导体材料层；利用光刻来图案化各种材料层以在衬底上形成电路部件和元件。许多集成电路通常制造在单个半导体晶圆上，并且通过在集成电路之间沿着划线切割而分隔晶圆上的独立管芯。独立管芯通常以多芯片模块或其他类型的封装来单独封装。
晶圆级封装(WLP)结构用作电子产品的半导体部件的封装结构。输入-输出(I/O)电接触件的数目的增多以及对高性能的需求的增大已导致扇出型WLP结构，该结构使得用于I/O电接触件的凸块之间的节距加大。
尽管现有的WLP结构和制造晶圆级封装的方法通常对于其预期的目的是能够胜任的，但是它们不是在所有方面都完全令人满意。
发明内容
根据本发明的一个方面，提供了一种半导体器件结构，包括：衬底；导电焊盘，形成在所述衬底上；保护层，形成在所述导电焊盘的上方；钝化后互连(PPI)结构，至少形成在所述保护层内，其中，所述钝化后互连结构电连接至所述导电焊盘；第一防潮层，形成在所述保护层的上方，其中，所述保护层和所述第一防潮层由不同的材料制成；以及凸块下金属(UBM)层，形成在所述第一防潮层上方并且连接至所述钝化后互连结构。
优选地，所述第一防潮层包括聚酰亚胺(PI)、环氧树脂、阻焊剂(SR)、氮化硅、氧化硅、六甲基二硅氮烷(HMDS)、含氟聚合物或它们的组合。
优选地，所述保护层由聚苯并恶唑(PBO)制成，并且所述第一防潮层由聚酰亚胺(PI)制成，其中，所述聚酰亚胺(PI)包括在约10wt％至约40wt％范围内的交联。
优选地，该半导体器件结构还包括：第二防潮层，形成在所述第一防潮层的上方并且邻近于所述凸块下金属层。
优选地，所述第二防潮层由含氟聚合物制成，所述含氟聚合物包括在约30wt％至约60wt％范围内的碳-氟键合物。
优选地，该半导体器件结构还包括：导电结构，形成在所述凸块下金属层的上方，其中，所述导电结构通过所述凸块下金属层电连接至所述钝化后互连结构。
优选地，该半导体器件结构还包括：封装结构，形成在所述导电结构上方，其中，所述导电结构电连接至所述封装结构的导电焊盘。
优选地，该半导体器件结构还包括：钝化层，形成在所述导电焊盘和所述钝化后互连结构之间，其中，所述钝化层和所述第一防潮层由相同材料制成。
根据本发明的另一方面，提供了一种半导体器件结构，包括：导电焊盘，形成在芯片上方；绝缘层，包围所述芯片；保护层，形成在所述导电焊盘和所述绝缘层的上方；钝化后互连(PPI)结构，至少形成在所述保护层内，其中，所述钝化后互连结构电连接至所述导电焊盘；第一防潮层，形成在所述保护层的上方，其中，所述第一防潮层包括聚酰亚胺(PI)、环氧树脂、阻焊剂(SR)、氮化硅、氧化硅、六甲基二硅氮烷(HMDS)、含氟聚合物或它们的组合；以及凸块下金属(UBM)层，形成在所述第一防潮层的上方。
优选地，该半导体器件结构还包括：钝化层，形成在所述芯片和所述保护层之间，其中，所述钝化层和所述第一防潮层由相同的材料制成。
优选地，所述阻焊剂(SR)包括在约10wt％至约30wt％范围内的硅酸盐填料。
优选地，所述环氧树脂包括在约60wt％至约90wt％范围内的酚醛树脂或丙烯酸树脂。
优选地，该半导体器件结构还包括：第一导电结构，形成在所述凸块下金属层上；以及第一封装结构，形成在所述第一导电结构上方。
优选地，该半导体器件结构还包括：导电柱状结构，穿过所述绝缘层而形成，其中，所述导电柱状结构包括邻近于所述钝化后互连结构的第一表面和与所述第一表面相对的第二表面；以及导电层，形成在所述导电柱状结构的第二表面上方。
优选地，半导体器件结构，还包括：第二导电结构，形成在所述导电层的上方；以及第二封装结构，形成在所述第二导电结构上方。
优选地，该半导体器件结构还包括：第二防潮层，形成在所述第一防潮层的上方，其中，所述第二防潮层邻近于所述凸块下金属层。
根据本发明的又一方面，提供了一种用于形成半导体器件结构的方法，包括：在衬底上方形成导电焊盘；在所述导电焊盘上方形成保护层；在所述保护层内形成钝化后互连(PPI)结构，其中，所述钝化后互连结构电连接至所述导电焊盘；在所述保护层的上方形成第一防潮层，其中，所述保护层和所述第一防潮层由不同的材料制成；以及在所述第一防潮层内形成凸块下金属(UBM)层。
优选地，该方法还包括：邻近于所述凸块下金属层形成第二防潮层，其中，所述第二防潮层由含氟的聚合物制成。
优选地，该方法还包括：在所述凸块下金属层的上方形成导电结构；以及在所述导电结构上方形成封装结构，其中，所述封装结构电连接至所述导电结构。
优选地，该方法还包括：在所述导电焊盘和所述衬底之间形成芯片结构；形成包围所述芯片的绝缘层；以及形成穿过所述绝缘层并且邻近于所述芯片结构的导电柱状结构。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1A至图1F示出了根据本发明的一些实施例的代表半导体器件结构不同形成阶段的截面图。
图1F’示出了根据本发明的一些实施例的半导体器件结构的经过修改的实施例。
图2A示出了根据本发明的一些实施例的代表半导体器件结构的截面图。
图2B示出了根据本发明的一些实施例的半导体器件结构的经过修改的实施例。
图3A至图3D示出了根据本发明的一些实施例的代表半导体器件结构不同形成阶段的截面图。
图3D’示出了根据本发明的一些实施例的半导体器件结构的经过修改的实施例。
图4A示出了根据本发明的一些实施例的代表半导体器件结构的截面图。
图4B示出了根据本发明的一些实施例的代表半导体器件结构的截面图。
图5A至图5C示出了根据本发明的一些实施例的代表半导体器件结构不同形成阶段的截面图。
图5B’示出了根据本发明的一些实施例的代表半导体器件结构的截面图。
图6A至图6C示出了根据本发明的一些实施例的代表半导体器件结构不同形成阶段的截面图。
图6B’示出了根据本发明的一些实施例的代表半导体器件结构的截面图。
图7A至图7C示出了根据本发明的一些实施例的代表半导体器件结构不同形成阶段的截面图。
图7B’示出了根据本发明的一些实施例的代表半导体器件结构的截面图。
具体实施方式
以下公开内容提供了许多不同实施例或实例，用于实现所提供主题的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附件部件使得第一部件和第二部件不直接接触的实施例。另外，本发明可以在多个实例中重复参考标号和/或字母。这种重复是为了简化和清楚的目的，但其本身并不指示所讨论的各个实施例和/或配置之间的关系。
描述了实施例的变形。通过不同的视图和说明性的实施例，类似的标号用于表示类似的部件。应理解，可在所述方法之前、期间和之后提供附加的操作，并且所述的一些操作可被替换或消除以作为该方法的其他实施例。
提供了半导体结构及其形成方法的实施例。图1A至图1F示出了根据本发明的一些实施例的形成半导体器件100a的不同阶段的截面图。这些半导体器件结构100a应用于晶圆级封装(WLP)。
参考图1A，提供衬底102。衬底102可由硅或其他半导体材料制成。可选或附加的，衬底102可包括诸如锗的其他元素半导体材料。在一些实施例中，衬底102由诸如碳化硅、砷化镓、砷化铟或磷化铟的化合物半导体制成。在一些实施例中，衬底102由合金半导体(诸如，硅锗、碳化硅锗、磷砷化镓或磷铟化镓)制成。在一些实施例中，衬底102包括外延层。例如，衬底102具有上覆块状半导体上的外延层。
半导体器件结构100a还包括位于衬底上方的层间介电(ILD)层110。ILD层110由氧化硅(SiOx)、氮化硅(SixNy)或氮氧化硅(SiON)制成。
器件元件104形成在ILD层110内。器件元件104包括晶体管(例如，金属氧化物场效应晶体管(MOSFET)、互补金属氧化物(CMOS)晶体管、双极结晶体管(BJT)、高压晶体管、高频晶体管、p沟道和/或n沟道场效应晶体管(PFET)等)、二极管和/或其他可用的元件。执行各种工艺(诸如，沉积、蚀刻、注入、光刻、退火和/或其他可用的工艺)以形成器件元件104。在一些实施例中，在前端制程(FEOL)工艺中，在衬底102内形成器件元件104。
衬底102可包括各种掺杂区域，诸如p型阱或n型阱。掺杂区域可掺有p型掺杂剂(诸如，硼或BF2)和/或n型掺杂剂(诸如，磷(P)或砷(As))。掺杂区域可以P阱结构、N阱结构或双阱结构直接形成在衬底102上。
衬底102还可包括隔离部件(未示出)，诸如浅沟槽隔离(STI)部件或局部硅氧化(LOCOS)部件。隔离部件可限定和隔离各种器件元件。
金属间介电层(IMD)120形成在ILD层110上方。IMD层120由氧化硅(SiOx)、氮化硅(SixNy)或氮氧化硅(SiON)、具有低介电常数(低k)的介电材料或它们的组合。在一些实施例中，IMD层120由介电常数小于约2.5的极低k(ELK)介电材料制成。在一些实施例中，ELK介电材料包括掺碳的氧化硅、非晶氟化碳、聚对二甲苯、苯并环丁烯(BCB)、聚四氟乙烯(PTFE)(特氟龙)或碳氧化硅(SiOC)。在一些实施例中，ELK介电材料包括现有介电材料的多孔形式(version)，诸如氢硅倍半氧烷(HSQ)、多孔甲基硅氧烷(MSQ)、多孔聚芳醚(PAE)、多孔SiLK或多孔氧化硅(SiO2)。在一些实施例中，通过等离子体增强化学汽相沉积(PECVD)工艺或旋涂工艺来沉积IMD层120。
导电焊盘131形成在IMD层120上方。导电焊盘通过IMD层120内的金属线和通孔电连接至器件元件104。
在后端制程(BEOL)工艺中形成IMD层120和导电焊盘132。导电焊盘132由铜(Cu)、铜合金、铝(Al)、铝合金、钨(W)、钨合金、钛(Ti)、钽(Ta)或钽合金制成。在一些实施例中，导电焊盘132由镀法形成。
钝化层124形成在IMD层120上方并且覆盖导电焊盘132的边缘部分。此外，导电焊盘132的中心部分露出。在一些实施例中，钝化层124由非有机材料(诸如，氧化硅、非掺杂硅酸盐玻璃、氮氧化硅、阻焊剂(SR)、氮化硅、HMDS(六甲基二硅氮烷))制成。在其他一些实施例中，钝化层124由聚合物材料(诸如，聚酰亚胺(PI)、环氧树脂或含氟的聚合物)制成。
根据本发明的一些实施例，在形成钝化层124之后，如图1B所示，第一保护层130形成在钝化层124的上方。
此后，通过图案化工艺来图案化第一保护层130以露出导电焊盘132的一部分。图案化工艺包括光刻工艺和蚀刻工艺。光刻工艺的实例包括软烘、掩模对准、曝光、曝光后烘烤、使光刻胶显影、清洗和干燥(例如，硬烘)。蚀刻工艺可以是干蚀刻或湿蚀刻工艺。
在一些实施例中，第一保护层130由聚苯并恶唑(PBO)、苯开环丁烯酮(BCB)、硅树脂、丙烯酸酯或它们的组合制成。在一些实施例中，第一保护层130能够提供高图案化分辨率，这使得形成在其上的PPI互连结构(将在图1D中示出)具有精细的节距。钝化后互连(PPI)焊盘134形成在第一保护层130内，并且电连接至导电焊盘132。在形成钝化层124之后形成PPI焊盘134。在一些实施例中，PPI焊盘134被称为再分布层(RDL)焊盘。
PPI焊盘134由导电材料(诸如，铜、铜合金、铝(Al)、铝合金、钨(W)、钨合金、钛(Ti)、钛合金、钽或钽合金)制成。PPI焊盘134提供镀法、化学镀、溅射或化学汽相沉积(CVD)而形成。
通过将诸如金属材料的导电材料填充至开口内和第一保护层130上来形成PPI焊盘134。此后，通过化学机械抛光(CMP)工艺来去除过量的导电材料。
根据本发明的一些实施例，如图1C所示，在形成PPI焊盘134之后，第二保护层140形成在第一保护层130和PPI焊盘134的上方。
第二保护层140由聚苯并恶唑(PBO)、苯开环丁烯酮(BCB)、硅树脂、丙烯酸酯、硅氧烷或它们的组合制成。
在形成第二保护层140之后，通过图案化工艺对第二保护层140进行图案化以形成开口137。因此，PPI焊盘134的至少一部分露出。
根据本发明的一些实施例，如图1D所示，此后，PPI结构142形成在开口137内以及第二保护层140上。PPI结构142电连接至PPI焊盘134。PPI结构142用于电连接至衬底102中不同的区域。
PPI结构由导电材料(诸如，铜、铜合金、铝(Al)、铝合金、钨(W)、钨合金、钛、钛合金、钽或钽合金)制成。PPI结构通过镀法、化学镀、溅射或化学汽相沉积(CVD)来形成。
根据本发明的一些实施例，如图1E所示，在形成PPI结构142之后，形成第一防潮层150。此后，图案化第一防潮层150以形成开口157。PPI结构142的一部分通过开口157露出。
第一防潮层150形成在器件元件104的上方以防止可导致下方各层和PPI结构分层的潮气渗入。第一防潮层150的形成有助于半导体器件结构100a能够耐受极端环境(诸如各种可靠性测试)而潮气不会渗入。第一防潮层150的吸水性低于保护层130和140的吸水性。例如，第一防潮层150的吸水性在约0.5wt％至约2.5wt％之间。此外，第一防潮层150具有极好的机械特性，但是其仍然具有充分的应力缓冲能力。在一些实施例中，第一防潮层150在约-55摄氏度至室温的温度条件下，具有在约120Mpa至约250Mpa范围内的拉伸模量。在一些实施例中，第一防潮层150在室温下，具有约50％至约100％的断裂延伸率。此外，在一些实施例中，第一防潮层150在-55摄氏度的条件下，具有约40％至约100％的断裂延伸率。
在一些实施例中，第一防潮层150包括无机材料，诸如氮化硅、氧化硅、氮氧化硅、HMDS(六甲基二硅烷)或它们的组合。可选地，第一防潮层包括聚合物，诸如聚酰亚胺(PI)、环氧树脂、阻焊剂(SR)、含氟聚合物或它们的组合。在一些实施例中，第一防潮层150不是由PBO制成。在一些实施例中，第一防潮层150不包括PBO。
在一些实施例中，当第一防潮层150由聚合物制成时，该聚合物具有约250度至约400度范围内的分解温度(Td)，约200度至约350度范围内的玻璃化温度(Tg)，这使得第一防潮层150足够强健但不是过于刚硬易碎。
在一些实施例中，为了满足以上所述的防潮和应力缓冲的要求，聚酰亚胺(PI)具有约10wt％至约40wt％的交联(cross-link)。在一些实施例中，交联包括烷氧基(OR)，其中，R包括具有分支链或不具有分支链的C1-C20烷基、C3-C20环烷基、C6-C20芳基或C6-C20芳烷基组。类似地，环氧树脂包括介于约60wt％至约90wt％范围内的酚树脂或丙烯酸树脂；阻焊剂(SR)包括介于约10wt％至约30wt％范围内的硅酸盐填料；或含氟的聚合物包括介于约30wt％至约60wt％范围内的碳-氟(C-F)键合。含氟层可由六氟乙烷(C2F6)源、四氟甲烷(CF4)源、三氟甲烷(CHF3)源、二氟甲烷(CH2F2)源、八氟丙烷(C3F8)源、过氟化环丁烷(C4F8)源或它们的组合制成。
在一些实施例中，第一防潮层150由与钝化物层124相同的材料制成。第二保护层140和第一防潮层150构成用于保护器件元件104的防潮混合结构。
根据本发明的一些实施例，如图1F所示，在形成开口157后，凸块下金属化(UBM)层160形成在第一防潮层150内，以及导电结构162形成在UBM层160上。导电结构162通过UBM层160电连接至PPI结构142。
UBM层160可由导电材料(诸如，铜(Cu)、铜合金、铝(Al)、铝合金、钨(W)、钨合金、钛(Ti)、钛合金、钽(Ta)或钽合金)制成。此外，UBM层160可包含粘合层和/或润湿层。在一些实施例中，UBM层160还包括铜晶种层。
导电结构162是类似球状的凸块或柱体。导电结构162由导电材料(诸如锡(Sn)、铜(Cu)、金(Au)、银(Ag)、它们的合金或其他适合的材料)制成。在一些实施例中，焊膏用于提高UBM层205与导电结构162之间的粘合强度。
根据本发明的一些实施例，图1F’示出了半导体结构100a的经过修改的实施例。诸如模塑料的绝缘层126邻近于金属间介电(IMD)层120形成。在一些实施例中，芯片结构125，诸如包括半导体器件100a或100b的硅管芯或芯片，被绝缘层126包围或封装。绝缘层126被第一防潮层150覆盖，因此免于受潮。
图2A示出了根据一些实施例的半导体器件结构100b的截面图。半导体器件结构100b类似于图1F中所示的半导体器件结构100a或与其相同，除了第二防潮层170形成在第一防潮层150的上方。用于形成半导体器件结构100b的工艺和材料可与用于形成半导体器件结构100a的工艺和材料类似或相同，因此这里不再重复。
第二防潮层170邻近于UBM层160形成且与UBM层160直接接触。在一些实施例中，第二防潮层170具有的厚度与UBM层160的厚度基本相同或大于UBM层160的厚度。第二防潮层170可包括聚酰亚胺(PI)、环氧树脂、阻焊剂(SR)、氮化硅、氧化硅、HMDS(六甲基二硅烷)、含氟的聚合物或它们的组合。在一些实施例中，第二防潮层170由与第一防潮层150相同的材料形成。
图2B示出了根据一些实施例的半导体器件结构100b的修改后的实施例。绝缘层126邻近于金属间介电(IMD)层120形成。在一些实施例中，芯片结构125被绝缘层126包围或封装。绝缘层126被第一防潮层150覆盖，因此免于受潮。
图3A至图3D示出了根据本发明的一些实施例的代表半导体器件结构100c不同形成阶段的截面图。
如图3A所示，粘合层106形成在衬底102上，并且芯片结构108形成在粘合层106的上方。在一些实施例中，芯片结构108包括半导体器件结构100a或100b。导电柱状结构122邻近于芯片结构108形成。绝缘层123包围导电柱状结构122的侧壁并且使导电柱状结构122与芯片结构108分隔。在一些实施例中，绝缘层123包括氧化硅、氮化硅、导电柱状结构122的氧化物、模塑料或它们的组合。
导电柱状结构122用于连接至另一封装结构。导电柱状结构122由铜(Cu)、金(Au)、银(Ag)或其他适合的材料制成。
导电焊盘132形成在芯片结构108上方并且用于将芯片结构108的信号传输至外部元件。钝化层124形成在芯片结构108的上方。钝化层124的一部分延伸以形成在导电焊盘132和PPI焊盘134之间。
如图3A所示，导电柱状结构122的顶面与PPI焊盘134的顶面平齐。此外，第一保护层130的顶面与导电柱状结构122的顶面基本平齐。
此后，根据本发明的一些实施例，如图3B所示，第二保护层140形成在导电柱状结构122和第一保护层130的上方。PPI结构142形成在第二保护层140内。PPI结构142电连接至PPI焊盘134。
根据本发明的一些实施例，如图3C所示，在形成PPI结构142之后，第一防潮层150形成在第二保护层140和PPI结构142的上方。此后，UBM层160形成在第一防潮层150内。
根据本发明的一些实施例，如图3D所示，在形成UBM层160后，导电结构162形成在UBM层160的上方。
图3D’示出了根据本发明的一些实施例的半导体器件结构100c的经过修改的实施例。第一防潮层150包括第一子层150a和第二子层150b以使得不只一层的PPI结构形成在第一防潮层150内。在一些实施例中，第一子层150a和第二子层150b由不同的材料制成。
图4A示出了根据本发明的一些实施例的代表半导体器件结构100d的截面图。半导体器件结构100d与图1F中所示的半导体器件结构100a相同或类似，除了第二防潮层170形成在第一防潮层150的上方。用于形成半导体器件结构100d的工艺和材料可与用于形成半导体器件结构100a的工艺和材料相同或类似，因此这里不再重复。
图4B示出了根据本发明的一些实施例的代表半导体器件结构100d的截面图。第二防潮层170形成在第一防潮层150的第二子层150b的上方并且与UBM层160直接接触。
图5A至图5B示出了根据本发明的一些实施例的代表半导体器件结构100e不同形成阶段的截面图。图5A至图5B示出了叠层封装(PoP)结构。
如图5A所示，去除衬底102。背面RDL(再分布层)202形成在芯片结构108的背面。背面RDL 202包括形成在导电柱122上方的导电层204.在一些实施例中，导电层204包括UBM层。在其他一些实施例中，导电层204包括预焊(pre-solder)层。
在图5A之后，可执行两种不同的工艺。在一些实施例中，如图5B所示，第一封装结构300首先形成在半导体结构162的上方。可选地，在其他一些实施例中，如图5B’所示，第二封装结构400首先形成在导电层204的上方。
在一些实施例中，如图5B所示，第一封装结构300首先形成在导电结构162的上方。第一封装结构300包括形成在衬底302上的导电焊盘304。一些器件元件(未示出)形成在衬底302内。第一封装结构300和具有导电柱状结构122的半导体器件结构200通过导电焊盘304和导电结构162而彼此接合。因此，实现了PoP结构。
导电柱状结构122具有第一表面122a和与第一表面122a相对的第二表面122b。第一表面122a与PPI结构142直接接触，而第二表面122b与导电层204直接接触。
在其他一些实施例中，如图5B’所示，根据本发明的一些实施例，第二封装结构400首先形成在导电柱状结构122的第二表面122b的上方。导电结构206形成在导电层204的上方。
第二封装结构400包括衬底402和形成在衬底402上方的导电焊盘404.一些器件元件(未示出)形成在衬底402内。第二封装结构400和具有导电柱状结构122的半导体器件结构200通过导电焊盘404和导电结构206而彼此接合。
根据本发明的一些实施例，在第一封装结构300和第二封装结构200顺序形成在半导体器件结构200的上方之后，实现了如图5C所示的PoP结构。
图6A至图6C示出了根据本发明的一些实施例的代表半导体器件结构100f不同形成阶段的截面图。
参考图6A，第一防潮层150包括第一子层150a和第二子层150b。第二防潮层170形成在第一防潮层150的第二部分150b的上方并且邻近于UBM层160。
在一些实施例中，如图6A所示，第一封装结构300包括衬底302和形成在衬底上方的导电焊盘304。导电结构162电连接至导电焊盘304。
在一些实施例中，如图6B’所示，根据本发明的一些实施例，第二封装结构400首先形成在导电柱状结构122的第二表面122b的上方。
根据本发明的一些实施例，在第一封装结构300和第二封装结构400形成在半导体器件结构200的上方之后，实现如图6C所示的PoP结构。
如上所提及的，第一防潮层150相对于衬底102位于最外部或最顶部并且由防潮/防水层制成。第一防潮层150具有极好的防潮/防水特性，因此防止了分层问题。此外，第一防潮层150也具有极好的机械特性以防止破裂。
图7A至图7C示出了根据本发明的一些实施例的代表半导体器件结构100g不同形成阶段的截面图。图7A至图7C示出了扇出型晶圆级封装。该扇出型晶圆级封装意味着芯片结构上的I/O焊盘可分布至比芯片结构更大的区域，因此增大了芯片结构表面上的I/O焊盘的数目。
如图7A所示，绝缘层126邻近于芯片结构108和绝缘层123而形成。导电柱状结构122形成在各绝缘层126之间。在其他一些实施例中，省去了绝缘层123。
在一些实施例中，如图7B所示，第一封装结构300首先形成在导电结构162的上方。
在其他一些实施例中，如图7B’所示，第二封装结构400首先形成在UBM层204的上方。
在图7B或图7B’之后，形成另一封装结构，因此实现了包括第一封装结构300、封装结构200和第二封装结构400的PoP结构。
本发明提供了用于形成半导体器件结构的实施例及其形成方法。半导体器件结构包括衬底上方的导电焊盘结构和导电焊盘结构上方的第一保护层。PPI结构形成在第一保护层内并且第一防潮层形成在第一保护层的上方。UBM层形成在第一防潮层内。第一防潮层和第一保护层由不同的材料制成。第一防潮层具有良好的防潮性，因此它能够防止器件元件受到损坏。此外，防止了PPI结构的分层问题。第一防潮层用作应力缓冲层以防止破裂或翘曲。因此，改善了半导体器件的性能。
在一些实施例中，提供了一种半导体结构。半导体器件结构包括衬底和形成在衬底上的导电焊盘。半导体器件结构包括形成在导电焊盘上方的保护层和至少形成在保护层内的钝化后互连(PPI)结构。PPI结构电连接至导电焊盘。半导体器件结构还包括形成在所述保护层的上方的第一防潮层，并且所述保护层和所述第一防潮层由不同的材料制成。半导体器件结构还包括形成在所述第一防潮层上方并且连接至所述PPI结构的凸块下金属(UBM)层。
在一些实施例中，提供了一种半导体结构。半导体器件结构包括形成在芯片上方的导电焊盘和包围芯片的绝缘层。半导体器件结构包括形成在导电焊盘和绝缘层上方的保护层以及至少形成在保护层内的钝化后互连(PPI)结构。PPI结构电连接至导电焊盘。半导体器件结构还包括形成在所述保护层的上方的第一防潮层，并且所述第一防潮层包括聚酰亚胺(PI)、环氧树脂、阻焊剂(SR)、氮化硅、氧化硅、六甲基二硅氮烷(HMDS)、含氟聚合物或它们的组合。半导体器件结构还包括形成在所述第一防潮层上方的凸块下金属(UBM)层。
在一些实施例中，提供了一种用于形成半导体器件结构的方法。该方法包括在衬底上方形成导电焊盘以及在所述导电焊盘上方形成保护层。该方法还包括在所述保护层内形成钝化后互连(PPI)结构，并且所述PPI结构电连接至所述导电焊盘。该方法还包括在所述保护层的上方形成第一防潮层，并且所述保护层和所述第一防潮层由不同的材料制成。该方法包括在所述第一防潮层内形成凸块下金属(UBM)层。
上面论述了多个实施例的特征使得本领域技术人员能够更好地理解本发明的各个方面。本领域技术人员应该理解，他们可以容易地以本公开为基础设计或修改用于执行与本文所述实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域技术人员还应该意识到，这些等效结构不背离本发明的精神和范围，并且可以在不背离本发明的精神和范围的情况下做出各种变化、替换和改变。

Claims (10)

1.一种半导体器件结构，包括：
衬底；
导电焊盘，形成在所述衬底上；
保护层，形成在所述导电焊盘的上方；
钝化后互连(PPI)结构，至少形成在所述保护层内，其中，所述钝化后互连结构电连接至所述导电焊盘；
第一防潮层，形成在所述保护层的上方，其中，所述保护层和所述第一防潮层由不同的材料制成；以及
凸块下金属(UBM)层，形成在所述第一防潮层上方并且连接至所述钝化后互连结构。
2.根据权利要求1所述的半导体器件结构，其中，所述第一防潮层包括聚酰亚胺(PI)、环氧树脂、阻焊剂(SR)、氮化硅、氧化硅、六甲基二硅氮烷(HMDS)、含氟聚合物或它们的组合。
3.根据权利要求1所述的半导体器件结构，其中，所述保护层由聚苯并恶唑(PBO)制成，并且所述第一防潮层由聚酰亚胺(PI)制成，其中，所述聚酰亚胺(PI)包括在约10wt％至约40wt％范围内的交联。
4.根据权利要求1所述的半导体器件结构，还包括：
第二防潮层，形成在所述第一防潮层的上方并且邻近于所述凸块下金属层。
5.根据权利要求4所述的半导体器件结构，其中，所述第二防潮层由含氟聚合物制成，所述含氟聚合物包括在约30wt％至约60wt％范围内的碳-氟键合物。
6.根据权利要求1所述的半导体器件结构，还包括：
导电结构，形成在所述凸块下金属层的上方，其中，所述导电结构通过所述凸块下金属层电连接至所述钝化后互连结构。
7.一种半导体器件结构，包括：
导电焊盘，形成在芯片上方；
绝缘层，包围所述芯片；
保护层，形成在所述导电焊盘和所述绝缘层的上方；
钝化后互连(PPI)结构，至少形成在所述保护层内，其中，所述钝化后互连结构电连接至所述导电焊盘；
第一防潮层，形成在所述保护层的上方，其中，所述第一防潮层包括聚酰亚胺(PI)、环氧树脂、阻焊剂(SR)、氮化硅、氧化硅、六甲基二硅氮烷(HMDS)、含氟聚合物或它们的组合；以及
凸块下金属(UBM)层，形成在所述第一防潮层的上方。
8.根据权利要求7所述的半导体器件结构，还包括：
钝化层，形成在所述芯片和所述保护层之间，其中，所述钝化层和所述第一防潮层由相同的材料制成。
9.一种用于形成半导体器件结构的方法，包括：
在衬底上方形成导电焊盘；
在所述导电焊盘上方形成保护层；
在所述保护层内形成钝化后互连(PPI)结构，其中，所述钝化后互连结构电连接至所述导电焊盘；
在所述保护层的上方形成第一防潮层，其中，所述保护层和所述第一防潮层由不同的材料制成；以及
在所述第一防潮层内形成凸块下金属(UBM)层。
10.根据权利要求9所述的用于形成所述半导体器件结构的方法，还包括：
邻近于所述凸块下金属层形成第二防潮层，其中，所述第二防潮层由含氟的聚合物制成。
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