TW201705358A - 半導體裝置結構及其形成方法 - Google Patents

半導體裝置結構及其形成方法 Download PDF

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TW201705358A
TW201705358A TW104136967A TW104136967A TW201705358A TW 201705358 A TW201705358 A TW 201705358A TW 104136967 A TW104136967 A TW 104136967A TW 104136967 A TW104136967 A TW 104136967A TW 201705358 A TW201705358 A TW 201705358A
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layer
moisture barrier
conductive
semiconductor device
barrier layer
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TW104136967A
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TWI596701B (zh
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鄭心圃
劉獻文
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台灣積體電路製造股份有限公司
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Abstract

本揭露提供一種半導體裝置結構及其形成方法。半導體裝置結構包括一基底及位於基底上的一導電墊。半導體裝置結構包括形成於導電墊上方的一保護層以及至少形成於保護層內的一後鈍化內連接(post-passivation interconnect,PPI)結構。PPI結構電性連接至導電墊。半導體裝置結構也包括形成於保護層上方的一第一防潮層，且保護層及第一防潮層由不同材料所製成。半導體裝置結構更包括一凸塊底部金屬(UBM)層，形成於第一防潮層上方且連接至PPI結構。

Description

半導體裝置結構及其形成方法
本揭露係關於一種半導體技術，且特別是關於一種半導體裝置結構及其形成方法。
半導體裝置係使用於各種不同的電子應用中，例如個人電腦、手機、數位相機以及其他電子設備。半導體裝置的製造通常藉由於一半導體基底上方依序進行絕緣或介電層、導電層及半導體層的材料沉積，且使用微影進行各種不同材料的圖案化以於其上形成電路部件及元件。許多積體電路通常製造於單一半導體晶圓上，並藉由沿著一切割道於積體電路之間進行切割而將晶圓上各個晶粒單體化。各個晶粒通常分開封裝於多晶粒模組內或是其他類型的封裝體內。
晶圓級封裝(wafer level package,WLP)結構係電子產品的半導體部件中所使用封裝結構之一。輸入/輸出(I/O)電性接點數量增加連同高效能積體電路的需求增加，致使扇出(fan-out)式WLP結構的發展，其能夠讓用於I/O電性接點的凸塊具有較大的間距。
儘管現有的WLP結構及製造晶圓級封裝的方法一般已足以勝任其使用目的，但其尚未全面性滿足所有的面向。
根據一些實施例，本揭露提供一種半導體裝置結構，包括：一基底；一導電墊，形成於基底上；一保護層，形成於導電墊上方；一後鈍化內連接結構，至少形成於保護層內，其中後鈍化內連接結構電性連接至導電墊；一第一防潮層，形成於保護層上方，其中保護層及第一防潮層由不同材料製成；以及一凸塊底部金屬層，形成於第一防潮層上方且連接至後鈍化內連接結構。
根據一些實施例，本揭露提供一種半導體裝置結構，包括：一導電墊，形成於一晶片上方；一絕緣層，圍繞晶片；一保護層，形成於導電墊與絕緣層上方；一後鈍化內連接結構，至少形成於保護層內，其中後鈍化內連接結構電性連接至導電墊；一第一防潮層，形成於保護層上方，其中第一防潮層包括聚醯亞胺、環氧化物、防焊劑、氮化矽、氧化矽、六甲基二矽氮烷、含氟高分子材料或其組合；以及一凸塊底部金屬層，形成於第一防潮層上方。
根據一些實施例，本揭露提供一種半導體裝置結構之形成方法，包括：形成一導電墊於一基底上；形成一保護層於導電墊上方；形成一後鈍化內連接結構於保護層內，其中後鈍化內連接結構電性連接至導電墊；形成一第一防潮層於保護層上方，其中保護層及第一防潮層由不同材料製成；以及形成一凸塊底部金屬層於第一防潮層內。
100a、100b、100c、100d、100e、100f、100g、200‧‧‧半導體裝置結構
102、302、402‧‧‧基底
104‧‧‧裝置元件
106‧‧‧黏著層
108、125‧‧‧晶片結構
110‧‧‧內層介電層/ILD層
120‧‧‧金屬層間介電層/IMD層
122‧‧‧導電柱體結構
122a‧‧‧第一表面
122b‧‧‧第二表面
123、126‧‧‧絕緣層
124‧‧‧鈍化護層
130‧‧‧第一保護層
132、304、404‧‧‧導電墊
134‧‧‧後鈍化內連接墊/PPI墊
137、157‧‧‧開口
140‧‧‧第二保護層
142‧‧‧後鈍化內連接結構/PPI結構
150‧‧‧第一防潮層
150a‧‧‧第一次層
150b‧‧‧第二次層
160‧‧‧凸塊底部金屬層/UBM層
162、206‧‧‧導電結構
170‧‧‧第二防潮層
202‧‧‧背側重佈線層/背側RDL
204‧‧‧導電層
300‧‧‧第一封裝結構
400‧‧‧第二封裝結構
第1A至1F圖係繪示出根據本揭露一些實施例之半導體裝 置結構之形成方法於不同階段的剖面示意圖。
第1F’圖係繪示出根據一些實施例之半導體裝置結構的變更實施例。
第2A圖係繪示出根據一些實施例之半導體裝置結構的剖面示意圖。
第2B圖係繪示出根據一些實施例之半導體裝置結構的變更實施例。
第3A至3D圖係繪示出根據本揭露一些實施例之半導體裝置結構之形成方法於不同階段的剖面示意圖。
第3D’圖係繪示出根據一些實施例之半導體裝置結構的變更實施例。
第4A圖係繪示出根據一些實施例之半導體裝置結構的剖面示意圖。
第4B圖係繪示出根據一些實施例之半導體裝置結構的剖面示意圖。
第5A至5C圖係繪示出根據本揭露一些實施例之半導體裝置結構之形成方法於不同階段的剖面示意圖。
第5B’圖係繪示出根據一些實施例之半導體裝置結構的剖面示意圖。
第6A至6C圖係繪示出根據本揭露一些實施例之半導體裝置結構之形成方法於不同階段的剖面示意圖。
第6B’圖係繪示出根據一些實施例之半導體裝置結構的剖面示意圖。
第7A至7C圖係繪示出根據本揭露一些實施例之半導體裝 置結構之形成方法於不同階段的剖面示意圖。
第7B’圖係繪示出根據一些實施例之半導體裝置結構的剖面示意圖。
以下的揭露內容提供許多不同的實施例或範例，以實施本發明的不同特徵部件。而以下的揭露內容是敘述各個構件及其排列方式的特定範例，以求簡化本揭露內容。當然，這些僅為範例說明並非用以限定本發明。舉例來說，若是以下的揭露內容敘述了將一第一特徵部件形成於一第二特徵部件之上或上方，即表示其包含了所形成的上述第一特徵部件與上述第二特徵部件是直接接觸的實施例，亦包含了尚可將附加的特徵部件形成於上述第一特徵部件與上述第二特徵部件之間，而使上述第一特徵部件與上述第二特徵部件可能未直接接觸的實施例。另外，本揭露內容在各個不同範例中會重複標號及/或文字。重複是為了達到簡化及明確目的，而非自行指定所探討的各個不同實施例及/或配置之間的關係。
以下說明實施例的差異。全文中不同的圖式及實施例中，相同的標號係用於表示相同的部件。可以理解的是可在方法進行之前、期間及之後進行額外的操作，而所述方法的其他實施例中可取代或排除某些所述的操作。
以下提供半導體裝置結構及其製造方法的實施例。第1A至1F圖係繪示出根據本揭露一些實施例之半導體裝置結構100a之形成方法於不同階段的剖面示意圖。半導體裝置結構100a應用於晶圓級封裝(WLP)。
請參照第1A圖，提供一基底102。基底102由矽或其他半導體材料製成。另外，基底102可包括其他元素半導體材料，例如鍺。在一些其他實施例中，基底102由化合物半導體製成，例如，碳化矽、砷化鎵、砷化銦或磷化銦。在一些實施例中，基底102由合金半導體製成，例如，鍺化矽、碳化矽鍺、磷化鎵砷或磷化鎵銦。在一些其他實施例中，基底102包括一磊晶層。舉例來說，基底102包括位於塊材半導體上的一磊晶層。
半導體裝置結構100a也包括一內層介電(inter-layer dielectric,ILD)層110為於基底102上。ILD層110由氧化矽(SiOx)、氮化矽(SixNy)或氮氧化矽(SiON)製成。
裝置元件104形成於ILD層110內。裝置元件104包括電晶體(例如，金屬氧化物半導體場效電晶體(MOSFET))、互補式金屬氧化物半導體(CMOS)電晶體、雙極接面電晶體(BJT)、高壓電晶體、高頻電晶體、p通道及/或n通道場效應電晶體(PFET/NFET)等)、二極體及/或其他合適的元件。實施各種不同的製程(例如，沉積、蝕刻、佈植、光學微影、退火及/或其他合適的製程)以形成各種不同的裝置元件。
基底102可包括各種不同的摻雜區，例如p型井區或n型井區。摻雜區可摻雜p型摻雜物(例如，硼或BF2)及/或n型摻雜物(例如，磷(P)或砷(As))。摻雜區可直接形成於p型井區結構、n型井區結構或雙井區結構內的基底102上。
基底102可進一步包括隔離特徵部件(未繪示)， 例如淺溝槽隔離(STI)特徵部件或矽局部氧化(LOCOS)特徵部件。隔離特徵部件可定義及隔離各種不同的裝置元件。
一金屬層間介電(inter-metal dielectric,IMD)層120形成於ILD層110上方。IMD層120由氧化矽(SiOx)、氮化矽(SixNy)、氮氧化矽(SiON)、具有低介電常數(low-k)的介電材料或其組合製成。在一些實施例中，IMD層120由具有介電常數低於約2.5的超低介電常數(ELK)介電材料製成。在一些實施例中，ELK介電材料包括碳摻雜氧化矽、雙-苯並環丁烯(bis-benzocyclobutene,BCB)、聚四氟乙烯(Polytetrafluoroethene,PTFE)(Teflon)或碳氧化矽(SiOC)高分子。在一些實施例中，ELK介電材料包括多孔形式的現有介電材料，例如含氫矽酸鹽類(hydrogen silsequioxane,HSQ)、多孔甲基矽酸鹽類(methyl silsequioxane,MSQ)、多孔聚芳烯醚(polyarylether,PAE)、多孔SiLK或多孔氧化矽(SiO2)。在一些實施例中，IMD層120藉由電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition,PECVD)製程或旋塗製程進行沉積。
一導電墊132形成於IMD層120上方。導電墊132經由IMD層120內各個不同的金屬線及介層連接窗(via)而電性連接至裝置元件104。
IMD層120及導電墊132形成於後段製程(back-end-of-line,BEOL)中。導電墊132由銅(Cu)、銅合金、鋁(Al)、鋁合金、鎢(W)、鎢合金、鈦(Ti)、鈦合金、鉭(Ta)或鉭合金製成。在一些實施例中，導電墊132藉 由電鍍法而形成。
一鈍化護層124形成於IMD層120上方，且覆蓋導電墊132的邊緣部分。另外，露出導電墊132的中心部分。在一些實施例中，鈍化護層124由非有機材料製成，例如氧化矽、未摻雜矽玻璃、氮氧化矽、防焊劑(solder resist,SR)、氮化矽或六甲基二矽氮烷(hexamethyldisilazane,HMDS)。在一些實施例中，鈍化護層124由高分子材料製成，例如聚醯亞胺(polyimide,PI)、環氧化物或含氟高分子材料。
根據本揭露一些實施例，在形成鈍化護層124之後，一第一保護層130形成於鈍化護層124上方，如第1B圖所示。
之後，藉由一圖案化製程以圖案化第一保護層130，而露出部分的導電墊132。圖案化製程包括一光學微影製程及一蝕刻製程。光學微影製程的範例包括軟烤、光罩對準、曝光、曝後烤、光阻顯影、清洗及乾燥(例如，硬烤)。
在一些實施例中，第一保護層130由聚苯噁唑(polybenzoxazole,PBO)、雙-苯並環丁烯(BCB)、矽膠、丙烯酸鹽(acrylates)、矽氧烷(siloxane)或其組合製成。在一些實施例中，第一保護層130能夠提供高圖案化解析度，其容許PPI結構(將繪示於第1D圖)形成於其上而具有微間距。一PPI墊134形成於第一保護層130內，且電性連接至導電墊132。PPI墊134於形成鈍化護層124之後形成。在一些實施例中，PPI墊134稱作重佈線(redistribution layer,RDL)墊。
PPI墊134由導電材料製成，例如銅(Cu)、銅合金、鋁(Al)、鋁合金、鎢(W)、鎢合金、鈦(Ti)、鈦合 金、鉭(Ta)或鉭合金。PPI墊134由電鍍、無電電鍍、濺鍍或化學氣相沉積(CVD)形成。
PPI墊134藉由填入導電材料(例如，金屬材料)於開口內，並形成於第一保護層130上而形成。之後，藉由化學機械研磨(chemical mechanical polishing,CMP)製程去除多餘的導電材料。
根據本揭露一些實施例，在形成PPI墊134之後，一第二保護層140形成於第一保護層130及PPI墊134上方，如第1C圖所示。
第二保護層140由聚苯噁唑(PBO)、雙-苯並環丁烯(BCB)、矽膠、丙烯酸鹽、矽氧烷或其組合製成。
在形成第二保護層140之後，藉由圖案化製程以圖案化第二保護層140，而形成開口137。因此，露出至少一部份的PPI墊134。
之後，根據本揭露一些實施例，一PPI結構142形成於開口137內及第二保護層140上，如第1D圖所示。PPI結構142電性連接至PPI墊134。PPI結構142係用於電性連接至基底102的不同區域。
PPI結構142由導電材料所製成，例如銅(Cu)、銅合金、鋁(Al)、鋁合金、鎢(W)、鎢合金、鈦(Ti)、鈦合金、鉭(Ta)或鉭合金。PPI結構142由電鍍、無電電鍍、濺鍍或化學氣相沉積(CVD)形成。
根據本揭露一些實施例，在形成PPI結構142之後，形成一第一防潮層150，如第1E圖所示。之後，圖案化第 一防潮層150以形成開口157。藉由開口157露出一部分的PPI結構142。
第一防潮層150形成於裝置元件104上方以防止水氣穿透而導致下方的保護層及PPI結構發生剝離。形成的第一防潮層150有助於半導體裝置結構100a能夠經過嚴苛環境(例如各種不同的可靠度測試)而無水氣透入。第一防潮層150具有低於保護層130及140的吸水性(water absorption)。舉例來說，第一防潮層150的吸水性約在0.5wt%至2.5wt%的範圍。再者，第一防潮層150具有良好的機械特性，但仍具有適當的應力緩衝能力。在一些實施例中，第一防潮層150在-55度C至室溫的溫度範圍中，其拉伸模數約在120MPa至250MPa的範圍。在一些實施例中，第一防潮層150在室溫下的斷裂伸長率(elongation at break)在50%至100%的範圍。另外，在一些實施例中，第一防潮層150在-55度C下的斷裂伸長率在40%至100%的範圍。
在一些實施例中，第一防潮層150由無機材料製成，例如氮化矽、氧化矽、氮氧化矽、六甲基二矽氮烷(HMDS)或其組合。另外，第一防潮層150包括一高分子材料，例如聚醯亞胺(PI)、環氧化物、防焊劑(SR)或含氟高分子材料。在一些實施例中，第一防潮層150不由聚苯噁唑(PBO)製成。在一些實施例中，第一防潮層150不包括聚苯噁唑(PBO)。
在一些實施例中，當第一防潮層150由高分子材料製成時，高分子材料具有一分解溫度(Td)，其在250度C至400度C的範圍，且具有一玻璃轉換溫度(Tg)，其在200度C至350 度C的範圍，其讓第一防潮層150夠堅固卻不會太剛性或脆性。
在一些實施例中，為了符合上述防潮及應力緩衝的需求，聚醯亞胺(PI)具有約10wt%至40wt%範圍的交聯(cross-links)。在一些實施例中，交聯包括烷氧基(alkoxy,OR)，其中R包括具有或不具有支鏈(branched chain)的C1-C20烷基(alkyl)、C3-C20環烷基(cycloalky)、C6-C20芳香基(aryl)或C6-C20芳烷基(aralkyl)。同樣地，環氧化物包括具有約60wt%至90wt%範圍的苯酚(phenol)樹脂或丙烯酸(acrylic)樹脂。防焊劑(SR)包括具有約10wt%至30wt%範圍的矽酸鹽填充劑(silicate filler)。含氟高分子材料包括具有約30wt%至60wt%範圍的碳氟(C-F)鍵結。含氟層的製作來源為六氟乙烷(hexafluoroethane,C2F6)、四氟化碳(tetrafluoromethane,CF4)、三氟甲烷(trifluoromethane,CHF3)、二氟甲烷(difluoromethane,CH2F2)、八氟丙烷(octafluoropropane,C3F8)、八氟環丁烷(octafluorocyclobutane,C4F8)或其組合。
在一些實施例中，第一防潮層150由相同於鈍化護層124的材料製成。第二保護層140及第一防潮層150構成一防潮混合結構，以保護裝置元件104。
根據本揭露一些實施例，在形成開口157之後，一凸塊底部金屬(UBM)層160形成於第一防潮層150內，且一導電結構162形成於UBM層160上，如第1F圖所示。導電結構162藉由UBM層160電性連接至PPI結構142。
UBM層160由導電材料製成，例如銅(Cu)、銅合 金、鋁(Al)、鋁合金、鎢(W)、鎢合金、鈦(Ti)、鈦合金、鉭(Ta)或鉭合金。另外，UBM層160可包含一黏著層及/或一潤濕層。在一些實施例中，UBM層160更包括一銅種子層。
導電結構162為一球形凸塊或柱體。導電結構162由導電材料製成，例如錫(Sn)、銅(Cu)、金(Au)、銀(Ag)、其合金或其他合適材料。在一些實施例中，使用錫膏以加強UBM層160與導電結構162之間的黏著強度。
第1F’圖係繪示出根據一些實施例之半導體裝置結構100a的變更實施例。形成一絕緣層126(例如，一模塑成型材料(molding compound))鄰近於金屬層間介電(IMD)層120。在一些實施例中，包括半導體裝置100a或100b的一晶片結構125(例如，一矽晶粒或晶片)為絕緣層126所圍繞或包圍。絕緣層126為第一防潮層150所覆蓋，因此能夠免於受潮。
第2A圖係繪示出根據一些實施例之半導體裝置結構100b的剖面示意圖。半導體裝置結構100b相似或相同於第1F圖所示的半導體裝置結構100a，除了一第二防潮層170形成於第一防潮層150上方。用於形成半導體裝置結構100b的製程及材料可相似或相同於用於形成半導體裝置結構100a的製程及材料，在此不再贅述。
形成的第二防潮層170鄰近於UBM層160且與其直接接觸。在一些實施例中，第二防潮層170具有一厚度實質相同或大於UBM層160。第二防潮層170可包括聚醯亞胺(PI)、環氧化物、防焊劑(SR)、氮化矽、氧化矽、六甲基二矽氮烷(HMDS)、含氟高分子材料或其組合。在一些實施例中，第 二防潮層170由相同於第一防潮層150的材料形成。
第2B圖係繪示出根據一些實施例之半導體裝置結構100b的變更實施例。絕緣層126鄰近形成於金屬層間介電(IMD)層120。在一些實施例中，一晶片結構125為絕緣層126所圍繞或包圍。絕緣層126為第一防潮層150所覆蓋，因此能夠免於受潮。
第3A至3D圖係繪示出根據本揭露一些實施例之半導體裝置結構100c之形成方法於不同階段的剖面示意圖。
如第3A圖所示，一黏著層106形成於基底102上，且一晶片結構108形成於黏著層106上方。在一些實施例中，晶片結構108包括半導體裝置結構100a或100b。導電柱體結構122鄰近形成於晶片結構108。絕緣層123圍繞導電柱體結構122側壁，且隔開導電柱體結構122與晶片結構108。在一些實施例中，絕緣層123包括氧化矽、氮化矽、導電柱體結構122的氧化物、模塑成型材料或其組合。
導電柱體結構122用於連接另一封裝結構。導電柱體結構122由銅(Cu)、金(Au)、銀(Ag)、或其他合適材料製成。
導電墊132形成於晶片結構108上方，且用於將晶片結構108的信號傳送至外部元件。鈍化護層124形成於晶片結構108上方。延伸一部分的鈍化護層124以形成於導電墊132與PPI墊134之間。
如第3A圖所示，導電柱體結構122的一上表面與導電墊132的一上表面切齊。另外，第一保護層130的一上表面與 導電柱體結構122的上表面實質上切齊。
之後，根據本揭露一些實施例，第二保護層140形成於導電柱體結構122及第一保護層130上方，如第3B圖所示。PPI結構142形成於第二保護層140內。PPI結構142電性連接至PPI墊134。
根據本揭露一些實施例，在形成PPI結構142之後，第一防潮層150形成於第二保護層140及PPI結構142上方，如第3C圖所示。之後，UBM層160形成於第一防潮層150內。
根據本揭露一些實施例，在形成UBM層160之後，導電結構162形成於UBM層160上方，如第3D圖所示。
第3D’圖係繪示出根據一些實施例之半導體裝置結構100c的變更實施例。第一防潮層150包括一第一次層150a及一第二次層150b，以容許多於一層的PPI結構形成於第一防潮層150內。在一些實施例中，第一次層150a及第二次層150b由不同材料製成。
第4A圖係繪示出根據一些實施例之半導體裝置結構100d的剖面示意圖。半導體裝置結構100d相似或相同於第1F圖的半導體裝置結構100a，除了第二防潮層170形成於第一防潮層150上方。用於形成半導體裝置結構100d的製程及材料可相似或相同於用於形成半導體裝置結構100a的製程及材料，在此不再贅述。
第4B圖係繪示出根據一些實施例之半導體裝置結構100d的剖面示意圖。第二防潮層170形成於第一防潮層150的第二次層150b上方且與UBM層160直接接觸。
第5A至5C圖係繪示出根據本揭露一些實施例之半導體裝置結構100e之形成方法於不同階段的剖面示意圖。第5A至5C圖繪示出層疊封裝(package on package,PoP)結構。
如第5A所示，移除基底102。一背側重佈線層(RDL)202形成於晶片結構108的背側上。背側RDL 202包括一導電層204形成於導電柱體結構122上。在一些實施例中，導電層204包括一UBM層。在一些實施例中，導電層204包括一預焊(pre-solder)層。
如第5A圖所示，進行二個不同的製程。在一些實施例中，如第5B圖所示，第一封裝結構300先形成於導電結構162上方。另外，在一些實施例中，如第5B’圖所示，第二封裝結構400先形成於導電結構204上方。
在一些實施例中，如第5B圖所示，第一封裝結構300先形成導電結構162上方。第一封裝結構300包括一導電墊304形成於一基底302上。一些裝置元件(未繪示)形成於基底302內。第一封裝結構300與具有導電柱體結構122的半導體裝置結構200透過導電墊304及導電結構162彼此接合。因此，獲得PoP結構。
導電柱體結構122具有一第一表面122a及與第一表面122a相對的一第二表面122b。第一表面122a與PPI結構142直接接觸，且第二表面122b與導電層204直接接觸。
根據本揭露一些實施例，如第5B’圖所示，第二封裝結構400先形成於導電柱體結構122的第二表面122b上方。一導電結構206形成於導電層204上方。
第二封裝結構400包括一基底402及形成於基底402上的一導電墊404。一些裝置元件(未繪示)形成於基底402內。第二封裝結構400與具有導電柱體結構122的半導體裝置結構200透過導電墊404及導電結構206彼此接合。
根據本揭露一些實施例，在第一封裝結構300及第二封裝結構400依序形成於半導體裝置結構200上方之後，可獲得PoP結構，如第5C圖所示。
第6A至6C圖係繪示出根據本揭露一些實施例之半導體裝置結構100f之形成方法於不同階段的剖面示意圖。
請參照第6A圖，第一防潮層150包括第一次層150a及第二次層150b。第二防潮層170形成於第一防潮層150的第二次層150b上方，且鄰近於UBM層160。
在一些實施例中，如第6A圖所示，第一封裝結構300包括基底302及形成於基底302上方的導電墊304。導電結構162電性連接至導電墊304。
根據本揭露一些實施例，如第6B’圖所示，第二封裝結構400先形成於導電柱體結構122的第二表面122b上方。
根據本揭露一些實施例，在形成第一封裝結構300及第二封裝結構400於半導體裝置結構200之後，可得到PoP結構，如第6C圖所示。
如以上所述，第一防潮層150位於相對於基底102的最外或上方位置，且由防潮/防水層製成。第一防潮層150具有良好的防潮/防水性，因而可防止剝離問題。另外，第一防潮層150也具有良好的機械性質以防止龜裂。
第7A至7C圖係繪示出根據本揭露一些實施例之半導體裝置結構100g之形成方法於不同階段的剖面示意圖。第7A至7C圖係繪示出一扇出式(fan-out)晶圓級封裝。扇出式晶圓級封裝意指晶片結構上的I/O墊可分佈成比晶片結構更大的區域，因此晶片結構的表面上的I/O墊的數量得以增加。
如第7A圖所示，絕緣層126鄰近形成於晶片結構108及絕緣層123。導電柱體結構122形成於絕緣層126之間。在一些實施例中，可省略絕緣層123。
在一些實施例中，如第7B圖所示，第一封裝結構300先形成於導電結構162上方。
在一些實施例中，如第7B’圖所示，第二封裝結構400先形成於UBM層204上方。
在完成如第7B或7B’圖的結構之後，形成另一封裝結構，因而可得到包括第一封裝結構300、半導體裝置結構200及第二封裝結構400的PoP結構。
以下提供半導體裝置及其形成方法的實施例。一半導體裝置結構包括一導電墊位於一基底上方，且一第一保護層位於導電墊上方。一PPI結構形成於第一保護層內，且一第一防潮層形成於第一保護層上方。一UBM層形成於第一防潮層內。第一防潮層及第一保護層由不同材料製成。第一防潮層具有良好的防潮性，且其防止裝置元件受損。另外，防止PPI結構的剝離問題。第一防潮層係用作一應力緩衝層，以防止龜裂或翹曲。因此，可改善半導體裝置結構的效能。
在一些實施例中，提供一種半導體裝置結構。半 導體裝置結構包括一基底及形成於基底上的一導電墊。半導體裝置結構包括一保護層形成於導電墊上方及一後鈍化內連接結構至少形成於保護層內。後鈍化內連接結構電性連接至導電墊。半導體裝置結構包括一第一防潮層形成於保護層上方，且保護層及第一防潮層由不同材料製成。半導體裝置結構更包括一凸塊底部金屬層形成於第一防潮層上方，且連接至後鈍化內連接結構。
在一些實施例中，提供一種半導體裝置結構。半導體裝置結構包括一導電墊形成於一晶片上方及一絕緣層圍繞晶片。半導體裝置結構包括一保護層形成於導電墊與絕緣層上方及一後鈍化內連接結構至少形成於保護層內。後鈍化內連接結構電性連接至導電墊。半導體裝置結構包括一第一防潮層形成於保護層上方，且第一防潮層包括聚醯亞胺、環氧化物、防焊劑、氮化矽、氧化矽、六甲基二矽氮烷、含氟高分子材料或其組合。半導體裝置結構包括一凸塊底部金屬層形成於第一防潮層上方。
在一些實施例中，提供一種半導體裝置結構之形成方法。上述方法包括形成一導電墊於一基底上及形成一保護層於導電墊上方。上述方法也包括形成一後鈍化內連接結構於保護層內，且後鈍化內連接結構電性連接至導電墊。上述方法更包括形成一第一防潮層於保護層上方，且保護層及第一防潮層由不同材料製成。上述方法包括形成一凸塊底部金屬層於第一防潮層內。
以上概略說明了本發明數個實施例的特徵，使所 屬技術領域中具有通常知識者對於本揭露的型態可更為容易理解。任何所屬技術領域中具有通常知識者應瞭解到可輕易利用本揭露作為其它製程或結構的設計或變更基礎，以進行相同於此處所述實施例的目的及/或獲得相同的優點。任何所屬技術領域中具有通常知識者也可理解與上述等同的結構並未脫離本揭露之精神和保護範圍內，且可在不脫離本揭露之精神和範圍內，當可作更動、替代與潤飾。
100a‧‧‧半導體裝置結構
102‧‧‧基底
104‧‧‧裝置元件
110‧‧‧內層介電層/ILD層
120‧‧‧金屬層間介電層/IMD層
124‧‧‧鈍化護層
130‧‧‧第一保護層
132‧‧‧導電墊
134‧‧‧後鈍化內連接墊/PPI墊
140‧‧‧第二保護層
142‧‧‧後鈍化內連接結構/PPI結構
150‧‧‧第一防潮層
160‧‧‧凸塊底部金屬層/UBM層
162‧‧‧導電結構

Claims (14)

  1. 一種半導體裝置結構，包括：一基底；一導電墊，形成於該基底上；一保護層，形成於該導電墊上方；一後鈍化內連接結構，至少形成於該保護層內，其中該後鈍化內連接結構電性連接至該導電墊；一第一防潮層，形成於該保護層上方，其中該保護層及該第一防潮層由不同材料製成；以及一凸塊底部金屬層，形成於該第一防潮層上方且連接至該後鈍化內連接結構。
  2. 如申請專利範圍第1項所述之半導體裝置結構，其中該第一防潮層包括聚醯亞胺、環氧化物、防焊劑、氮化矽、氧化矽、六甲基二矽氮烷、含氟高分子材料或其組合，且其中該保護層由聚苯噁唑製成，該第一防潮層由聚醯亞胺製成，其中該聚醯亞胺包括10wt%至40wt%範圍的交聯。
  3. 如申請專利範圍第1項所述之半導體裝置結構，更包括：一第二防潮層，形成於該第一防潮層上方且鄰近於該凸塊底部金屬層，其中該第二防潮層由含氟高分子材料製成，其中該含氟高分子材料包括具有30wt%至60wt%範圍的碳氟(C-F)鍵結。
  4. 如申請專利範圍第1項所述之半導體裝置結構，更包括：一導電結構，形成於該凸塊底部金屬層上方，其中該導電結構經由該凸塊底部金屬層電性連接至該後鈍化內連接結 構；以及一封裝結構，形成於該導電結構上方，其中該導電結構電性連接至該封裝結構的一導電墊。
  5. 如申請專利範圍第1項所述之半導體裝置結構，更包括：一鈍化護層，形成於該導電墊與該後鈍化內連接結構之間，其中該鈍化護層及該第一防潮層由相同材料製成。
  6. 一種半導體裝置結構，包括：一導電墊，形成於一晶片上方；一絕緣層，圍繞該晶片；一保護層，形成於該導電墊與該絕緣層上方；一後鈍化內連接結構，至少形成於該保護層內，其中該後鈍化內連接結構電性連接至該導電墊；一第一防潮層，形成於該保護層上方，其中該第一防潮層包括聚醯亞胺、環氧化物、防焊劑、氮化矽、氧化矽、六甲基二矽氮烷、含氟高分子材料或其組合；以及一凸塊底部金屬層，形成於該第一防潮層上方。
  7. 如申請專利範圍第6項所述之半導體裝置結構，更包括：一鈍化護層，形成於該晶片與該保護層之間，其中該鈍化護層及該第一防潮層由相同材料製成。
  8. 如申請專利範圍第6項所述之半導體裝置結構，更包括：一第一導電結構，形成於該凸塊底部金屬層上；以及一第一封裝結構，形成於該第一導電結構上方。
  9. 如申請專利範圍第6項所述之半導體裝置結構，更包括：一導電柱體結構，穿過該絕緣層，其中該導電柱體結構包 括鄰近於該後鈍化內連接結構的一第一表面以及相對於該第一表面的一第二表面；一導電層，形成於該導電柱體結構的該第二表面上方；一第二導電結構，形成於該導電層上方；以及一第二封裝結構，形成於該第二導電結構上方。
  10. 如申請專利範圍第6項所述之半導體裝置結構，更包括：一第二防潮層，形成於該第一防潮層上方，其中該第二防潮層鄰近於該凸塊底部金屬層。
  11. 一種半導體裝置結構之形成方法，包括：形成一導電墊於一基底上；形成一保護層於該導電墊上方；形成一後鈍化內連接結構於該保護層內，其中該後鈍化內連接結構電性連接至該導電墊；形成一第一防潮層於該保護層上方，其中該保護層及該第一防潮層由不同材料製成；以及形成一凸塊底部金屬層於該第一防潮層內。
  12. 如申請專利範圍第11項所述之半導體裝置結構之形成方法，更包括：形成一第二防潮層鄰近於該凸塊底部金屬層，其中該第二防潮層由含氟高分子材料製成。
  13. 如申請專利範圍第11項所述之半導體裝置結構之形成方法，更包括：形成一導電結構於該凸塊底部金屬層上方；以及形成一封裝結構於該導電結構上方，其中該封裝結構電性 連接至該導電結構。
  14. 如申請專利範圍第11項所述之半導體裝置結構之形成方法，更包括：形成一晶片結構於該導電墊與該基底之間；形成一絕緣層圍繞該晶片結構；以及形成一導電柱體結構穿過該絕緣層且鄰近於該晶片結構。
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