WO2015123952A1 - 半导体封装结构及其形成方法 - Google Patents

半导体封装结构及其形成方法 Download PDF

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Publication number
WO2015123952A1
WO2015123952A1 PCT/CN2014/080839 CN2014080839W WO2015123952A1 WO 2015123952 A1 WO2015123952 A1 WO 2015123952A1 CN 2014080839 W CN2014080839 W CN 2014080839W WO 2015123952 A1 WO2015123952 A1 WO 2015123952A1
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Prior art keywords
layer
package structure
semiconductor package
chip
structure according
Prior art date
Application number
PCT/CN2014/080839
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English (en)
French (fr)
Inventor
夏鑫
丁万春
高国华
Original Assignee
南通富士通微电子股份有限公司
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Publication date
Priority claimed from CN201410061267.1A external-priority patent/CN103903989A/zh
Priority claimed from CN201410061904.5A external-priority patent/CN103887187B/zh
Application filed by 南通富士通微电子股份有限公司 filed Critical 南通富士通微电子股份有限公司
Priority to US14/780,233 priority Critical patent/US9515010B2/en
Publication of WO2015123952A1 publication Critical patent/WO2015123952A1/zh

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Definitions

  • the present invention relates to the field of semiconductor packaging, and more particularly to a semiconductor package structure and a method of forming the same.
  • the QFN package structure includes: a semiconductor chip 14, the semiconductor chip 1 has a disk 2; a pin 3 (lead frame), and the pin 3 surrounds Arranging the periphery of the semiconductor chip 1; the metal wire 4, the metal wire 4 electrically connecting the pad 2 of the semiconductor chip 1 with the pin 3 surrounding the semiconductor chip 1; the molding material 5, the molding material 5 will be the semiconductor chip 1
  • the metal wire 4 and the pin 3 are sealed, and the surface of the pin 3 is exposed on the bottom surface of the molding material, and the electrical connection between the semiconductor chip 1 and the external circuit is realized through the pin 3.
  • the existing package structure occupies a large volume, which is not conducive to the improvement of the package structure integration.
  • the problem solved by the present invention is how to improve the integration degree of the package structure.
  • the present invention provides a semiconductor package structure, including: a chip, a surface of the chip is provided with a pad and a deuterated layer, and the deuterated layer is provided with a first opening exposing the pad, a seed layer and a columnar bump are disposed in the first opening, and the seed layer and the disk are
  • the columnar bumps are stacked on the seed layer;
  • the lead frame, the lead frame is provided with a plurality of discrete pins, and the inner and outer pins are disposed on opposite sides of the pin;
  • the columnar bump is connected to the inner lead; a plastic sealing layer, the plastic sealing layer seals the chip, the column bump and the lead frame, and exposes the outer lead;
  • the dots are composed of an adhesion layer, a barrier layer and a solder stack in order from bottom to top, the adhesion layer is connected to the seed layer, the barrier layer is stacked on the adhesion layer, and the solder is stacked on the barrier layer.
  • the present invention also provides a method of forming a semiconductor package structure, comprising: providing a semiconductor chip, a surface of the chip is provided with a pad and a passivation layer, and the passivation layer is provided with a first opening exposing the pad Forming a heat resistant metal layer and a metal wetting layer on the pad and the passivation layer of the chip; forming a photoresist on the metal wetting layer, wherein the photoresist is provided with a metal infiltrated layer over the die pad a second opening; an adhesion layer and a barrier layer are sequentially formed on the metal wetting layer in the second opening; solder is formed on the barrier layer; the photoresist is removed; the heat resistant metal layer and the metal wetting layer on the passivation layer are etched to the surface a layer of exposed; reflowing the solder to form a stud bump; providing a lead frame, the lead frame having a plurality of discrete pins, the inner and outer pins being disposed on opposite sides of the pin
  • the package structure of the present invention is that the semiconductor chip is flipped over the lead, and the pad on the semiconductor chip is electrically connected to the inner lead through the column bump, so that the lateral area occupied by the formed package structure is reduced, and the entire package structure is completed.
  • the smaller size increases the integration of the package structure.
  • FIG. 1 is a schematic structural view of a prior art package structure
  • FIG. 2 to FIG. 11 are schematic cross-sectional structural views showing a process of forming a package structure according to an embodiment of the present invention.
  • a semiconductor chip 200 is provided, a surface of the semiconductor chip 200 A pad 201 and a passivation layer 202 are provided, and the passivation layer 202 is provided with a first opening exposing the pad 201.
  • the pad 201 is a functional output terminal of the chip 200, and finally realizes an electrical functional conduction transition through the subsequently formed columnar bumps 206;
  • the material of the passivation layer 202 includes silicon oxide, silicon nitride, silicon oxynitride, and polyacyl A dielectric material such as an imine or a benzene tripolybutene or a mixture thereof is used to protect the wiring in the chip 200.
  • the pad and the passivation layer of the chip may be the initial pad and the initial passivation layer of the chip, or may be a transition pad and a passivation layer formed according to the layout design requirement;
  • the way of the pad and passivation layer is mainly by using the rewiring process technology, and the initial pad and the passivation layer are transferred to the transition pad and the passivation layer by one or more layers of rewiring.
  • the rewiring process technology is a well-established process and is well known to those skilled in the art and will not be described again.
  • a heat resistant metal layer 203 and a metal wetting layer 204 are sequentially formed on the disk 201 and the deuterated layer 202 of the chip 200.
  • the material of the heat resistant metal layer 203 may be titanium Ti, chromium Cr, tantalum Ta or a combination thereof, and Ti is preferably used in the present invention.
  • the material of the metal wetting layer 204 may be one of copper Cu, aluminum Al, nickel M or a combination thereof, wherein the preferred metal wetting layer 204 is Cu.
  • the heat resistant metal layer 203 and the metal wetting layer 204 together form a seed layer of the final structure.
  • the method of the heat resistant metal layer 203 and the metal wetting layer 204 can also be carried out by a conventional evaporation or sputtering or physical vapor deposition method, and the preferred method is sputtering.
  • the method of formation is not limited to the sputtering method, and other applicable methods can be applied to the present invention, and the thicknesses of the formed heat resistant metal layer 203 and the metal wetting layer 204 are also practical. Depending on the process requirements.
  • a photoresist 205 is formed on the metal wetting layer 204, and the photoresist 205 is provided with a second opening exposing the metal wetting layer 204 above the pad 201 of the chip 200.
  • the method of forming the photoresist 205 may be spin coating, and the specific steps of these methods are well known to those skilled in the art and will not be described here.
  • the shape of the disk 201 can be specifically defined by an existing photolithographic development technique to form an opening in the photoresist 205 to expose the metal wetting layer 204 on the pad 201.
  • the second opening is smaller than the first opening, that is, the opening size of the photoresist 205 is smaller than the opening size of the deuterated layer of the chip 200;
  • the bumps 206 can fall within the first opening, avoiding the reliability problem that the columnar bumps 206 are formed on the passivation layer 202 to cause excessive stress and the pads 201 are easily brittle.
  • an adhesion layer 206a and a barrier layer 206b are sequentially formed on the metal wetting layer 204 in the second opening.
  • an adhesion layer 206a and a barrier layer 206b are sequentially formed, the specific process It can be done by electroplating.
  • the method of formation is not limited to electroplating, and other applicable methods can be applied to the present invention.
  • the material of the adhesion layer 206a is copper Cu
  • the material of the barrier layer 206b is nickel M.
  • the adhesion layer 206a has a thickness of 5 to 50 ⁇ m, and a specific thickness of 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, 20 ⁇ m, 25 ⁇ m, 30 ⁇ m, 35 ⁇ m, 40 ⁇ m, 45 ⁇ m or 50 ⁇ m.
  • the adhesion layer 206a is a columnar structure main body of the columnar bump 206 which is the final electrical output terminal.
  • the adhesion layer 206a spatially provides a sufficient material space to ensure that the subsequently formed solder 206c can be firmly placed on the adhesion layer 206a without being deviated after reflow, and also improves the bonding force with the solder 206c.
  • the size of the solder 206c is reduced, and the number of functional output ports in the unit space is improved under the premise of ensuring the reliability of the physical connection in the final product soldering process, and the density is more satisfied. Packaging requirements with high pitch and function output.
  • the barrier layer 206b has a thickness of 1.5 ⁇ m to 3 ⁇ m, and a specific thickness of 1.5 ⁇ m, 2 ⁇ m, 2.5 ⁇ m or 3 ⁇ m.
  • the function of the barrier layer 206b is to prevent the material of the subsequent formation of the bumps from scattering into the metal wetting layer 204.
  • the thickness of the M layer is less than 1.5 ⁇ m, the germanium eventually disappears due to the diffusion effect between adjacent metals, and thus cannot be effectively The subsequent solder bumps are prevented from diffusing into the metal wetting layer 204; when the thickness of the germanium layer is greater than 3 ⁇ m, the resistivity increases due to the poor electrothermal performance of the germanium metal itself, thereby affecting the electrothermal performance of the final product.
  • the thickness of the appropriate barrier layer ( ⁇ ) can avoid its own disappearance due to the diffusion effect, thereby effectively preventing the pores between the solder and the metal-wetting layer due to the formation of intermetallic compounds; at the same time, it is not blocked by nickel.
  • the layer is too thick and the resistivity increases to affect the electrothermal performance of the product.
  • a solder 206c is formed on the barrier layer 206b.
  • the resist 206c is still formed on the barrier layer 206b by using the photoresist 205 as a mask, and the solder 206c is formed of pure tin or a tin alloy, such as tin-silver alloy or tin-copper. Gold, tin-silver-copper alloy, etc.
  • the method of forming the dip 206c may be electrolytic plating, sputtering, screen printing or directly implanting a pre-formed solder ball. The specific steps of these methods are well known to those skilled in the art and will not be described herein.
  • the thickness of the solder 206c is 5 ⁇ m to 70 ⁇ m, and the specific thickness is, for example, 5 ⁇ m, 10 ⁇ m, 15 ⁇ m, 20 ⁇ m, 25 ⁇ m, 30 ⁇ m, 35 ⁇ m, 40 ⁇ m, 45 ⁇ m, 50 ⁇ m, 55 ⁇ m, 60 ⁇ m, 65 ⁇ m or 70 ⁇ m.
  • the columnar structure formed by the above steps can greatly reduce the amount of solder 308a used, on the one hand, the material cost is saved, and more importantly, the small amount of solder 206c is reflowed to a smaller size, which can satisfy the fine pitch of the crucible 201 or the same space. Application requirements for multi-function output points.
  • the photoresist 205 is removed; and the adhesion layer 206a is used as a mask to etch the heat resistant metal layer 203 and the metal wetting layer 204 on the passivation layer 202 to the passivation layer.
  • the photoresist 205 can be removed and removed by wet or stripping.
  • the specific steps of these methods are well known to those skilled in the art and will not be described again.
  • the metal wetting layer 204 and the heat resistant metal layer 203 on the surface of the chip 200 other than the material 206c may be removed by spraying the acid solution or immersing the wafer in the acid solution, thereby exposing the deuterated layer. 202.
  • the molten solder 206c is hemispherical by reflow heating, and constitutes a columnar bump 206 composed of the adhesion layer 206a, the barrier layer 206b and the solder 206c.
  • the functional output terminal of the chip 200 is transitioned from the disk 201.
  • the stud bump 206 becomes the electrical output of the chip 200.
  • a lead frame 300 is provided.
  • the lead frame 300 is provided with a plurality of discrete pins, and the inner pin 301 and the outer pin 302 are disposed on opposite sides of the pin.
  • the lead frame 300 is formed by a punching or etching process, and the internal pin 301 is connected as an electrical input terminal to an active device or a passive device, and the external pin is used as an electrical output terminal and a next-level package.
  • Printed circuit boards and the like are interconnected.
  • the chip 200 on which the stud bumps 206 are formed is flip-chip mounted on the lead frame 300, and the bumps 206 are electrically connected to the inner leads 301.
  • the disk 201 on the chip 200 is electrically connected to the inner lead 301 through the stud bumps 206,
  • the lateral area occupied by the formed package structure is reduced, and the volume of the entire package structure is small, which improves the integration degree of the package structure.
  • the flip-chip structure of the invention greatly shortens the transmission distance between the chip 200 and the inner pin 201, and the resistance and the thermal resistance are correspondingly The reduction, thereby improving the performance of the entire product, as the columnar bump 206 at the output end of the chip 200 is also more able to meet the requirements of high power products.
  • the reflow process has the function of curing the material and aligning the alignment, so that the columnar bumps 206 and the inner leads 301 can be accurately aligned and fixed. .
  • the chip 200, the column bumps 206, and the lead frame 300 are sealed, and the mold layer 400 of the outer leads 302 is exposed.
  • the plastic encapsulation layer 400 surrounds the area between the chip 200, the filling chip 200 and the inner leads 301.
  • the encapsulation layer 400 also fills the opening between the pins, and the bottom of the encapsulation layer 400 exposes the outer leads 302.
  • the plastic encapsulation layer 400 is filled, since the space between the openings between the pins and the space between the chip 200 and the space between the chip 200 and the inner leads 301 are in communication, the fluidity of the molding material is improved, thereby preventing the plastic layer from being sealed. Defects such as voids are generated.
  • the plastic sealing layer 400 is used for protecting and isolating the package structure.
  • the material of the plastic sealing layer 400 is a resin, and the resin may be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole. Resin; the resin may also be polybutylene terephthalate, polycarbonate, ethylene glycol phthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, poly The amide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol; the plastic sealing layer 400 may also be other suitable molding materials.
  • the process of forming the plastic layer 400 is a plastic injection molding process or transfer process (transfer moldin) 0 molding the layer forming process 400 can also be in other suitable processes.
  • the method further comprises: dividing the encapsulation layer 400 by a dicing process to form a plurality of discrete semiconductor package units.
  • the package structure formed by the above method please refer to FIG. 11, including:
  • a chip 200 having a surface of the chip 200 and a passivation layer 202, the deuterated layer 202 being provided with a first opening exposing the pad 201, wherein the first opening is provided with a seed layer and a columnar bump 206, the seed layer is connected to the pad 201, and the columnar bump 206 is stacked Stacked on the seed layer;
  • the lead frame is provided with a plurality of discrete pins, and an inner pin 301 and an outer pin 302 are disposed on opposite sides of the pin;
  • the chip 200 is flipped on the lead frame 300, and the stud bump 206 is connected to the inner pin 301;
  • the plastic sealing layer 400 seals the chip 200, the columnar bump 206 and the lead frame 300, and exposes the outer lead 302;
  • the columnar bumps 206 are sequentially composed of an adhesion layer 206a, a barrier layer 206b and a solder 206c stacked from bottom to top, the adhesion layer 206a is connected to the seed layer, the barrier layer 206b is stacked on the adhesion layer 206a, and the buffer 206c is stacked on On the barrier layer 206b.
  • the seed layer is composed of a heat resistant metal layer 203 and a metal wetting layer 204
  • the heat resistant metal layer 203 is connected to the pad 201
  • the metal wetting layer 204 is stacked on the heat resistant metal layer 203.
  • the material of the heat resistant metal layer 203 is titanium, chromium, ruthenium or a combination thereof.
  • the material of the metal wetting layer 204 is copper, aluminum, nickel or a combination thereof.
  • the material of the adhesion layer 206a is copper, and the thickness of copper is 5 to 50 ⁇ m.
  • the material of the barrier layer 206b is nickel, and the thickness of nickel is 1.5 to 3 ⁇ m.
  • the material of the material 206c is pure tin or a tin alloy, and the thickness of the tantalum 206c is 5 to 70 ⁇ m.
  • the package structure and the method for forming the package structure of the embodiment of the present invention the semiconductor chip is flipped on the inner lead, and the pad on the semiconductor chip is guided by the connection structure formed by the seed layer and the columnar bump block.
  • the foot is electrically connected, so that the entire package structure is small in volume, and the method for forming the package structure can realize the chip size package of the lead frame structure, thereby improving the integration degree of the package structure.

Abstract

一种半导体封装结构，包括：芯片，所述芯片的表面设有焊盘和钝化层，所述钝化层设有裸露所述焊盘的第一开口，所述焊盘上设有种子层和柱状凸点，所述种子层与焊盘相连，所述柱状凸点堆叠于所述种子层上；引线框架，所述引线框架设有若干分立的引脚，内引脚和外引脚设于引脚的相对两面；所述芯片倒装于引线框架上，所述柱状凸点与所述内引脚相连；塑封层，所述塑封层密封所述芯片、柱状凸点和引线框架，并裸露出所述外引脚。所述封装结构占据的横向的面积减小，整个封装结构的体积相应减小，提高了封装结构的集成度。还提供一种半导体封装结构的形成方法。

Description

半导体封装结构及其形成方法
技术领域
本发明涉及半导体封装领域， 尤其涉及一种半导体封装结构及其形 成方法。
背景技术
随着电子产品如手机、笔记本电脑等朝着小型化，便携式， 超薄化， 多媒体化以及满足大众需求的低成本方向发展， 高密度、 高性能、 高可 靠性和低成本的封装形式及其组装技术得到了快速的发展。 与价格昂贵 的 BGA ( Ball Grid Array )等封装形式相比， 近年来快速发展的新型封 装技术， 如四边扁平无引脚 QFN ( Quad Flat No-leadPackage )封装， 由于其具有良好的热性能和电性能、 尺寸小、 成本低以及高生产率等众 多的优点， 引发了微电子封装技术领域的一场新的革命。
图 1为现有的 QFN封装结构的结构示意图， 所述 QFN封装结构包 括： 半导体芯片 14， 所述半导体芯片 1上具有烊盘 2; 引脚 3 (引线框 架）， 所述引脚 3围绕所述半导体芯片 1的四周排列； 金属导线 4， 金属 导线 4将半导体芯片 1的焊盘 2与环绕所述半导体芯片 1的引脚 3电连 接； 塑封材料 5， 所述塑封材料 5将半导体芯片 1、 金属线 4和引脚 3 密封， 引脚 3的表面棵露在塑封材料的底面， 通过引脚 3实现半导体芯 片 1与外部电路的电连接。
现有的封装结构占据的体积较大， 不利于封装结构集成度的提高。
发明内容
本发明解决的问题是怎样提高封装结构的集成度。
为解决上述问题， 本发明提供一种半导体封装结构， 包括： 芯片， 所述芯片的表面设有焊盘和飩化层， 所述飩化层设有棵露所述焊盘的第 一开口， 所述第一开口内设有种子层和柱状凸点， 所述种子层与烊盘相 连， 所述柱状凸点堆叠于所述种子层上； 引线框架， 所述引线框架设有 若干分立的引脚， 内引脚和外引脚设于引脚的相对两面； 所述芯片倒装 于引线框架上， 所述柱状凸点与所述内引脚相连； 塑封层， 所述塑封层 密封所述芯片、 柱状凸点和引线框架， 并棵露出所述外引脚； 所述柱状 凸点自下而上依次由附着层、 阻挡层和焊料堆叠组成， 所述附着层与种 子层相连， 阻挡层堆叠于附着层上， 焊料堆叠于阻挡层上。
本发明还提供一种半导体封装结构的形成方法， 包括： 提供半导体 芯片， 所述芯片的表面设有焊盘和钝化层， 所述钝化层设有棵露所述焊 盘的第一开口； 在芯片的焊盘和钝化层上依次形成耐热金属层和金属浸 润层； 在金属浸润层上形成光刻胶， 所述光刻胶设有曝露出芯片焊盘上 方金属浸润层的第二开口； 在第二开口中的金属浸润层上依次形成附着 层和阻挡层； 在阻挡层上形成焊料； 去除光刻胶； 蚀刻钝化层上的耐热 金属层和金属浸润层至飩化层棵露； 回流焊料， 形成柱状凸点； 提供引 线框架， 所述引线框架设有若干分立的引脚， 内引脚和外引脚设于引脚 的相对两面； 将形成有柱状凸点的芯片倒装于引线框架上， 所述柱状凸 点与所述内引脚电连接； 形成密封所述芯片、 柱状凸点和引线框架， 并 棵露出所述夕卜引脚的塑封层。
与现有技术相比， 本发明的技术方案具有以下优点：
本发明的封装结构是将半导体芯片倒装在引脚上方， 通过柱状凸点 将半导体芯片上的焊盘与内引脚电连接， 使得形成的封装结构占据的横 向的面积减小， 整个封装结构的体积较小， 提高了封装结构的集成度。
附图说明
图 1为现有技术封装结构的结构示意图；
图 2〜图 11为本发明实施例封装结构的形成过程的剖面结构示意图。
具体实施方式
下面结合附图对本发明的具体实施方式做详细的说明。
首先， 参考图 2，提供半导体芯片 200, 所述半导体芯片 200的表面 设有焊盘 201和钝化层 202， 所述钝化层 202设有棵露所述焊盘 201的 第一开口。
所述焊盘 201是芯片 200的功能输出端子， 并最终通过后续形成的 柱状凸点 206实现电性功能的传导过渡；鈍化层 202的材料包括氧化硅、 氮化硅、 氮氧化硅、聚酰亚胺、苯三聚丁烯等介电材料或它们的混合物， 用于保护芯片 200中的线路。
需要说明的是， 所述芯片的焊盘和钝化层可以是芯片的初始焊盘和 初始钝化层， 也可以是根据线路布图设计需要而形成的过渡焊盘、 钝化 层； 形成过渡焊盘、 钝化层的方式主要是采用再布线工艺技术， 通过一 层或多层再布线将初始焊盘、 钝化层转载到过渡焊盘、 钝化层上。 所述 再布线工艺技术为现有成熟工艺， 已为本领域技术人员所熟知， 在此不 再赘述。
接着， 参考图 3， 在芯片 200的烊盘 201和飩化层 202上依次形成 耐热金属层 203和金属浸润层 204。
所述耐热金属层 203的材料可以是钛 Ti、 铬 Cr、 钽 Ta或它们的组 合构成， 本发明优选为 Ti。 所述金属浸润层 204的材料可以是铜 Cu、 铝 Al、 镍 M中的一种或它们的组合构成， 其中较优的金属浸润层 204 为 Cu。 耐热金属层 203与金属浸润层 204—起构成最终结构的种子层。 所述耐热金属层 203和金属浸润层 204的方法同样可以采用现有的蒸发 或溅射或物理气相沉积的方法， 其中较优的方法为溅射。 当然， 根据本 领域技术人员的公知常识， 形成的方法不仅限于溅射方法， 其他适用的 方法均可应用于本发明， 并且形成的耐热金属层 203和金属浸润层 204 的厚度也是根据实际的工艺需求而定。
接着， 参考图 4， 在金属浸润层 204上形成光刻胶 205， 所述光刻胶 205设有曝露出芯片 200焊盘 201上方金属浸润层 204的第二开口。
形成光刻胶 205的方法可以是旋转涂布， 这些方法的具体步骤已为 本领域技术人员所熟知， 在此不再赞述。 形成光刻胶 205后， 具体可通 过现有光刻显影技术定义出烊盘 201的形状， 使光刻胶 205中形成开口 以曝露出焊盘 201上的金属浸润层 204。
在本实施例中， 所述第二开口小于所述第一开口， 即光刻胶 205的 开口尺寸要小于芯片 200的飩化层开口尺寸； 目的是使后续形成的柱状 凸点 206能够落在第一开口内， 避免使柱状凸点 206形成于钝化层 202 上而造成应力过大、 焊盘 201容易脆裂的可靠性问题。
接着， 参考图 5， 在第二开口中的金属浸润层 204上依次形成附着 层 206a和阻挡层 206b。
在这一步驟中， 以芯片 200上剩余的光刻胶 205为掩膜， 在上步中 形成的第二开口内、金属浸润层 204的上方，依次形成附着层 206a和阻 挡层 206b， 具体工艺可以通过用电镀的方式。 当然， 根据本领域技术人 员的公知常识， 形成的方法不仅限于电镀， 其他适用的方法均可应用于 本发明。 所述附着层 206a的材料为铜 Cu， 阻挡层 206b的材料为镍 M。
所述附着层 206a铜的厚度为 5~50μιη, 具体厚度为 5μιη、 10μιη、 15μιη、 20μιη、 25μιη、 30μιη 、 35μιη、 40μιη、 45μιη或 50μιη等。 附着 层 206a为最终电性输出端子即柱状凸点 206的柱状结构主体。 附着层 206a在空间上提供了一个足够的物质空间，保证了后续形成的焊料 206c 在回流后能够牢固地置于附着层 206a上而不会偏离，同时也提高了与焊 料 206c之间的结合力； 同时， 也正因为附着层 206a的柱状结构使得焊 料 206c的尺寸得以缩小，在保证最终产品焊接过程中物理连接可靠度的 前提下， 提升了单位空间内的功能输出端口数， 更能满足密间距、 功能 输出多的封装需求。
所述阻挡层 206b镍的厚度为 1.5μιη~3μιη， 具体厚度为 1.5μιη、 2μιη、 2.5μιη或 3μιη等。 阻挡层 206b的作用为防止后续形成烊料凸点 的材料 散至金属浸润层 204中， 当 M层厚度小于 1.5μιη时， Μ最终 会因相邻金属间的扩散效应而消失， 进而无法有效地阻挡后续焊料凸点 扩散到金属浸润层 204中； 当 Μ层厚度大于 3μιη时，会因 Μ金属本身 的电热性能较差而导致电阻率上升， 进而影响最终产品的电热性能。 因 此， 厚度适宜的阻挡层（Μ )—方面能够避免自身因扩散效应而消失， 进而有效地阻止焊料和金属浸润层之间因金属间化合物的形成而产生的 孔隙； 同时又不至于因镍阻挡层过厚而导致电阻率上升而影响产品的电 热性能。
接着， 参考图 6， 在阻挡层 206b上形成焊料 206c。
在这一步骤中，仍以光刻胶 205为掩膜，在阻挡层 206b上形成彈料 206c, 形成所述焊料 206c的材料为纯锡或锡合金， 如锡银合金、 锡铜合 金、 锡银铜合金等。 形成烊料 206c的方法可以是电解电镀、 溅射、 网版 印刷或直接植入预制好的焊料球等方式， 这些方法的具体步骤已为本领 域技术人员所熟知， 在此不再赘述。
本实施例中， 焊料 206c的厚度为 5μιη~70μιη， 具体厚度例如 5μιη、 10μιη、 15μιη、 20μιη、 25μιη、 30μιη、 35μιη、 40μιη、 45μιη、 50μιη、 55μιη、 60μιη、 65μιη或 70μιη等。 由上述步驟形成的柱状结构， 可以大大减少 焊料 308a的使用量，一方面节约了材料成本，更重要的是少量焊料 206c 回流后的尺寸较小， 能满足絆盘 201密间距或相同空间内更多功能输出 点的应用需求。
接着， 参考图 7, 去除光刻胶 205; 以附着层 206a为掩膜， 蚀刻钝 化层 202上的耐热金属层 203和金属浸润层 204至钝化层棵露。
在完成上述工序后， 光刻胶 205可以去除了， 可以使用湿法或剥离 的方式去除， 这些方法的具体步骤已为本领域技术人员所熟知， 在此不 再赘述。
在本实施例中， 具体可通过喷洒酸液或将晶片浸泡于酸液中的方法 来去除烊料 206c以外的芯片 200表面的金属浸润层 204和耐热金属层 203, 从而曝露出飩化层 202。
接着， 参考图 8， 回流烊料， 形成柱状凸点 206。
在本实施例中，通过回流加热熔化焊料 206c成半球状，构成了由附 着层 206a、 阻挡层 206b和焊料 206c组成的柱状凸点 206, 此时， 芯片 200的功能输出端子由烊盘 201过渡到柱状凸点 206上， 柱状凸点 206 成为了芯片 200的电性输出端。
接着， 参考图 9,提供引线框架 300， 所述引线框架 300设有若干分 立的引脚， 内引脚 301和外引脚 302设于引脚的相对两面。
所述引线框架 300釆用沖切或蚀刻工艺形成， 内引脚 301作为引脚 的电性输入端与有源器件或无源器件相连， 外引脚作为电性输出端与下 一级封装如印刷线路板等进行互连。
接着， 参考图 10， 将形成有柱状凸点 206的芯片 200倒装于引线框 架 300上， 所^^状凸点 206与所述内引脚 301电连接。
通过柱状凸点 206将芯片 200上的烊盘 201与内引脚 301电连接， 使得形成的封装结构占据的横向的面积减小，整个封装结构的体积较小， 提高了封装结构的集成度。 同时， 与传统通过金属引线将焊盘 201与内 引脚 301互连的方式相比， 本发明的倒装结构大大缩短了芯片 200与内 引脚 201间的传输距离， 电阻、 热阻也相应降低， 从而提升了整个产品 的性能， 作为芯片 200输出端的柱状凸点 206也更能满足大功率产品的 要求。
柱状凸点 206与内引脚 301互连后， 还需经过回流工艺， 回流工艺 具有固化烊料、 校准对位的功能， 使柱状凸点 206与内引脚 301之间能 够精确对位并且固定。
然后， 请参考图 11， 形成密封所述芯片 200、 柱状凸点 206和引线 框架 300， 并棵露出外引脚 302的塑封层 400。
所述塑封层 400包围所述芯片 200、 填充芯片 200和内引脚 301之 间的区域， 塑封层 400还填充满引脚之间的开口， 塑封层 400的底部暴 露出外引脚 302。 填充塑封层 400时， 由于引脚间的开口与芯片 200之 间的空间以及芯片 200与内引脚 301之间的空间是相通的， 提高了塑封 材料的流动性， 从而防止在塑封层 400中产生空隙等缺陷。
所述塑封层 400用于保护和隔离封装结构， 所述塑封层 400的材料 为树脂， 所述树脂可以为环氧树脂、 聚酰亚胺树脂、 苯并环丁烯树脂或 聚苯并恶唑树脂； 所述树脂也可以为为聚对苯二甲酸丁二酯、聚碳酸酯、 苯二曱酸乙二醇酯、 聚乙烯、 聚丙烯、 聚烯烃、 聚氨酯、 聚烯烃、 聚醚砜、 聚酰胺、 聚亚氨酯、 乙烯-醋酸乙烯共聚物或聚乙烯醇； 所述塑 封层 400还可以为其他合适的塑封材料。
所述塑封层 400 的形成工艺为注塑工艺或转塑工艺 （transfer moldin )0 所述塑封层 400的形成工艺还可以为其他合适的工艺。
形成塑封层 400后， 还包括， 采用切割工艺分割塑封层 400， 形成 多个分立的半导体封装单元。
上述方法形成的封装结构， 请参考图 11， 包括：
芯片 200，所述芯片 200的表面设有烊盘 201和钝化层 202，所述飩 化层 202设有裸露所述焊盘 201的第一开口， 所述第一开口内设有种子 层和柱状凸点 206, 所述种子层与焊盘 201相连， 所述柱状凸点 206堆 叠于所述种子层上；
引线框架 300， 所述引线框架设有若干分立的引脚， 内引脚 301和 外引脚 302设于引脚的相对两面；
所述芯片 200倒装于引线框架 300上， 所述柱状凸点 206与所述内 引脚 301相连；
塑封层 400，所述塑封层 400密封所述芯片 200、柱状凸点 206和引 线框架 300， 并棵露出所述外引脚 302;
所述柱状凸点 206 自下而上依次由附着层 206a、 阻挡层 206b和焊 料 206c堆叠组成，所述附着层 206a与种子层相连， 阻挡层 206b堆叠于 附着层 206a上， 烊料 206c堆叠于阻挡层 206b上。
具体的，所述种子层由耐热金属层 203和金属浸润层 204堆叠组成， 所述耐热金属层 203与焊盘 201相连， 所述金属浸润层 204堆叠于所述 耐热金属层 203上。
所述耐热金属层 203的材料是钛、 铬、 钽或它们的组合。
所述金属浸润层 204的材料是铜、 铝、 镍或它们的组合。
所述附着层 206a的材料是铜， 铜的厚度是 5~50μιη。
所述阻挡层 206b的材料是镍， 镍的厚度是 1.5~3μιη。
所述烊料 206c的材质是纯锡或锡合金，烊料 206c的厚度是 5~70μιη。 综上， 本发明实施例的封装结构及其封装结构的形成方法， 将半导 体芯片倒装在内引脚上， 通过种子层和柱状凸点块构成的连接结构将半 导体芯片上的焊盘与引脚电连接， 使得整个封装结构的体积较小， 并且 该封装结构的形成方法能实现引线框结构的芯片尺寸级封装， 提高了封 装结构的集成度。
虽然本发明以较佳实施例披露如上， 但本发明并非限定于此。 任何 本领域技术人员， 在不脱离本发明的精神和范围内， 均可作各种更动与 修改， 因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims

1. 一种半导体封装结构， 其特征在于， 包括：
芯片， 所述芯片的表面设有焊盘和飩化层， 所述飩化层设有棵露所 述蜉盘的第一开口， 所述第一开口内设有种子层和柱状凸点， 所述种子 层与焊盘相连， 所述柱状凸点堆叠于所述种子层上；
权
引线框架， 所述引线框架设有若干分立的引脚， 内引脚和外引脚设 于引脚的相对两面；
所述芯片倒装于引线框架上， 所述柱状凸点与所述内引脚相连； 塑封层， 所述塑封层密封所述芯片、 柱状凸点和引线框架， 并裸露 出所述外引脚；
所述柱状凸点自下而上依次由附着层、 阻挡层和焊料堆叠组成， 所 述附着层与种子层相连， 阻挡层堆叠于附着层上书，焊料堆叠于阻挡层上。
2.根据权利要求 1所述的一种半导体封装结构， 其特征在于， 所述 种子层由耐热金属层和金属浸润层堆叠组成， 所述耐热金属层与焊盘相 连， 所述金属浸润层堆叠于所述种子层上。
3.根据权利要求 2所述的一种半导体封装结构， 其特征在于， 所述 耐热金属层的材料是钛、 铬、 钽或它们的组合。
4.根据权利要求 2所述的一种半导体封装结构， 其特征在于， 所述 金属浸润层的材料是铜、 铝、 镍或它们的组合。
5.根据权利要求 1所述的一种半导体封装结构， 其特征在于， 所述 附着层的材料是铜。
6.根据权利要求 5所述的一种半导体封装结构， 其特征在于， 所述 铜附着层的厚度是 5~50μιη。
7.根据权利要求 1所述的一种半导体封装结构， 其特征在于， 所述 阻挡层的材料是镍。
8.根据权利要求 7所述的一种半导体封装结构， 其特征在于， 所述 镍阻挡层的厚度是 1.5~3μιη。
9.根据权利要求 1所述的一种半导体封装结构， 其特征在于， 所述 焊料的材质是纯锡或锡合金。
10.根据权利要求 9所述的一种半导体封装结构， 其特征在于， 所 述焊料的厚度是 5~70μιηο
11. 一种半导体封装结构的形成方法， 其特征在于， 包括： 提供半导体芯片， 所述芯片的表面设有焊盘和钝化层， 所述钝化层 设有棵露所述焊盘的第一开口；
在芯片的焊盘和钝化层上依次形成耐热金属层和金属浸润层； 在金属浸润层上形成光刻胶， 所述光刻胶设有曝露出芯片焊盘上方 金属浸润层的第二开口；
在第二开口中的金属浸润层上依次形成附着层和阻挡层； 在阻挡层上形成烊料；
去除光刻胶；
蚀刻钝化层上的耐热金属层和金属浸润层至钝化层棵露；
回流焊料， 形成柱状凸点；
提供引线框架， 所述引线框架设有若干分立的引脚， 内引脚和外引 脚设于引脚的相对两面；
将形成有柱状凸点的芯片倒装于引线框架上， 所述柱状凸点与所述 内引脚电连接；
形成密封所述芯片、 柱状凸点和引线框架， 并棵露出所述夕卜引脚的 塑封层。
12.根据权利要求 11所述的一种半导体封装结构的形成方法， 其特 征在于， 所述第二开口小于所述第一开口。
13.根据权利要求 11所述的一种半导体封装结构的形成方法， 其特 征在于， 所述耐热金属层的材料是钛、 铬、 钽或它们的组合。
14.根据权利要求 11所述的一种半导体封装结构的形成方法， 其特 征在于， 所述金属浸润层的材料是铜、 铝、 镍或它们的组合。
15.根据权利要求 11所述的一种半导体封装结构的形成方法， 其特 征在于， 所述附着层的材料是铜。
16.根据权利要求 15所述的一种半导体封装结构的形成方法，其特 征在于， 所述铜附着层的厚度是 5~50μιη。
17.根据权利要求 11所述的一种半导体封装结构的形成方法， 其特 征在于， 所述阻挡层的材料是镍。
18.根据权利要求 17所述的一种半导体封装结构的形成方法，其特 征在于， 所述镍阻挡层的厚度是 1.5~3μιη。
19.根据权利要求 11所述的一种半导体封装结构的形成方法， 其特 征在于， 所述焊料的材质是纯锡或锡合金。
20. 根据权利要求 19所述的一种半导体封装结构的形成方法，其特 征在于， 所述焊料的厚度是 5~70μιη。
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