US20120313234A1 - Qfn package and manufacturing process thereof - Google Patents
Qfn package and manufacturing process thereof Download PDFInfo
- Publication number
- US20120313234A1 US20120313234A1 US13/158,124 US201113158124A US2012313234A1 US 20120313234 A1 US20120313234 A1 US 20120313234A1 US 201113158124 A US201113158124 A US 201113158124A US 2012313234 A1 US2012313234 A1 US 2012313234A1
- Authority
- US
- United States
- Prior art keywords
- conductive layer
- lead frame
- leads
- chip
- qfn package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 25
- 239000002131 composite material Substances 0.000 claims abstract description 59
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 39
- 239000011159 matrix material Substances 0.000 claims description 28
- 229910000679 solder Inorganic materials 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- 238000005538 encapsulation Methods 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 4
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 239000011701 zinc Substances 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 2
- 229920001187 thermosetting polymer Polymers 0.000 claims description 2
- 229910052718 tin Inorganic materials 0.000 claims description 2
- 239000011135 tin Substances 0.000 claims description 2
- 238000002844 melting Methods 0.000 description 6
- 230000008018 melting Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000000289 melt material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920002492 poly(sulfone) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Definitions
- the present invention relates to a QFN package and manufacturing process thereof, and more particularly, to a QFN package with composite bumps.
- Packaging processes have been widely used to electrically connect a semiconductor chip to an external component with a better reliability and also to protect the semiconductor chip from damages caused by external conditions.
- packaging materials and the packaging processes used are not only associated with the manufacturing cost, but also have an influence on operational performance of the packaged chip. For this reason, the packaging structure and materials thereof selected for use become very important.
- Quad Flat No-Leaded (QFN) semiconductor packages have achieved wide popularity in recent years because of their smaller package size.
- a chip is electrically connected to a lead frame by wire, with each bond pad of the chip being electrically connected to a corresponding lead of the lead frame respectively.
- a flip chip QFN package 10 a chip 101 is electrically connected to a lead frame 103 by bumps 105 as shown in FIG. 1A or FIG. 1C .
- the chip 101 is flipped and bonded on the lead frame 103 by solder joining of solder bump ( FIG. 1A ) or copper pillar with solder cap.
- the lead width will be limited to enough space for avoid the melting solder over flow to the opposite side of lead during the reflow process ( FIG. 1B ). That melting solder 107 over flow on the opposite side of lead will induce assembly defect of further process, for example encapsulation, or SMT (Surface Mount Technology).
- the lead width may not be designed with enough space to avoid the melting solder over flow.
- the primary objective of the present invention is to provide a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant.
- the chip has a plurality of pads
- the lead frame has a plurality of leads.
- a semi-cured encapsulant is formed in the spaces between the leads of the lead frame before the chip is bonded to the lead frame.
- Each of the plurality of composite bumps has a first conductive layer and a second conductive layer.
- the first conductive layer is electrically connected between one of the pads and the second conductive layer
- the second conductive layer is electrically connected between the first conductive layer and one of the leads.
- the encapsulant encapsulates the chip, the leads and the composite bumps.
- the manufacturing process of the present invention comprises the following steps of: forming a plurality of lead frame module; forming a plurality of chip modules, each having a chip being connected with a plurality of composite bumps; bonding the lead frame modules to the chip modules by connecting the composite bumps to the leads respectively; and forming a plurality of QFN packages by encapsulating and singulating the chip modules and the lead frame modules.
- the step of forming a plurality of lead frame modules comprises the following steps of: forming an upper unit by semi cured encapsulant onto a top carrier; forming a lower unit by disposing a matrix lead frame on a bottom carrier, wherein the matrix lead frame comprises a plurality of leads; bonding the upper unit and the lower unit by laminating the semi cured encapsulant with the matrix lead frame to have the leads be in contact with the top carrier; forming the plurality of lead frame modules by fully curing the encapsulant and removing the top carrier to make sure the top surface of lead is not lower than the encapsulant.
- the step of bonding the lead frame modules to the chip modules may be proceeded by one of thermo-ultrasonic bonding, reflowing and applying conductive paste.
- the present invention provides the following benefits: the QFN package and a manufacturing process thereof of the present invention replaces the conventional bumps with the composite bumps and a encapsulated matrix lead frame, so the pitch between and the height of the composite bumps of the QFN package could be controlled, and the short interconnection loop formed by the composite bumps could reduce the resistance and inductance and improve the performance of the whole QFN package.
- FIG. 1A to FIG. 1C are schematic views of conventional flip chip QFN packages
- FIG. 2B is a cross sectional view of another QFN package structure in accordance with a preferred embodiment of the present invention.
- FIG. 3A to FIG. 3E are schematic views illustrating a manufacturing process of a lead frame module of a QFN package in accordance with an embodiment of the present invention.
- FIG. 4A to FIG. 4C are schematic views illustrating a manufacturing process of a chip, electrically connected with plural composite bumps, of a QFN package in accordance with an embodiment of the present invention
- FIG. 5A to FIG. 5B are schematic views illustrating a manufacturing process of a QFN package in accordance with an embodiment of the present invention
- FIG. 6 is a schematic view of a matrix lead frame of the present invention.
- FIG. 7 is a cross sectional view of a composite bump in accordance with another aspect of the preferred embodiment of the present invention.
- FIG. 8 is a cross sectional view of a chip in accordance with another aspect of the preferred embodiment of the present invention.
- the QFN package 1 comprises a chip 11 , a lead frame 13 , a plurality of composite bumps 15 and an encapsulant 17 .
- the chip 11 has an active surface 113 , a plurality of pads 111 and a passivation layer.
- the pads 111 are formed on the active surface 113 of the chip 11 . More specifically, the pads 111 are arranged at four sides of the active surface 113 , and the pads 111 may be only arranged at two parallel sides of the active surface 113 in other aspects. Each of the pads 111 is partially covered by the passivation layer 115 , and some portion of each of the pads 111 is exposed for electrical connection thereby.
- the chip 11 may be, for example, a display driver circuit IC, an image sensor IC, a memory IC, a logic IC, an analog IC, an ultra-high frequency (UHF) or a radio frequency (RF) IC, but it is not limited thereto.
- a display driver circuit IC an image sensor IC
- a memory IC a memory IC
- a logic IC an analog IC
- UHF ultra-high frequency
- RF radio frequency
- the lead frame 13 has a plurality of leads 131 , which are arranged at four sides to form a square in this embodiment (not shown).
- Each lead 131 has an inner lead portion 131 a and an outer lead portion 131 b .
- Each of the inner lead portions 131 a and each of the outer lead portions 131 b have a height difference that the inner lead portions 131 a are higher than the outer lead portions 131 b as shown in FIG. 2A .
- the composite bumps 15 are electrically connected between the chip 11 and the lead frame 13 .
- Each composite bump 15 has a first conductive layer 151 and a second conductive layer 153 , and the second conductive layer 153 is softer than the first conductive layer 151 .
- the first conductive layer 151 is electrically connected between a corresponding pad 111 of the pads 111 of the chip 11 and the second conductive layer 153 .
- the second conductive layer 153 is electrically connected between the first conductive layer 151 and a corresponding inner lead portion 131 a of the inner lead portions 131 a of the leads 131 of the lead frame 13 .
- the composite bumps 15 electrically connect to the pads 111 of the chip 11 with the first conductive layers, and the composite bumps 15 electrically connect to the inner lead portions 131 a of the leads 131 of the lead frame 13 with the second conductive layers 153 .
- the first conductive layer 151 may be made of a material selected from a group consisting of copper, nickel, aluminum, zinc, and combinations thereof.
- the second conductive layer 153 may be made of a material selected from a group consisting of gold, copper, silver, tin, zinc, indium, and combinations thereof.
- the second conductive layer 153 made of gold forms a thickness which is at least less than a half of the total height of the composite bump 15 . The reduction of gold results in reducing the manufacture cost.
- the composite bumps 15 disclosed above are only provided as an example, and as may be appreciated by those of ordinary skill in the art, the composite bumps 15 may also be “composite” bump structures formed by other existing bumps in combination (for example, the composite bumps are formed by two layers of stud bumps) to satisfy different demands for electrical connection between different kinds of flip chips and the substrate and to lower the manufacturing cost by reducing use of gold.
- the encapsulant 17 encapsulates the chip 11 , the leads 131 and the composite bumps 15 .
- the encapsulant 17 is formed around the chip 11 and the composite bumps 15 and covers almost the whole surface of the lead frame 13 except for the bottom surface of outer lead portion 131 b of lead 131 of lead frame 13 thereof.
- the material of the encapsulant 17 is a material of which may be selected from thermoplastic resins such as acrylic resins, polyimide resins or polysulfone resins, or thermosetting resins such as epoxy resins, phenolic resins, tripolycyanamide resins or polyester resins, or combinations thereof.
- the encapsulant 17 is preferably made of low coefficient of thermal expansion (CTE) and low modulus material.
- each of the composite bumps 15 connects to the top surface of the corresponding inner lead portion 131 a of the lead 131 of the lead frame 13 by thermo-ultrasonic bonding, reflowing, or applying conductive paste therebetween.
- the composite bumps 15 connect to the leads 131 by thermo-ultrasonic bonding.
- the QFN package further comprises a plurality of plated structures, one of which is adhered between the second conductive layer and the lead for connecting each of the composite bumps to the corresponding inner lead portion of the lead of the lead frame by reflowing.
- the encapsulant of such modification would not have any encapsulation interface.
- the plated structure is solder or a copper pillar with a solder cap.
- the QFN package further comprises a plurality of conductive paste, respectively disposed between and adhering each of the composite bumps and a corresponding lead of the leads.
- the conductive paste may be silver paste or solder. Neither the encapsulant of such modification would have any encapsulation interface.
- the present invention further provides a QFN package 1 ′, which adopts specific manufacturing process and would be describe in detail later, further has an encapsulation interface 19 which is not higher than a top surface of the lead frame 13 as shown in FIG. 2B .
- the encapsulant 17 is only formed around the chip and the composite bump, fully cured encapsulant 17 ′ is formed around the leads 131 of the lead frames 13 under the encapsulant 17 , and the interface between the encapsulant 17 and the fully cured encapsulant 17 ′ is the encapsulation interface 19 .
- FIG. 3A As shown therein, forming an upper unit 3 a by forming a semi cured encapsulant 17 ′′ onto a top carrier 41 is executed.
- a top carrier 41 could be metal, glass, organic film, or plastic, which could provide a flat surface and appropriate strength for the semi cured encapsulant 17 ′′.
- FIG. 3B shows that a lower unit 3 b is formed by disposing a matrix lead frame 6 (as shown in FIG. 6 ) on a bottom carrier 31 , which could be organic film, glass, plastic, or metal.
- a matrix lead frame 6 as shown in FIG. 6
- the matrix lead frame 6 comprises a plurality of lead frames 13 , each of the lead frames 13 comprises a plurality leads 131 , and each lead 131 has an inner lead portion 131 a and an outer lead portion 131 b .
- Appropriate adhesion between the bottom carrier 31 and the lead frame 13 is necessary for further process. It should be noted that the executing priority of the processes illustrated in FIG. 3A and FIG. 3B are not limited.
- FIG. 3C features that bonding the upper unit 3 a and the lower unit 3 b by laminating the semi cured encapsulant 17 ′′ with the matrix lead frame to have the leads 131 be in contact with the top carrier 41 .
- the top carrier 41 contacts the top surface of the inner lead portions 131 a of the leads 131 . Since the semi cured encapsulant 17 ′′ is partially cured and is a semifluid substance, the leads 131 would be enclosed except for the top surface of the inner lead portions 131 a and the bottom surface of the outer lead portions 131 b.
- a lead frame module 3 d (or 3 e shown in FIG. 3E ) on each lead frame 13 of the matrix lead frame by fully cured the semi cured encapsulant 17 ′′ to fully cured encapsulant 17 ′ and removing the top carrier 41 .
- the top surface of the fully cured encapsulant 17 ′ may be as high as (or lower than shown in FIG. 3E ) the top surface of the inner lead portions 131 a of the leads 131 .
- the lead frame module 3 d (or 3 e shown in FIG. 3E ) on the matrix lead frame is formed.
- a wafer 30 is provided.
- the wafer 30 is formed with internal circuits, an active surface 113 , a plurality of pads 111 and a passivation layer 115 .
- the pads 111 are disposed on the active surface 113 and are partially covered by the passivation layer 115 to provide exposed areas (or named “openings”). Signals would be transmitted from or to the internal circuits through the exposed areas of the pads 111 .
- each of the composite bumps 15 comprises a first conductive layer 151 and a second conductive layer 153 , and the first conductive layer 151 is directly connected to and disposed between a corresponding pad 111 of the pads 111 and the second conductive layer 153 .
- the internal circuits of the wafer 30 and the composite bumps 15 are electrically connected via the exposed areas of the pads 111 .
- the wafer 30 is saw to provide a plurality of chips 11 , each of which is electrically connected with plural composite bumps 15 .
- other existing processes for composite bumps may also be applied in the present invention, and this will not be further described herein.
- a plurality of lead frame module which is disposed and formed on the matrix lead frame 6 on a bottom carrier 31 , is provided according to the steps FIGS. 3A-3E .
- the matrix lead frame 6 (as shown in FIG. 6 ) comprises a plurality of lead frames 13 , and each of the lead frames 13 has a plurality of leads 131 as depicted above. And the leads 131 of the matrix lead frame 13 are enclosed with the fully cured encapsulant 17 ′ except for the top surface of the inner lead portions 131 a and the bottom surface of the outer lead portions 131 b .
- each of the chips 11 is electrically connected to a part of the leads 131 of the matrix lead frame by a plurality of composite bumps 15 .
- the second conductive layer 153 of each composite bump 15 is directly connected to the top surface of the inner lead portion 131 a of the corresponding lead 131 of the lead frame 13 by thermo-ultrasonic bonding, reflowing or applying conductive paste. It is known that there would be solder between the composite bumps 15 and the inner leads 131 a , and such solder is not shown in FIG. 5A if reflow is applied.
- the chip 11 , the lead frames 13 on the matrix lead frame and the composite bumps 15 are encapsulated.
- the encapsulant 17 is formed around the chip 11 and the composite bumps 15 and covers almost the whole surface of the lead frame 13 except for the bottom surface of outer lead portion 131 b of lead 131 by transfer molding, screen printing, coating, or injection, etc.
- the encapsulation interface 19 would be formed in such case, no matter whether the encapsulant 17 is the same material as the fully cured encapsulant 17 ′ or not.
- singulating the matrix lead frame and stripping off the bottom carrier 31 to the QFN packages 1 is executed as shown in FIG. 2 .
- the QFN package 1 comprises one of the encapsulated chips 11 and a part of the encapsulated matrix lead frame.
- thermo-ultrasonic bonding there would be thermal stress arisen after thermo-ultrasonic boding, and the top surface of the inner lead portion 131 a would be not bent, cracked or even fractured. And no more melting solder overflows in the present invention
- the composite bump may further comprise at least an under bump metallization (UBM) layer, or a covering third conductive layer and a barrier layer.
- UBM under bump metallization
- the chip 11 is electrically connected to plural composite bumps through plural pads 111 .
- Each of the composite bumps 2 comprises an under bump metallization (UBM) layer 21 , a first conductive layer 23 , a second conductive layer 25 , a covering third conductive layer 27 and a barrier layer 29 .
- the UBM layer 21 is disposed between the first conductive layer 23 and the pad 111 of the chip 11 .
- the first conductive layer 23 is located on the UBM layer 21
- the second conductive layer 25 is in turn located on the first conductive layer 23 .
- the covering third conductive layer 27 that covers the surface each of the composite bumps 2 , which includes the second conductive layer 25 , and the first conductive layer 23 .
- the barrier layer 29 located between the first conductive layer 23 and the second conductive layer 25 .
- the UBM layer 21 may be made of a material selected from titanium, tungsten, copper, gold, and alloys thereof.
- the covering third conductive layer 27 may be made of gold, but it is not limited thereto.
- the barrier layer 29 may be made of nickel, but it is not limited thereto.
- the step of forming the wafer 30 shown in FIG. 4A may further comprises the following steps of forming a redistribution layer (RDL) 51 on each of the pads 111 of the chips 11 for electrical connection between the first conductive layer 151 of each of the composite bumps 2 ; and forming the composite bump 15 by forming a first conductive layer 151 on each of the RDL layers 51 and forming a second conductive layer 153 on the first conductive layer 151 to re-layout the bump position as shown in FIG. 8 .
- RDL redistribution layer
- the pitch between and the height of the composite bumps 15 of the QFN package 1 could be controlled, and the short interconnection loop formed by the composite bumps 15 could reduce the resistance and inductance and improve the performance of the whole QFN package.
- pre-molding the lead frame could avoid the different leveling issue of inner lead portions and protect the lead surface.
Abstract
The present invention provides a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant is forming between the spaces of leads of lead frame before chip bonded to the lead frame are provided.
Description
- Not applicable.
- 1. Field of the Invention
- The present invention relates to a QFN package and manufacturing process thereof, and more particularly, to a QFN package with composite bumps.
- 2. Descriptions of the Related Art
- Semiconductor packaging processes have been widely used to electrically connect a semiconductor chip to an external component with a better reliability and also to protect the semiconductor chip from damages caused by external conditions. However, packaging materials and the packaging processes used are not only associated with the manufacturing cost, but also have an influence on operational performance of the packaged chip. For this reason, the packaging structure and materials thereof selected for use become very important.
- Among several package technologies, Quad Flat No-Leaded (QFN) semiconductor packages have achieved wide popularity in recent years because of their smaller package size. In a conventional QFN semiconductor package, a chip is electrically connected to a lead frame by wire, with each bond pad of the chip being electrically connected to a corresponding lead of the lead frame respectively. As to a flip
chip QFN package 10, achip 101 is electrically connected to alead frame 103 bybumps 105 as shown inFIG. 1A orFIG. 1C . Thechip 101 is flipped and bonded on thelead frame 103 by solder joining of solder bump (FIG. 1A ) or copper pillar with solder cap. Due to reflow for melting the solder bump or solder cap on copper pillar to solder join thebump 105 ofchip 101 and lead oflead frame 103, the lead width will be limited to enough space for avoid the melting solder over flow to the opposite side of lead during the reflow process (FIG. 1B ). That melting solder 107 over flow on the opposite side of lead will induce assembly defect of further process, for example encapsulation, or SMT (Surface Mount Technology). - Unfortunately, sometimes limitation of chip size and package size, the lead width may not be designed with enough space to avoid the melting solder over flow. In view of this, it is highly desirable in the art to provide a solution that can improve the limitation of lead width and also provide a lower the manufacturing cost of a packaging structure.
- The primary objective of the present invention is to provide a Quad Flat Non-leaded (QFN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. A semi-cured encapsulant is formed in the spaces between the leads of the lead frame before the chip is bonded to the lead frame. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant, formed in the spaces between the leads of the lead frame before the chip is bonded to the lead frame, are provided.
- To provide the aforesaid QFN package, the manufacturing process of the present invention comprises the following steps of: forming a plurality of lead frame module; forming a plurality of chip modules, each having a chip being connected with a plurality of composite bumps; bonding the lead frame modules to the chip modules by connecting the composite bumps to the leads respectively; and forming a plurality of QFN packages by encapsulating and singulating the chip modules and the lead frame modules.
- When adapting thermo-ultrasonic bonding, the step of forming a plurality of lead frame modules comprises the following steps of: forming an upper unit by semi cured encapsulant onto a top carrier; forming a lower unit by disposing a matrix lead frame on a bottom carrier, wherein the matrix lead frame comprises a plurality of leads; bonding the upper unit and the lower unit by laminating the semi cured encapsulant with the matrix lead frame to have the leads be in contact with the top carrier; forming the plurality of lead frame modules by fully curing the encapsulant and removing the top carrier to make sure the top surface of lead is not lower than the encapsulant. It should be noted that the step of bonding the lead frame modules to the chip modules may be proceeded by one of thermo-ultrasonic bonding, reflowing and applying conductive paste.
- As compared to the prior art, the present invention provides the following benefits: the QFN package and a manufacturing process thereof of the present invention replaces the conventional bumps with the composite bumps and a encapsulated matrix lead frame, so the pitch between and the height of the composite bumps of the QFN package could be controlled, and the short interconnection loop formed by the composite bumps could reduce the resistance and inductance and improve the performance of the whole QFN package.
- The detailed technology and preferred embodiments implemented for the subject invention are described in the following paragraphs accompanying the appended drawings for people skilled in this field to well appreciate the features of the claimed invention.
-
FIG. 1A toFIG. 1C are schematic views of conventional flip chip QFN packages; -
FIG. 2A is a cross sectional view of a QFN package structure in accordance with a preferred embodiment of the present invention; -
FIG. 2B is a cross sectional view of another QFN package structure in accordance with a preferred embodiment of the present invention; -
FIG. 3A toFIG. 3E are schematic views illustrating a manufacturing process of a lead frame module of a QFN package in accordance with an embodiment of the present invention; and -
FIG. 4A toFIG. 4C are schematic views illustrating a manufacturing process of a chip, electrically connected with plural composite bumps, of a QFN package in accordance with an embodiment of the present invention; -
FIG. 5A toFIG. 5B are schematic views illustrating a manufacturing process of a QFN package in accordance with an embodiment of the present invention; -
FIG. 6 is a schematic view of a matrix lead frame of the present invention; -
FIG. 7 is a cross sectional view of a composite bump in accordance with another aspect of the preferred embodiment of the present invention; and -
FIG. 8 is a cross sectional view of a chip in accordance with another aspect of the preferred embodiment of the present invention. - In the following descriptions, this invention will be explained with reference to embodiments thereof, which relate to a QFN package and a manufacturing process thereof. However, these embodiments are not intended to limit this invention to any specific environment, applications or particular implementations described in these embodiments. Therefore, descriptions of these embodiments are only for illustration purposes rather than limitation. It should be appreciated that in the following embodiments and the attached drawings, elements unrelated to this invention are omitted from depiction; and dimensional relationships among individual elements in the attached drawings are depicted in an exaggerative way for ease of understanding.
- Referring to
FIG. 2A , a preferred embodiment of a Quad Flat Non-leaded (QFN)package 1 in accordance with the present invention is shown therein. TheQFN package 1 comprises achip 11, alead frame 13, a plurality ofcomposite bumps 15 and anencapsulant 17. - The
chip 11 has anactive surface 113, a plurality ofpads 111 and a passivation layer. Thepads 111 are formed on theactive surface 113 of thechip 11. More specifically, thepads 111 are arranged at four sides of theactive surface 113, and thepads 111 may be only arranged at two parallel sides of theactive surface 113 in other aspects. Each of thepads 111 is partially covered by thepassivation layer 115, and some portion of each of thepads 111 is exposed for electrical connection thereby. In the present invention, thechip 11 may be, for example, a display driver circuit IC, an image sensor IC, a memory IC, a logic IC, an analog IC, an ultra-high frequency (UHF) or a radio frequency (RF) IC, but it is not limited thereto. - The
lead frame 13 has a plurality ofleads 131, which are arranged at four sides to form a square in this embodiment (not shown). Eachlead 131 has aninner lead portion 131 a and anouter lead portion 131 b. Each of theinner lead portions 131 a and each of theouter lead portions 131 b have a height difference that theinner lead portions 131 a are higher than theouter lead portions 131 b as shown inFIG. 2A . - The composite bumps 15 are electrically connected between the
chip 11 and thelead frame 13. Eachcomposite bump 15 has a firstconductive layer 151 and a secondconductive layer 153, and the secondconductive layer 153 is softer than the firstconductive layer 151. The firstconductive layer 151 is electrically connected between acorresponding pad 111 of thepads 111 of thechip 11 and the secondconductive layer 153. The secondconductive layer 153 is electrically connected between the firstconductive layer 151 and a correspondinginner lead portion 131 a of theinner lead portions 131 a of theleads 131 of thelead frame 13. As a result, the composite bumps 15 electrically connect to thepads 111 of thechip 11 with the first conductive layers, and the composite bumps 15 electrically connect to theinner lead portions 131 a of theleads 131 of thelead frame 13 with the secondconductive layers 153. The firstconductive layer 151 may be made of a material selected from a group consisting of copper, nickel, aluminum, zinc, and combinations thereof. The secondconductive layer 153 may be made of a material selected from a group consisting of gold, copper, silver, tin, zinc, indium, and combinations thereof. The secondconductive layer 153 made of gold forms a thickness which is at least less than a half of the total height of thecomposite bump 15. The reduction of gold results in reducing the manufacture cost. - It shall be noted that, the composite bumps 15 disclosed above are only provided as an example, and as may be appreciated by those of ordinary skill in the art, the composite bumps 15 may also be “composite” bump structures formed by other existing bumps in combination (for example, the composite bumps are formed by two layers of stud bumps) to satisfy different demands for electrical connection between different kinds of flip chips and the substrate and to lower the manufacturing cost by reducing use of gold.
- The
encapsulant 17 encapsulates thechip 11, theleads 131 and the composite bumps 15. In this embodiment, theencapsulant 17 is formed around thechip 11 and the composite bumps 15 and covers almost the whole surface of thelead frame 13 except for the bottom surface ofouter lead portion 131 b oflead 131 oflead frame 13 thereof. The material of theencapsulant 17 is a material of which may be selected from thermoplastic resins such as acrylic resins, polyimide resins or polysulfone resins, or thermosetting resins such as epoxy resins, phenolic resins, tripolycyanamide resins or polyester resins, or combinations thereof. Furthermore, theencapsulant 17 is preferably made of low coefficient of thermal expansion (CTE) and low modulus material. - Each of the composite bumps 15 connects to the top surface of the corresponding
inner lead portion 131 a of thelead 131 of thelead frame 13 by thermo-ultrasonic bonding, reflowing, or applying conductive paste therebetween. In this embodiment, the composite bumps 15 connect to theleads 131 by thermo-ultrasonic bonding. In another aspect of the present invention, the QFN package further comprises a plurality of plated structures, one of which is adhered between the second conductive layer and the lead for connecting each of the composite bumps to the corresponding inner lead portion of the lead of the lead frame by reflowing. The encapsulant of such modification would not have any encapsulation interface. The plated structure is solder or a copper pillar with a solder cap. Moreover, in a further aspect of the present invention, the QFN package further comprises a plurality of conductive paste, respectively disposed between and adhering each of the composite bumps and a corresponding lead of the leads. The conductive paste may be silver paste or solder. Neither the encapsulant of such modification would have any encapsulation interface. - It should be noted that there would be thermal stress arisen after thermo-ultrasonic boding, and the top surface of the
inner lead portion 131 a would be bent, cracked or even fractured. Meanwhile, if a low melting temperature soft melt material is applied for solder (not shown) to join thebump 15 andinner lead portion 131 a oflead 131 oflead frame 13, the soft melt material would overflow and induce some defects in further assembly process. To avoid such defects, the present invention further provides aQFN package 1′, which adopts specific manufacturing process and would be describe in detail later, further has anencapsulation interface 19 which is not higher than a top surface of thelead frame 13 as shown inFIG. 2B . In more detail, theencapsulant 17 is only formed around the chip and the composite bump, fully curedencapsulant 17′ is formed around theleads 131 of the lead frames 13 under theencapsulant 17, and the interface between the encapsulant 17 and the fully curedencapsulant 17′ is theencapsulation interface 19. - Hereinbelow, the manufacturing process for manufacturing the QFN packages of the abovementioned embodiment of the present invention will be detailed with reference to the above descriptions, the attached drawings
FIGS. 3A-3E , 4A-4C, 5A-5B. It shall be noted that, for simplicity of the description, the manufacturing process for manufacturing the QFN packages will be described with only one chip as a representative example in the following descriptions and the attached drawings, and the material or related description of the elements is the same as above-mentioned and is omitted. - Instead of providing a matrix lead frame in the well-known manufacturing process of QFN packages, a plurality of lead frame modules are provided by pre-molding in this specific manufacturing process. Referring to
FIG. 3A , as shown therein, forming anupper unit 3 a by forming a semi curedencapsulant 17″ onto atop carrier 41 is executed. Atop carrier 41 could be metal, glass, organic film, or plastic, which could provide a flat surface and appropriate strength for the semi curedencapsulant 17″. Then,FIG. 3B shows that alower unit 3 b is formed by disposing a matrix lead frame 6 (as shown inFIG. 6 ) on abottom carrier 31, which could be organic film, glass, plastic, or metal. As shown inFIG. 3B andFIG. 6 , thematrix lead frame 6 comprises a plurality of lead frames 13, each of the lead frames 13 comprises a plurality leads 131, and each lead 131 has aninner lead portion 131 a and anouter lead portion 131 b. Appropriate adhesion between thebottom carrier 31 and thelead frame 13 is necessary for further process. It should be noted that the executing priority of the processes illustrated inFIG. 3A andFIG. 3B are not limited. - Then,
FIG. 3C features that bonding theupper unit 3 a and thelower unit 3 b by laminating the semi curedencapsulant 17″ with the matrix lead frame to have theleads 131 be in contact with thetop carrier 41. In more detail, thetop carrier 41 contacts the top surface of theinner lead portions 131 a of theleads 131. Since the semi curedencapsulant 17″ is partially cured and is a semifluid substance, theleads 131 would be enclosed except for the top surface of theinner lead portions 131 a and the bottom surface of theouter lead portions 131 b. - Next, referring to
FIG. 3D , as shown therein, forming alead frame module 3 d (or 3 e shown inFIG. 3E ) on eachlead frame 13 of the matrix lead frame by fully cured the semi curedencapsulant 17″ to fully curedencapsulant 17′ and removing thetop carrier 41. After removing thetop carrier 41, the top surface of the fully curedencapsulant 17′ may be as high as (or lower than shown inFIG. 3E ) the top surface of theinner lead portions 131 a of theleads 131. Thereby, thelead frame module 3 d (or 3 e shown inFIG. 3E ) on the matrix lead frame is formed. - Referring to
FIG. 4A , as shown therein, awafer 30 is provided. Thewafer 30 is formed with internal circuits, anactive surface 113, a plurality ofpads 111 and apassivation layer 115. Thepads 111 are disposed on theactive surface 113 and are partially covered by thepassivation layer 115 to provide exposed areas (or named “openings”). Signals would be transmitted from or to the internal circuits through the exposed areas of thepads 111. - Referring to
FIG. 4B , as shown therein, forming acomposite bump 15 on each of thepads 111 is executed. Each of the composite bumps 15 comprises a firstconductive layer 151 and a secondconductive layer 153, and the firstconductive layer 151 is directly connected to and disposed between acorresponding pad 111 of thepads 111 and the secondconductive layer 153. Thereby, the internal circuits of thewafer 30 and the composite bumps 15 are electrically connected via the exposed areas of thepads 111. Then, as shown inFIG. 4C , thewafer 30 is saw to provide a plurality ofchips 11, each of which is electrically connected with plural composite bumps 15. As will be appreciated by those of ordinary skill in the art upon reviewing the above descriptions, other existing processes for composite bumps may also be applied in the present invention, and this will not be further described herein. - On the other hand, a plurality of lead frame module, which is disposed and formed on the
matrix lead frame 6 on abottom carrier 31, is provided according to the stepsFIGS. 3A-3E . The matrix lead frame 6 (as shown inFIG. 6 ) comprises a plurality of lead frames 13, and each of the lead frames 13 has a plurality ofleads 131 as depicted above. And theleads 131 of thematrix lead frame 13 are enclosed with the fully curedencapsulant 17′ except for the top surface of theinner lead portions 131 a and the bottom surface of theouter lead portions 131 b.FIG. 5A shows the following step that bonding each of thechips 11 to a corresponding plurality ofleads 131 of the lead frames 13 of lead frame module on the matrix lead frame withcomposite bumps 15. Each of thechips 11 is electrically connected to a part of theleads 131 of the matrix lead frame by a plurality of composite bumps 15. The secondconductive layer 153 of eachcomposite bump 15 is directly connected to the top surface of theinner lead portion 131 a of thecorresponding lead 131 of thelead frame 13 by thermo-ultrasonic bonding, reflowing or applying conductive paste. It is known that there would be solder between thecomposite bumps 15 and the inner leads 131 a, and such solder is not shown inFIG. 5A if reflow is applied. - Then, as shown in
FIG. 5B , thechip 11, the lead frames 13 on the matrix lead frame and the composite bumps 15 are encapsulated. Theencapsulant 17 is formed around thechip 11 and the composite bumps 15 and covers almost the whole surface of thelead frame 13 except for the bottom surface ofouter lead portion 131 b oflead 131 by transfer molding, screen printing, coating, or injection, etc. Theencapsulation interface 19 would be formed in such case, no matter whether theencapsulant 17 is the same material as the fully curedencapsulant 17′ or not. Finally, singulating the matrix lead frame and stripping off thebottom carrier 31 to the QFN packages 1 is executed as shown inFIG. 2 . TheQFN package 1 comprises one of the encapsulatedchips 11 and a part of the encapsulated matrix lead frame. - When adapting thermo-ultrasonic bonding, there would be thermal stress arisen after thermo-ultrasonic boding, and the top surface of the
inner lead portion 131 a would be not bent, cracked or even fractured. And no more melting solder overflows in the present invention - In other aspect, the composite bump may further comprise at least an under bump metallization (UBM) layer, or a covering third conductive layer and a barrier layer. Referring to
FIG. 7 , as shown therein, thechip 11 is electrically connected to plural composite bumps throughplural pads 111. Each of thecomposite bumps 2 comprises an under bump metallization (UBM)layer 21, a firstconductive layer 23, a secondconductive layer 25, a covering thirdconductive layer 27 and abarrier layer 29. TheUBM layer 21 is disposed between the firstconductive layer 23 and thepad 111 of thechip 11. The firstconductive layer 23 is located on theUBM layer 21, and the secondconductive layer 25 is in turn located on the firstconductive layer 23. The covering thirdconductive layer 27 that covers the surface each of thecomposite bumps 2, which includes the secondconductive layer 25, and the firstconductive layer 23. Thebarrier layer 29 located between the firstconductive layer 23 and the secondconductive layer 25. TheUBM layer 21 may be made of a material selected from titanium, tungsten, copper, gold, and alloys thereof. The covering thirdconductive layer 27 may be made of gold, but it is not limited thereto. Thebarrier layer 29 may be made of nickel, but it is not limited thereto. - Moreover, the step of forming the
wafer 30 shown inFIG. 4A may further comprises the following steps of forming a redistribution layer (RDL) 51 on each of thepads 111 of thechips 11 for electrical connection between the firstconductive layer 151 of each of thecomposite bumps 2; and forming thecomposite bump 15 by forming a firstconductive layer 151 on each of the RDL layers 51 and forming a secondconductive layer 153 on the firstconductive layer 151 to re-layout the bump position as shown inFIG. 8 . - With the composite bumps, the pitch between and the height of the composite bumps 15 of the
QFN package 1 could be controlled, and the short interconnection loop formed by the composite bumps 15 could reduce the resistance and inductance and improve the performance of the whole QFN package. Moreover, pre-molding the lead frame could avoid the different leveling issue of inner lead portions and protect the lead surface. - The above disclosure is related to the detailed technical contents and inventive features thereof. People skilled in this field may proceed with a variety of modifications and replacements based on the disclosures and suggestions of the invention as described without departing from the characteristics thereof. Nevertheless, although such modifications and replacements are not fully disclosed in the above descriptions, they have substantially been covered in the following claims as appended.
Claims (15)
1. A Quad Flat Non-leaded (QFN) package, comprising:
a chip;
a lead frame, having a plurality of leads;
a plurality of composite bumps, each having a first conductive layer and a second conductive layer, the first conductive layer being electrically connected between the chip and the second conductive layer, and the second conductive layer being electrically connected between the first conductive layer and one of the leads; and
an encapsulant, encapsulating the chip, the leads and the composite bumps, and an encapsulation interface which is not higher than a top surface of the lead frame.
2. The QFN package as claimed in claim 1 , further comprising a plurality of plated structures, one of which is adhered between the second conductive layer and the lead.
3. The QFN package as claimed in claim 2 , wherein each of the plated structures is one of solder and a copper pillar with a solder cap.
4. The QFN package as claimed in claim 1 , further comprising a covering third conductive layer, which covers surfaces of the composite bumps.
5. The QFN package as claimed in claim 1 , wherein the chip having a redistribution layer (RDL) to electrically connect to the first conductive layer of each of the composite bumps.
6. The QFN package as claimed in claim 1 , further comprising a plurality of conductive paste, respectively disposed between and adhering each of the composite bumps and a corresponding lead of the leads.
7. The QFN package as claimed in claim 1 , wherein the encapsulant is thermosetting resin.
8. The QFN package as claimed in claim 1 , wherein the first conductive layer is made of a material selected from copper, nickel, aluminum, zinc, and combinations thereof.
9. The QFN package as claimed in claim 1 , wherein the second conductive layer is made of a material selected from gold, copper, silver, tin, zinc, indium, and combinations thereof.
10. A manufacturing process for Quad Flat Non-leaded (QFN) packages, comprising the steps of:
forming a semi-cured encapsulant between a plurality of leads of a matrix lead frame on a bottom support carrier;
bonding a plurality chips on the leads of the matrix lead frame, each of the chips being electrically connected to a part of the leads of the matrix lead frame by a plurality of bumps after the semi-cured encapsulant is fully cured;
encapsulating the chips and the matrix lead frame; and
forming a QFN package by singulating the encapsulated chips and the encapsulated matrix lead frame, wherein the QFN package comprises one of the encapsulated chips and a part of the encapsulated matrix lead frame.
11. The manufacturing process as claimed in claim 10 , wherein the semi-cured encapsulant is not higher than a top surface of the leads of the matrix lead frame.
12. The manufacturing process as claimed in claim 10 , wherein each of the leads has an inner lead portion and an outer lead portion, and a bottom surface of the inner lead portion of each of the leads is higher than a bottom surface of the outer lead portion of each of the leads.
13. The manufacturing process as claimed in claim 10 , wherein each of the bumps is a composite bump, including a first conductive layer and a second conductive layer, which is softer than the first conductive layer.
14. The manufacturing process as claimed in claim 12 , wherein each of the chips is electrically connected to a top surface of the inner lead portions of the part of the leads of the matrix lead frame.
15. The manufacturing process as claimed in claim 10 , wherein the plurality of bumps are directly connected to the leads of the matrix lead frame by thermo-ultrasonic bonding.
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Also Published As
Publication number | Publication date |
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US8962395B2 (en) | 2015-02-24 |
CN102820276A (en) | 2012-12-12 |
TW201250885A (en) | 2012-12-16 |
TWI550741B (en) | 2016-09-21 |
CN102820276B (en) | 2016-05-11 |
US20130280865A1 (en) | 2013-10-24 |
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