TWI279887B - Manufacturing method of flip chip electronic device - Google Patents

Manufacturing method of flip chip electronic device Download PDF

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Publication number
TWI279887B
TWI279887B TW090120963A TW90120963A TWI279887B TW I279887 B TWI279887 B TW I279887B TW 090120963 A TW090120963 A TW 090120963A TW 90120963 A TW90120963 A TW 90120963A TW I279887 B TWI279887 B TW I279887B
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TW
Taiwan
Prior art keywords
substrate
pad
conductive layer
wafer
input
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Application number
TW090120963A
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Chinese (zh)
Inventor
Lu-Jen Huang
Guei-Sung Liou
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Chipbond Technology Corp
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Priority to TW090120963A priority Critical patent/TWI279887B/en
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Publication of TWI279887B publication Critical patent/TWI279887B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81205Ultrasonic bonding
    • H01L2224/81207Thermosonic bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying

Abstract

The method of the present invention includes the step of forming a plated bump and the step of connecting the plated bump and a pad on the substrate by thermosonic bonding. It is easy to control the thickness of the plated bump. The thermosonic bonding allows for low temperature bonding process for the plated bump and a pad on the substrate.

Description

1279887 B7 五、發明説明(1 ) 替換本 2006/12/12 案號:90120963 發明領域 本發明係關於覆晶電子裝置,以熱超音波接合晶片上 的電鍍金屬凸塊與基板的焊墊。 發明背景 通常一個積體電路裝置係由一積體電路晶片與一基板 電性接合後而形成。覆晶(flip chip)是其中的一種接合 方式。覆晶電子裝置是將一積體電路晶片的作用區域 (active area)對準基板上的焊墊並將兩者電氣結合,此 一方式可提供較短的接合路線、較低電感(inductance )及 較高積集度等優點。在覆晶技術中,接合方式主要以金屬 導體,連接積體電路晶片的作用區域和基板的焊墊。 1 ----;------裝-- 、清tsr滂皆6之ii意事頃再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 所使用的金屬導體如爲錫鉛凸塊,則製程中需加入迴 焊(refl〇w)步驟以融接晶片和基板,因此無法達到較小 間距(pitch)的要求。如以金或銅凸塊爲金屬導體,則不 需迴焊製程,因此凸塊在製程中不會變形,無微小間距的 限制。但是元件接合時所需的溫度高,因此低溫基板不適 合此一製程。如以熱超音波方式來接合,則可以較低溫度 (約150-200°C)完成接合。熱超音波方式廣泛運用於打 線成球(stud bumping)的製程中,打線成球爲覆晶技術 中的一種常用接合製程。 打線成球製程形成金屬導體的方法是利用打線( 4CHIPBOND200109TW, CBP-01-009 線 wire 本纸張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 1279887 A7 B7 五、發明説明(2 ) 替換本 2006/12/12 案號:90120963 (請先閲讀背面之注意事項再填寫本頁) bonding)的方式進行。將一金屬導線的末端以超音波加熱 並達到融化狀態,由於表面張力緣故,金屬導線末端會形 成球狀而結合至積體電路(1C)上輸入輸出焊墊的位置。 如圖la所示,在一晶片1上以打線成球方式,於輸入輸出 焊墊4上形成一金屬球2。接著翻轉晶片1,如圖2所示翻 轉後的晶片1,金屬球2和基板焊墊5接合。接合方式爲 施加壓力於晶片1上,讓晶片1上的金屬凸塊和基板的焊 墊5電氣結合,接合過程也可加入熱超音波來幫助接合。 通常加上導電黏劑(conductive paste )或異方黏膠 (anisotropic adhesives)來幫助接合。 經濟部智慧財產局員工消費合作社印製 由於滴下金屬球2是以打線方式形成,因此在圖1中 的金屬球2並非完美的球狀,而是在上方帶有一尾端,且 在晶片上也非覆蓋全部輸入輸出焊墊4的接觸面積。此一 尾端的形狀和接觸面積較小的現象,如圖lb所示,在接合 時金屬球2和輸入輸出焊墊4及基板焊墊5的接觸面積減 少,造成電氣連結不佳,降低良率。有時爲解決此一問題, 會先加壓將金屬球2壓平(未圖示),再進行接合動作。但 增加一次加壓製程,會讓晶片上的元件因多一次加壓,而 增加損壞的機會,亦會降低良率。再則打線成球的金屬球 2無法覆蓋輸入輸出焊墊4的全部面積,會早成露鋁現象, 讓產品的可靠度出現問題。 綜上所述,打線成球的覆晶接合方式需要一形成金屬 4CHIPBOND200109TW, CBP-01-009 本紙張尺度適用中國國家標準(CNS ) A4規格(210X29*7公釐) 1279887 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明( > ) 替換本2006/12/12 案號:90120963 導體的較佳方式。並期望此方法可以控制晶屬導體的接觸 面大小和厚度,以達到提昇良率的效果。 發明之目的與槪述 本發明之目的在於提供一種製造覆晶電子裝置的方 法’此覆晶電子裝置具有晶片與基板,在晶片上具有至少 一輸入輸出焊墊,在基板具有至少一基板焊墊,製作方法 包含下列步驟。在輸入輸出焊墊上形成一層導電層,此導 電層和輸入輸出焊墊電氣導通。在導電層上形成一層光阻 層並以微影技術開出電鍍孔,以電鍍方式生成電鍍金屬凸 塊於該導電層上,電鍍金屬凸塊與導電層電氣導通,且電 鍍金屬凸塊具有一接觸面。利用熱超音波方式電讓電鍍金 屬凸塊經由接觸面與基板焊墊電氣結合,完成此一覆晶電 子裝置。 圖式之簡單說明 圖la揭露既有技術以打線(wire bonding)方式,形 成一金屬球2於晶片1的輸入輸出焊墊4上。 圖lb揭露既有技術中晶片1的金屬球2,和基板3的 基板焊墊5接合。 圖2a到圖2d揭露形成電鍍金屬塊9於晶片1上的流 程。 圖3爲利用熱超音波方式接合電鍍金屬凸塊9和基板 焊塾5的不意圖。 4CHIPBOND200109TW, CBP-01-009 5 (請先閲讀背面之注意事項再填寫本頁) •裝·1279887 B7 V. INSTRUCTIONS (1) ALTERNATION 2006/12/12 Case No.: 90120963 Field of the Invention The present invention relates to a flip chip electronic device in which a pad of a plated metal bump and a substrate on a wafer is bonded by thermal ultrasonic waves. BACKGROUND OF THE INVENTION Generally, an integrated circuit device is formed by electrically connecting an integrated circuit chip to a substrate. A flip chip is one of the bonding methods. The flip chip electronic device aligns the active area of an integrated circuit wafer with the pads on the substrate and electrically combines the two, which can provide a short bonding path, a low inductance (inductance) and Higher integration and other advantages. In the flip chip technique, the bonding method mainly uses a metal conductor to connect the active region of the integrated circuit wafer and the pad of the substrate. 1 ----;------Installation --- Clear, tsr滂 are 6 ii, and then fill out this page. The metal conductor used by the Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative is tin. For lead bumps, a reflow process is required in the process to fuse the wafer and the substrate, so that a smaller pitch cannot be achieved. If the gold or copper bump is used as the metal conductor, the reflow process is not required, so the bump is not deformed during the process, and there is no limitation of the fine pitch. However, the temperature required for the bonding of the components is high, so the low temperature substrate is not suitable for this process. If joined by thermal ultrasonic means, the bonding can be completed at a lower temperature (about 150-200 ° C). The thermal ultrasonic method is widely used in the process of stud bumping, and the ball bonding is a common bonding process in the flip chip technology. The method of forming a metal conductor by a wire-forming process is to use a wire (4CHIPBOND200109TW, CBP-01-009 wire. This paper scale applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 1279887 A7 B7 V. Invention description (2) Replace this 2006/12/12 case number: 90120963 (please read the note on the back and then fill out this page). The end of a metal wire is heated by ultrasonic waves and reaches a molten state. Due to the surface tension, the end of the metal wire is formed into a spherical shape and bonded to the position of the input and output pads on the integrated circuit (1C). As shown in FIG. 1a, a metal ball 2 is formed on the input/output pad 4 by wire bonding on a wafer 1. Next, the wafer 1 is flipped, and the wafer 1 turned over as shown in Fig. 2, the metal balls 2 and the substrate pads 5 are joined. The bonding is performed by applying pressure to the wafer 1 to electrically bond the metal bumps on the wafer 1 to the pads 5 of the substrate, and the bonding process may also incorporate thermal ultrasonic waves to aid bonding. A conductive paste or anisotropic adhesives are usually added to aid the bonding. Printed by the Intellectual Property Office of the Ministry of Economic Affairs, the consumer cooperatives. Since the dropping metal balls 2 are formed by wire bonding, the metal balls 2 in Fig. 1 are not perfectly spherical, but have a tail end on the top and are also on the wafer. The contact area of all the input and output pads 4 is not covered. The shape of the tail end and the contact area are small, as shown in FIG. 1b, the contact area of the metal ball 2 and the input/output pad 4 and the substrate pad 5 is reduced at the time of bonding, resulting in poor electrical connection and low yield. . In order to solve this problem, the metal ball 2 is first pressed and pressed (not shown), and then the joining operation is performed. However, adding a pressurization process will increase the chance of damage due to one more pressurization of the components on the wafer, which will also reduce the yield. Then, the metal ball 2 that is made into a ball cannot cover the entire area of the input/output pad 4, and the aluminum phenomenon will be formed early, which causes problems in the reliability of the product. In summary, the flip chip bonding method requires a metal 4CHIPBOND200109TW, CBP-01-009. The paper size applies to the Chinese National Standard (CNS) A4 specification (210X29*7 mm) 1279887 A7 B7 Ministry of Economics Intellectual Property Bureau employee consumption cooperative printing 5, invention description ( > ) Replace this 2006/12/12 case number: 90120963 conductors preferred way. It is expected that this method can control the size and thickness of the contact surface of the crystal conductor to achieve the effect of improving the yield. OBJECT AND SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of fabricating a flip chip electronic device having a wafer and a substrate having at least one input and output pad on the wafer and at least one substrate pad on the substrate The production method includes the following steps. A conductive layer is formed on the input and output pads, and the conductive layer and the input and output pads are electrically connected. Forming a photoresist layer on the conductive layer and opening a plating hole by lithography, forming a plated metal bump on the conductive layer by electroplating, electrically plating the metal bump and the conductive layer, and the plated metal bump has a Contact surfaces. The flip-chip electronic device is electrically connected by electrically contacting the electroplated metal bumps with the substrate pads via a thermal ultrasonic method. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A discloses the prior art in which a metal ball 2 is formed on the input and output pads 4 of the wafer 1 by wire bonding. Figure lb discloses the metal ball 2 of the wafer 1 of the prior art bonded to the substrate pad 5 of the substrate 3. 2a to 2d disclose the process of forming the plated metal block 9 on the wafer 1. Fig. 3 is a schematic view of joining the plated metal bumps 9 and the substrate pad 5 by thermal ultrasonic waves. 4CHIPBOND200109TW, CBP-01-009 5 (Please read the notes on the back and fill out this page) • Install·

、1T 線 本紙張尺度適用中國國家標準(CNS ) Α4規格(21〇><297公瘦) 1279887 A7 B7 五、發明説明(4 ) 圖4爲本發明完成晶片和基板接合的示意圖 替換本 2006/12/12 案號:90120963 圖式之元件符號說明 1晶片 3基板 5基板焊墊 7光阻層 9電鍍金屬凸塊 10加壓 2金屬球 4輸入輸出焊墊 6導電層 8電鍍孔 91電鍍金屬凸塊的接觸面 11超音波 經濟部智慧財產局員工消費合作社印製 發明詳細說明 本發明主要爲提供一覆晶接合方式,以供接合晶片上 的輸入輸出焊墊和基板上的基板焊墊,利用電鍍產生電鍍 金屬凸塊,並利用熱超音波方式完成接合。 製造覆晶電子裝置的方法的流程如圖2a到圖4所示。 首先請參考圖2a,在晶片1先以金屬濺鍍方式產生一層導 電層6,此一導電層6和輸入輸出焊墊4電氣導通。接著 以習知技藝人士所熟悉的微影製程(未圖示)在導電層6 上形成一層光阻層7,並且開有電鍍孔8,如圖2b所示。 接著以電鍍方式形成電鍍金屬凸塊9,如圖2c所示以 電鍍方式形成電鍍金屬凸塊9較容易控制厚度,且電鍍金 屬凸塊9形狀平整,不需加壓即可提供足夠接觸面積以進 4CHIPBOND200109TW, CBP-01-009 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) ------!------^----‘--*-1T------線、 (請先閱讀背面之注意事項再填寫本頁) 1279887 B7 五、發明説明(f) 替換本 2006/12/12 案號:90120963 行電氣連結,且整個晶圓上的金屬凸塊9 一次即可製作完 畢。之後移除光阻層7,並以蝕刻去除沒有被電鍍金屬凸 塊9覆蓋的導電層6,如圖2d所示,完成電鍍金屬凸塊9。 金屬凸塊9的平整度較佳爲±1.〇微米(//m),且形狀可依 需求製造。以電鍍方式製成的金屬凸塊9之間距(Pitch)可 達20微米。 金屬凸塊9有~金屬凸塊的接觸面91,可和基板焊墊 5接合,請參考圖3。將晶片1翻轉,將電鍍金屬凸塊9 對準基板3上的基板焊墊5。接合時以加壓10、超音波11 及加熱(未圖示)的熱超音波方式完成此一接合製程。熱 超音波的溫度較佳爲15〇-200 °C,當金屬凸塊9的接觸面 91之表面積爲20微米X20微米時,所加壓力較佳爲0.05-2 kgf,反應時間較佳爲每晶粒1.5秒(1.5 sec/die)。 所完成的元件如圖4所示,藉由電鍍金屬凸塊9電氣 連通晶片1和基板5。採用此一覆晶連接方式的晶片可以 是以矽或砷化鎵爲材料的元件,基板可以是軟性電路板、 PCB硬板、陶瓷基板、玻璃基板或矽晶圓材料基板等,電 鍍金屬凸塊的材料包含金、銀、冑、錫㈣銦等金屬或合 金。 以上所述爲本發明的較佳實施例,用以說明本發明的 特徵與精神,而非_本發明的範圍。依__利範圍 4CHIPBOND200109TW, CBP-01-009 I--.------裝-------^--"訂------線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS ) A4規格f 楱、 1279887 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明(b ) 替換本2006/12/12案號:90120963 所作之均等變化與修飾,皆應屬於本發明之涵蓋範圍。 4CHIPBOND200109TW, CBP-01-009 8 本紙張尺度適用中國國家標準(CNS ) Α4規格(210Χ297公釐) (請先閱讀背面之注意事項再填寫本頁) •裝·1T line paper size is applicable to China National Standard (CNS) Α4 specification (21〇><297 mm) 1279887 A7 B7 V. Invention Description (4) Figure 4 is a schematic replacement of the wafer and substrate bonding of the present invention. 2006/12/12 Case No.: 90120963 Symbol of the symbol of the diagram 1 wafer 3 substrate 5 substrate pad 7 photoresist layer 9 electroplated metal bump 10 pressurization 2 metal ball 4 input and output pad 6 conductive layer 8 plating hole 91 Contact surface of electroplated metal bumps 11 Ultrasonic Economics Department Intellectual Property Bureau Staff Consumer Cooperatives Printing Invention Detailed Description The present invention mainly provides a flip chip bonding method for bonding input and output pads on a wafer and substrate soldering on a substrate The pad is formed by electroplating to produce a plated metal bump and is joined by a thermal ultrasonic method. The flow of the method of manufacturing a flip chip electronic device is shown in Figures 2a through 4. First, referring to FIG. 2a, a conductive layer 6 is formed on the wafer 1 by metal sputtering, and the conductive layer 6 and the input/output pad 4 are electrically conducted. Next, a photoresist layer 7 is formed on the conductive layer 6 by a lithography process (not shown) familiar to those skilled in the art, and a plating hole 8 is formed, as shown in Fig. 2b. Then, the plated metal bumps 9 are formed by electroplating, and the plated metal bumps 9 are formed by electroplating as shown in FIG. 2c, and the thickness of the plated metal bumps 9 is relatively flat, and the plated metal bumps 9 are flat and can provide sufficient contact area without pressurization. 4CHIPBOND200109TW, CBP-01-009 This paper size is applicable to China National Standard (CNS) Α4 specification (210Χ297 mm) ------!------^----'--*-1T- -----Line, (Please read the note on the back and fill in this page) 1279887 B7 V. Invention Description (f) Replace this 2006/12/12 Case No.: 90120963 Electrical connection, and on the entire wafer The metal bumps 9 can be fabricated in one operation. Thereafter, the photoresist layer 7 is removed, and the conductive layer 6 not covered by the plated metal bumps 9 is removed by etching, as shown in Fig. 2d, and the metal bumps 9 are completed. The flatness of the metal bumps 9 is preferably ±1. 〇 micrometer (//m), and the shape can be manufactured as required. The metal bumps 9 made by electroplating can have a pitch of 20 microns. The metal bump 9 has a contact surface 91 of a metal bump which can be bonded to the substrate pad 5, please refer to FIG. The wafer 1 is turned over, and the plated metal bumps 9 are aligned with the substrate pads 5 on the substrate 3. This bonding process is performed by the thermal ultrasonic method of pressurization 10, ultrasonic wave 11 and heating (not shown) at the time of joining. The temperature of the thermal ultrasonic wave is preferably 15 〇 - 200 ° C. When the surface area of the contact surface 91 of the metal bump 9 is 20 μm × 20 μm, the applied pressure is preferably 0.05-2 kgf, and the reaction time is preferably per The die is 1.5 seconds (1.5 sec/die). The completed component is electrically connected to the wafer 1 and the substrate 5 by plating metal bumps 9, as shown in FIG. The wafer using the flip chip connection may be a material made of germanium or gallium arsenide. The substrate may be a flexible circuit board, a PCB hard board, a ceramic substrate, a glass substrate or a germanium wafer material substrate, etc., and the metal bumps are plated. The material includes metals or alloys such as gold, silver, antimony, tin (tetra) indium. The above is a preferred embodiment of the invention to illustrate the features and spirit of the invention and not to limit the scope of the invention. According to __ profit range 4CHIPBOND200109TW, CBP-01-009 I--.------ loaded-------^--" order ------ line (please read the back of the note first) Matters fill out this page) Ministry of Economic Affairs Intellectual Property Bureau employees consumption cooperatives printed paper scale applicable to China National Standards (CNS) A4 specifications f 楱, 1279887 B7 Ministry of Economic Affairs Intellectual Property Bureau employees consumption cooperatives printed five, invention description (b) The equivalent changes and modifications made by this 2006/12/12 case number: 90120963 are intended to be within the scope of the present invention. 4CHIPBOND200109TW, CBP-01-009 8 This paper size is applicable to China National Standard (CNS) Α4 specifications (210Χ297 mm) (please read the notes on the back and fill out this page) • Install·

、1T, 1T

Claims (1)

I 1279887 替換本2006/12Λ2 案號:90120963 ·/、·、申请專利範圍 申請專利範圍: L 造-懸電子裝簡雜,_子裝置具有 (請先Μ讀背面之注意事項再填寫本頁) =晶片與一基板,該晶片上具有至少一輸入輸出焊墊, 該棊被具有至少一碁.板焊墊Λ該方法包含下列步驟: ..於該輸入_出焊墊上形成一·導電層,該導電層係與該輸 • * . · · · · · .····.. · · •入輸出焊墊電氣導通Γ : ··.·以電鍍方赛生成一電鍍金屬凸塊於該導電層上,該電鍍 金.釋母:|^興該導電層電氣導通,且轉電鍍金屬凸塊具 •有一ft麁面·ΐ:ί .以及 ν. ·... .:. • _ . · _’·: · · · * . .· . : . . . 以熱輯音波方式亀氣結合該.接觸面與該基板焊墊。 * : * . · · \2·如申蕭_:利範_第1.項所述之'方法,其中形成該導電層 . · ·* . · · · 的方法進一步包含下列步驟: . • · . · ·· · · 以一金屬濺鍍方式形成該導電層。. v 3·如申請專利範圍第1項所述之方法.,其中該輸入輸出凸 塊的材料係選自包含金、銀、銅、錫鉛合金以及銦的群 組。 . : · * 經 m. 部 智 慧 財 產 局 員 工 消 合 作 社 印 製 4. 如申請專利範圍第1項所述之方法,其中該基板的材料 係選自包含矽與砷化鎵的群組。 - . .· · 5. 如申請.專利範圍第1.項所述之方法,其中該基板係爲一 軟性電路板。 4CHIPBOND200109TW, CBP-01-009 9 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 1279887 88809 ABCD .六、申請專利範圍 替換本 2006/12/12 寒號:90120963 6.如申請專利範圍第1項所述之方法,其中該基板係爲一 * : tPCB電路板。· ’. .. · · ·· . _· ··· · ’ ·. * : · ’ . _ .7:如申請專利範圍第.Γ項所述之方法,其中.該基板係爲一 • · · 陶瓷基板 ,· · · . ·. · . ·* · .······· 〆 · · · · . · ·. }'·;·.' · . .. ·· .· · _ · 8·如备輕_科f幽舞人項所述之方法,萁中:該基板係爲一 .'· ··.·· ^::·': ··.···. · · . .. ·· · · . · · •玻璃基板: : : .· .·;'·· · · ·· · . ·· ···.·.···. • · · · . · · • · . · . . · - *9.如申靑專利範崮第1項所述之方法,萁中該基板係爲一 ..···.·. · '·. · · .矽基板。 * • · ·.··.·. . · · · ** · ' -• ; * . 10..如申請專利範崮第Γ項所述之方法,其中該基板焊墊的 材料係選.自包含金、銅與銀的群組。 閱 面 之 注 .意 事 項 t 經濟部智慧財產局員Η消費合作社印製 4CHIPBOND200109TW, CBP-01-009 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公1TI 1279887 Replacement of this 2006/12Λ2 Case No.: 90120963 ·/, ·, the scope of application for patent application: L-made-suspended electronic equipment is simple, _ sub-device has (please read the back of the note first and then fill this page) a wafer and a substrate having at least one input and output pad thereon, the crucible having at least one pad. The method comprises the steps of: forming a conductive layer on the input_out pad The conductive layer is electrically connected to the output pad: ····································································· On the layer, the electroplated gold. Release mother: | ^ The conductive layer is electrically conductive, and the electroplated metal bumps have a ft surface, ΐ: ί., and ν. ·... .:. • _ . _'·: · · · * . . . . . . . . . . . The thermal contact acoustic wave method combines the contact surface with the substrate pad. * : * · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · The conductive layer is formed by a metal sputtering method. The method of claim 1, wherein the material of the input and output bumps is selected from the group consisting of gold, silver, copper, tin-lead alloy, and indium. The method of claim 1, wherein the material of the substrate is selected from the group consisting of bismuth and gallium arsenide, as described in the above-mentioned application of the Ministry of Finance and Industry of the People's Republic of China. 5. The method of claim 1, wherein the substrate is a flexible circuit board. 4CHIPBOND200109TW, CBP-01-009 9 This paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) 1279887 88809 ABCD. VI. Patent application scope replacement 2006/12/12 Cold number: 90120963 6. The method of claim 1, wherein the substrate is a *: tPCB circuit board. · '. .. · · · · · _· ··· · ' ·. * : · ' . _ .7: The method described in the scope of the patent application, wherein the substrate is a · Ceramic substrate, · · · · ···························································· 8. If the method is as follows: 基板中: The substrate is a ..······ ^::·'::········· . . ·· · · . · · •glass substrate: : : .· .·;'·· · · ·· · . ·· ···.·.···. • · · · . · · • · . ·····9. The method described in claim 1, wherein the substrate is a ..············. *·············································· A group containing gold, copper, and silver. Note to the note. Intentions t Ministry of Economic Affairs Intellectual Property Bureau Η Consumer Cooperative Print 4CHIPBOND200109TW, CBP-01-009 This paper scale applies to China National Standard (CNS) A4 specification (210 X 297 1T
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8962395B2 (en) 2011-06-10 2015-02-24 Chipmos Technologies Inc. QFN package and manufacturing process thereof
US9362247B2 (en) 2013-10-08 2016-06-07 Kulicke And Soffa Industries, Inc. Systems and methods for bonding semiconductor elements
US9780065B2 (en) 2013-10-08 2017-10-03 Kulicke And Soffa Industries, Inc. Systems and methods for bonding semiconductor elements
US9779965B2 (en) 2013-10-08 2017-10-03 Kulicke And Soffa Industries, Inc. Systems and methods for bonding semiconductor elements
CN114717613A (en) * 2022-04-13 2022-07-08 长电科技管理有限公司 Processing method for realizing leadless electroplating by using conductive film and substrate structure

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8962395B2 (en) 2011-06-10 2015-02-24 Chipmos Technologies Inc. QFN package and manufacturing process thereof
US9362247B2 (en) 2013-10-08 2016-06-07 Kulicke And Soffa Industries, Inc. Systems and methods for bonding semiconductor elements
TWI548012B (en) * 2013-10-08 2016-09-01 庫利克和索夫工業公司 Systems and methods for bonding semiconductor elements
US9633981B2 (en) 2013-10-08 2017-04-25 Kulicke And Soffa Industries, Inc. Systems and methods for bonding semiconductor elements
US9780065B2 (en) 2013-10-08 2017-10-03 Kulicke And Soffa Industries, Inc. Systems and methods for bonding semiconductor elements
US9779965B2 (en) 2013-10-08 2017-10-03 Kulicke And Soffa Industries, Inc. Systems and methods for bonding semiconductor elements
US9905530B2 (en) 2013-10-08 2018-02-27 Kulicke And Soffa Industries, Inc. Systems and methods for bonding semiconductor elements
US10297568B2 (en) 2013-10-08 2019-05-21 Kulicke And Soffa Industries, Inc. Systems and methods for bonding semiconductor elements
US10312216B2 (en) 2013-10-08 2019-06-04 Kulicke And Soffa Industries, Inc. Systems and methods for bonding semiconductor elements
CN114717613A (en) * 2022-04-13 2022-07-08 长电科技管理有限公司 Processing method for realizing leadless electroplating by using conductive film and substrate structure

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