TW530398B - Method for manufacturing bumps of chip scale package (CSP) - Google Patents

Method for manufacturing bumps of chip scale package (CSP) Download PDF

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Publication number
TW530398B
TW530398B TW091105394A TW91105394A TW530398B TW 530398 B TW530398 B TW 530398B TW 091105394 A TW091105394 A TW 091105394A TW 91105394 A TW91105394 A TW 91105394A TW 530398 B TW530398 B TW 530398B
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TW
Taiwan
Prior art keywords
wafer
bump
bumps
substrate
semi
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TW091105394A
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Chinese (zh)
Inventor
John Liu
Yau-Rung Li
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Chipmos Technologies Inc
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Priority to TW091105394A priority Critical patent/TW530398B/en
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Publication of TW530398B publication Critical patent/TW530398B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

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  • Wire Bonding (AREA)

Abstract

A method for manufacturing bumps of chip scale package (CSP) is provided. A mold is installed in front of a nozzle of injection device, the mold forms a plurality of holes. A semi-molten metal is filled inside the injection device. Then, the injection device injects the semi-molten metal to a plurality of contact pads of a provided substrate, so a plurality of bumps are formed on the contact pads by injection molding.

Description

530398530398

【發明領域】 ’特別係有關於 之基板上形成複 本發明係有關於一種凸塊形成之方法 一種以射出成形方式直接在晶片尺寸封震 數個凸塊之方法。 【先前技術】 csp所Λ的「晶片尺寸封裝」〔叫Scale Package, U 裝結#之面積不大於晶片面積-點五倍之半 =體、、、“冓,由於封裝結構之尺寸係縮小於接近晶片,且 说小化封裝之優點’因此高密度封裝的技術有裸晶封裝 (b^e chip)與覆晶封裝(fHp chip),其晶片與基板 之間大多係採用凸塊作電性連接。 在美國專利第5, 906, 3 1 2號「覆晶凸塊及其製造方 法」中,揭示一種覆晶凸塊之製造方法,其將導線以打線 (wire bonding)及熱超音波壓合(therm — s〇nic bonding)之方式連接至晶片之焊墊上,而形成一具有尖 端之凸塊(bumps ),該晶片之焊墊周邊形成防護層 (passivation layers),以保護晶片,另在凸塊表面以 電鐘等方式形成一傳導層(diffusi〇ri barrier layer )’如鎳或把金屬,該傳導層係具有高導電及導熱特性, 亦可降低接觸阻抗(contact resistances),以進行覆 晶接合至一基板,然而在晶片(或晶圓)上直接以打線方 式形成之凸塊’其係以打線機(w i r e b 〇 n d e r )逐一打線 成形’無法一次大量製作完成凸塊,故生產效率有待提 530398 五、發明說明(2) 【發明目的及概要】 本發明之主要目的在於提供一種晶片尺寸封裝之凸塊 形成方法’其係利用射出成形方式直接在晶片尺寸封裝之 基板上形成複數個凸塊,使凸塊之製程具有高量產性。 本發明之次一目的在於提供一種晶片尺寸封裝之凸塊 形成方法,其係利用射出成形方式在晶片尺寸封裝之基板 上形成複數個凸塊,該些凸塊係可具有一尖端,而利^ 面接合。 依本發明之晶片尺寸封裝之凸塊形成方法,其係在一 f出裝置之出料口前端設置一模具,該模具係具有複數個 模孔,射出裝置内係填充有半熔融金屬,將半熔融金屬由 射出裝置之出料口射出至一基板之複數個導接墊,以形 複數個凸塊。 【發明詳細說明】 請參閱所附圖式,本發明將列舉以下之實施例說明: 狀在本發明之第一具體實施例中,第丨圖係為晶片尺寸 封裝之凸塊形成方法截面圖,該些凸塊係以金屬射出成形 (metal injecti〇n m〇lding,MIM)之方式形成在一美 上,其製造方法詳述如後。 ^如第1圖所示,準備一基板10,該基板10係可為陶瓷 ,路板印刷電路板(printed circuit board,PCB)、 晶片或晶圓等等,在本實施例中,該基板1 0係為一晶圓, 且’、表面係形成有複數個導接墊11 (contact pads),以 供形成凸塊(bumps )。[Field of the Invention] 'It is particularly related to the formation of a bump on a substrate. The present invention relates to a method for forming bumps, a method for directly sealing several bumps at a wafer size by injection molding. [Previous technology] The "chip size package" [called Scale Package by csp] is not larger than the area of the chip-half of the point-five times the size of the chip = body, ,, "", because the size of the package structure is reduced to Close to the chip, and said the advantages of miniaturized packaging 'Therefore, high-density packaging technologies include bare chip packaging (b ^ e chip) and flip-chip packaging (fHp chip), most of which use bumps for electrical connection between the chip and the substrate In U.S. Patent No. 5,906, 3 1 2 "Flip-Chip Bumps and Manufacturing Method", a method for manufacturing flip-chip bumps is disclosed, in which wires are bonded by wire bonding and thermal ultrasound (Therm — sonic bonding) to connect to the pads of the wafer to form a bumps with a tip. The wafer's pads are surrounded by passivation layers to protect the wafer and A conductive layer (such as nickel or metal) is formed on the surface of the block by means of an electric clock or the like. The conductive layer has high electrical and thermal characteristics, and can also reduce contact resistances for chip-on-chip Join to one The substrate, however, the bumps formed by wire bonding directly on the wafer (or wafer) are formed by wire bonding one by one using a wire bonder. The bumps cannot be produced in large quantities at one time, so the production efficiency needs to be improved. 530398 Description of the Invention (2) [Objective and Summary of the Invention] The main object of the present invention is to provide a bump forming method for a wafer-size package, which uses an injection molding method to directly form a plurality of bumps on a substrate of a wafer-size package to make the bumps The block manufacturing process is highly productive. A second object of the present invention is to provide a bump forming method for a wafer size package, which uses an injection molding method to form a plurality of bumps on a substrate of the wafer size package. The bumps may have a tip, which is advantageous. Face bonding. According to the method for forming bumps of a wafer-size package according to the present invention, a die is provided at the front end of a discharge port of an f-out device, and the die has a plurality of die holes. The molten metal is ejected from a discharge port of the injection device to a plurality of lead pads of a substrate to form a plurality of bumps. [Detailed description of the invention] Please refer to the attached drawings. The present invention will enumerate the following embodiment descriptions: In the first specific embodiment of the present invention, the first diagram is a cross-sectional view of a bump forming method for a chip size package The bumps are formed on the US by a metal injection molding (MIM) method, and the manufacturing method is described in detail below. ^ As shown in FIG. 1, a substrate 10 is prepared. The substrate 10 may be ceramic, printed circuit board (PCB), wafer or wafer, etc. In this embodiment, the substrate 1 0 is a wafer, and a plurality of contact pads 11 (contact pads) are formed on the surface for forming bumps.

530398530398

主要==形之射出裝置2〇 (injecti0“-i-) ,要包U熱炼爐21、送料螺桿22、出料⑽ (hopper )、促動機25 (i j 二(一),其中在出料口 =具=質^金屬或陶莞…等,其係具有複數個模 接執η ΐ 孔28之口㈣約略等於基板1〇之導 ί ϊ α! ί 且模孔28 一端係具有較大口徑,以利於導入 f射土半:融金屬’而半熔融金屬(semii〇iten )係由送料斗24填充至射出裝置2〇之熱炼㈣内部,並以 r”續加熱射出裝置2〇内之半熔融金屬,使其保持 熔融湓度(如錫之熔融溫度約2〇〇t及金之熔融溫度約 l〇64t以上),該半熔融金屬係由金屬粉末與黏結劑(或 稱兩分子結合劑)混煉而成,該金屬粉末係可為金、錫、 錫鉛合金或錫銅合金…等等,而射出裝置2〇係以促動機25 推動送料螺桿22,迫使半熔融金屬由出料口23前端之模呈 27之模孔28射出。 、^ 將該基板10以定位裝置30定位於模具27前方,該定位 裝置30係可控制基板1〇前後移動,使模具27之複數個模孔 28對應於該基板1〇之導接墊丨丨,較佳地,該基板1〇與模具 27間係具有一間距,該間距係約略等於所需凸塊丨2之高/、 度,如第2圖所示,將半熔融金屬由射出裝置2〇之出料口 23射出丨並經由模具27之模孔28,使半熔融金屬熔接在基 板1 〇之導接墊11上,而在半熔融金屬冷卻凝固後即形成$ 而之凸塊1 2,必要時,可在半熔融金屬冷卻凝固之前,以 530398Main == Xingzhi injection device 2〇 (injecti0 “-i-), which includes U thermal furnace 21, feeding screw 22, discharge hopper, hopper 25 (ij two (one), in which口 = 具 = quality ^ metal or ceramics, etc., which has a plurality of die attachment η ΐ The opening of the hole 28 is approximately equal to the guide of the substrate 10 ί ϊ α! Ί And the end of the die hole 28 has a larger diameter In order to facilitate the introduction of f shot soil half: molten metal, and semi-molten metal (semii〇iten) is filled from the feed hopper 24 to the inside of the hot smelter of the injection device 20, and r "continuously heating the inside of the injection device 20" Semi-molten metal to keep its melting degree (such as the melting temperature of tin is about 2000t and the melting temperature of gold is about 1064t or more). The semi-molten metal is composed of a metal powder and a binder (or a combination of two molecules) Agent), the metal powder can be gold, tin, tin-lead alloy or tin-copper alloy, etc., and the injection device 20 is used to promote the feeding screw 22 to promote the feed screw 22 to force the semi-molten metal to be discharged from the material. The die at the front end of the mouth 23 is shot in a die hole 28 of 27. ^ Position the substrate 10 in front of the die 27 with the positioning device 30, and The positioning device 30 can control the substrate 10 to move back and forth, so that the plurality of mold holes 28 of the mold 27 correspond to the conductive pads of the substrate 10. Preferably, the substrate 10 and the mold 27 have a distance therebetween. The distance is approximately equal to the height / degree of the required bump 丨 2. As shown in FIG. 2, the semi-molten metal is shot from the discharge port 23 of the injection device 20 and passed through the die hole 28 of the mold 27. The semi-molten metal is welded to the lead pad 11 of the substrate 10, and the bump 12 is formed after the semi-molten metal is cooled and solidified. If necessary, the semi-molten metal can be cooled to 530398 before the semi-molten metal is cooled and solidified.

五、發明說明(4) 定位裝置3 0移動該基板1 〇 ’或是移動該射出裝置2 〇,使凸 塊1 2具有一尖端1 3 ’而具有適當之彈性,以利於表面接合 (surface mounting),另,較佳地,該基板1〇係置於一 可控溫之密閉空間,或是該定位裝置3〇内設有冷卻裝置 (圖未繪出),在凸塊12射出成形時,可使半熔融^屬急 速冷卻凝固。 ~V. Description of the invention (4) The positioning device 30 moves the substrate 1 0 ′ or the injection device 2 0, so that the bump 12 has a tip 1 3 ′ and has appropriate elasticity to facilitate surface mounting. ) In addition, preferably, the substrate 10 is placed in a temperature-controlled closed space, or a cooling device (not shown) is provided in the positioning device 30, and when the projection 12 is formed by injection, It can make the semi-melted alloy rapidly solidify. ~

、之後,如第3圖所示,以上述過程製作完成之凸塊以 係為生胚(green compact),將該些凸塊12進行脫脂 (debinding),以脫除先前混入之黏結劑,而該具^凸 塊1 2之基板1 〇 (如晶圓或晶片)即可用以進行表面接合, 必要時,可再進行燒結(sintering )(如常壓燒結、氣 ^燒結或熱壓燒結…等等),使該些凸塊12之結構較為密 貝而具有咼搶度(95%以上)、高機械性及高可電鍍 性,且在射出成形時,該些凸塊12係可具有一尖端13,另 可在凸塊12表面電鍍一層金、鎳或鈀等高導電性金屬,以 ::f面接合及提高電性接觸,目此,射出成形方式係可 在基板10上一次形成複數個凸塊12,其係可省去不少後續 ^ =驟,而使凸塊之製程具有高量產性,故藉由射出成After that, as shown in FIG. 3, the bumps produced by the above process are used as green compacts, and the bumps 12 are debinding to remove the previously mixed adhesive, and The substrate 10 with bumps 12 (such as wafers or wafers) can be used for surface bonding, and if necessary, sintering (such as atmospheric sintering, gas sintering or hot pressing sintering, etc.) Etc.) to make the structures of the bumps 12 denser and have a grabbing degree (more than 95%), high mechanical properties and high electroplatability, and when injection molding, the bumps 12 can have a tip 13. Another layer of highly conductive metal such as gold, nickel, or palladium can be plated on the surface of the bump 12, and the :: f surface can be used to increase the electrical contact. For this reason, the injection molding method can form a plurality of substrates on the substrate 10 at a time. The bump 12 can save a lot of subsequent ^ = steps, so that the process of the bump has high mass production, so by injection

了有效率地製作完成凸塊,且在製程上可節省所需 人力、時間及成本等等。 故^發明之保護範圍視後附之申請專利範圍所界定者 圍内所:何熟知此項技藝者,在不脫離本發明之精神和範 之任何變化與修改,均屬於本發明之保護範園。In this way, the bumps can be produced efficiently, and the labor, time, and cost can be saved in the process. Therefore, the scope of protection of the invention is determined by the scope of the attached patent application. The following are the scope of the invention: Anyone who is familiar with this technology, without departing from the spirit and scope of the invention, belongs to the scope of protection of the invention.

530398 圖式簡單說明 【圖式說明】 第1圖:依本發明之一具體實施例,以射出成形方式在晶 片尺寸封裝之基板上形成凸塊之截面圖;及 第2圖:依本發明之一具體實施例中,移動定位裝置及射 出裝置,使凸塊具有一尖端之截面圖;及 第3圖:依本發明之射出成形方式在晶片尺寸封裝之基板 上形成之凸塊截面圖。 【圖號說明】 10 基板 11 導接墊 12 凸塊 13 尖端 20 射出裝置 21 熱熔爐 22 送料螺桿 23 出料口 24 送料斗 25 促動機 26 加熱器 27 模具 28 模孑L 30 定位裝置530398 Brief description of the drawings [Illustration of the drawings] Figure 1: According to a specific embodiment of the present invention, a sectional view of a bump formed on a wafer-size package substrate by injection molding; and Figure 2: According to the present invention In a specific embodiment, the positioning device and the injection device are moved so that the bump has a tip cross-sectional view; and FIG. 3 is a cross-sectional view of the bump formed on the substrate of the wafer-size package according to the injection molding method of the present invention. [Illustration of drawing number] 10 base plate 11 lead pad 12 bump 13 tip 20 injection device 21 hot melting furnace 22 feeding screw 23 discharge opening 24 feeding hopper 25 motivator 26 heater 27 mold 28 mold L 30 positioning device

第8貢8th tribute

Claims (1)

530398530398 裳之凸塊形成方法 置一模具,該模具 係填充有半熔融金 口射出至一基板之 l、一種晶片尺寸封 置之出料口前端設 子匕,該射出裝置内 由射出裝置之出料 形成複數個凸塊。 ,其係在一射出裝 係具有複數個模 屬,將半熔融金屬 複數個導接墊,以 2、 如申請專利範圍第1項所沭之a H p斗私壯 杰古、土 ^ ^ ^ ά± 貝所述之曰日片尺寸封裝之凸塊形 、一 / ’八中“射出裝置(injection device)内之半 熔融金屬(Semi-m〇lten metal )係由金屬 劑混煉而成。 不〜勒、、、口 3、 、如申請專利範圍第2項所述之晶片尺寸封裝之凸塊形 成方法,其中該金屬粉末係為金、錫、錫鉛合金或錫銅 合金。 、、如申請專利範圍第1項所述之晶片尺寸封裝之凸塊形 成方法’其中該模具之模孔一端係具有較大口徑。 、如申請專利範圍第1項所述之晶片尺寸封裝之凸塊形 成方法,其中該基板係以定位裝置定位,該定位裝置係 控制該基板前後移動。 如申睛專利範圍第1項所述之晶片尺寸封裝之凸塊形 成方法’其中在凸塊射出成形時,移動該射出裝置,以 使凸塊具有尖端。 、如申請專利範圍第1項所述之晶片尺寸封裝之凸塊形 成方法,其中該基板係為陶瓷電路板、印刷電路板、晶 片或晶圓。A method for forming a bump of a skirt is to set a mold. The mold is filled with a semi-molten gold port to be ejected to a substrate, and a wafer size is enclosed at the front end of a discharge port. A dagger is set in the injection device. A plurality of bumps are formed. , It is a injection molding system with a plurality of molds, the semi-molten metal is a plurality of lead pads, 2, as in the scope of the application for the first patent of a H p bucket private strong ancient, soil ^ ^ ^ The semi-molded metal (Semi-molten metal) in the injection device of the Japanese film size package described in Japanese is encapsulated by a metal agent. Bu ~ Le ,,, Mouth 3, Bump forming method of wafer size package as described in item 2 of the patent application scope, wherein the metal powder is gold, tin, tin-lead alloy or tin-copper alloy. Method for forming bumps of a wafer size package described in item 1 of the scope of patent application 'wherein one end of the die hole of the mold has a larger diameter. Method for forming bumps of a wafer size package described in item 1 of the scope of patent application Wherein, the substrate is positioned by a positioning device, which controls the substrate to move forward and backward. The method for forming a bump of a wafer-size package as described in item 1 of the Shen-Jin patent scope, wherein the bump is moved during the injection molding of the bump. Injection device to The bump is provided with a tip. The bump forming method for a wafer-size package as described in item 1 of the patent application scope, wherein the substrate is a ceramic circuit board, a printed circuit board, a wafer, or a wafer.
TW091105394A 2002-03-19 2002-03-19 Method for manufacturing bumps of chip scale package (CSP) TW530398B (en)

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8962395B2 (en) 2011-06-10 2015-02-24 Chipmos Technologies Inc. QFN package and manufacturing process thereof
TWI478254B (en) * 2003-11-10 2015-03-21 Chippac Inc Bump-on-lead flip chip interconnection
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9064858B2 (en) 2003-11-10 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US9219045B2 (en) 2003-11-10 2015-12-22 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9373573B2 (en) 2003-11-10 2016-06-21 STATS ChipPAC Pte. Ltd. Solder joint flip chip interconnection
US9773685B2 (en) 2003-11-10 2017-09-26 STATS ChipPAC Pte. Ltd. Solder joint flip chip interconnection having relief structure
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US10580749B2 (en) 2005-03-25 2020-03-03 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming high routing density interconnect sites on substrate

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9379084B2 (en) 2003-11-10 2016-06-28 STATS ChipPAC Pte. Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9865556B2 (en) 2003-11-10 2018-01-09 STATS ChipPAC Pte Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9064858B2 (en) 2003-11-10 2015-06-23 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US9219045B2 (en) 2003-11-10 2015-12-22 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9373573B2 (en) 2003-11-10 2016-06-21 STATS ChipPAC Pte. Ltd. Solder joint flip chip interconnection
TWI478254B (en) * 2003-11-10 2015-03-21 Chippac Inc Bump-on-lead flip chip interconnection
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US9922915B2 (en) 2003-11-10 2018-03-20 STATS ChipPAC Pte. Ltd. Bump-on-lead flip chip interconnection
US9773685B2 (en) 2003-11-10 2017-09-26 STATS ChipPAC Pte. Ltd. Solder joint flip chip interconnection having relief structure
US9385101B2 (en) 2003-11-10 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming bump-on-lead interconnection
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