200843598 九、發明說明： 【發明所屬之技術領域】 本發明係關於將配置於配線基板上之焊料凸塊加以平 坦化的附帶有零件之配線基板的製造方法、具有焊料凸塊 之配線基板的製造方法、及將焊料凸塊平坦化處理後之配 線基板。 【先前技術】 以往，已知一種在搭載電子零件用之焊墊上形成焊料 凸塊的配線基板（半導體封裝體）。此種之配線基板係具有 球狀柵極陣列（BGA)、針狀柵極陣列（PGA)等的各種類型。 對此等配線基板所具有之焊料凸塊，能以覆晶方式高密度 地裝設電子零件。又，焊料凸塊例如係藉由焊料糊膏法等 所形成。具體而言，在配線基板上面的焊墊上印刷焊料膏 並進行迴焊。藉此，可形成凸起成半球狀之形狀的焊料凸 爲了提高配線基板與電子零件之接合性等，較佳爲形 成於配線基板上之每個焊料凸塊的高度爲一致。換言之， 較佳爲每個之焊料凸塊的共面性（Coplanarity)的測定値較 小者。又，焊料凸塊之高度係依焊料的體積或焊墊的面積 等而定。然而，會產生被稱之爲L V S B (L 〇 w V ο 1 u m e S ο 1 d e r Bump)之體積小的焊料凸塊（現在之發生率爲2〜3%)等，而 有於每個之焊料凸塊的高度上產生偏差的情況。其結果， 會使得共面性之測定値增大，而有在和電子零件之間產生 連接不良的可能性。 200843598 在此，如第1 8圖所示，提出一種在形成於配線基板5 1 上之各焊料凸塊52的上方設定一治具61，並使用治具61 來按壓各焊料凸塊5 2等，而將各焊料凸塊5 2的頂部加以 平坦化（參照第1 8圖之虛線部分）的技術（例如，參照專利文 獻1)。如此，即可防止LVSB的產生，進而可減低各焊料 凸塊52之共面性的測定値。又，在將各焊料凸塊52的頂 部平坦化處理後之配線基板5 1上，電子零件7 1的搭載係 0 依如下方式來進行（參照第19圖）。首先，使電子零件71 側之連接端子72與配線基板5 1側之焊料凸塊52位置對 準。然後，進行加熱而對焊料凸塊52進行迴焊，藉以將焊 ^ 料凸塊52與連接端子72接合。藉此，可將電子零件71搭 載於配線基板5 1上。 [專利文獻1]日本特開2004-6926號公報（第2圖等） 【發明內容】 (發明所欲解決之課題） • 然而，爲了提高與電子零件7 1之接合性，通常在焊接 時，對焊料凸塊52之頂部供給助焊劑53(參照第19圖）。 此助焊劑53係於迴焊時進行氣化而從與連接端子72的接 合界面釋出至外部，但如上述，當焊料凸塊52被平坦化 時’則易於形成不被釋出而蓄積於焊料凸塊52內。其結 果’會在焊料凸塊52與連接端子72之接合界面產生空洞， 因此會與電子零件71產生連接不良。 本發明係鑒於上述課題而提出者，其目的在於提供一 200843598 種可減低焊料凸塊之共面性的測定値，而且可防止空洞之 產生的附帶有零件之配線基板的製造方法、具有焊料凸塊 之配線基板的製造方法、及具有焊料凸塊之配線基板。 (解決課題之手段） 作爲解決上述課題用之手段（第1手段），採用一種附 帶有零件之配線基板的製造方法，係接合有配置於配線基 板本體之表面側的複數個焊料凸塊及配置於零件之底面側 的複數個連接端子的附帶有零件之配線基板的製造方法， 其特徵爲包含：焊料凸塊成形步驟，係將複數個焊料凸塊 之頂部加以平坦化及粗化；助焊劑供給步驟，係將助焊劑 供給於平坦化及粗化後之該複數個焊料凸塊之該頂部；及 加熱熔化步驟，係使該零件之該複數個連接端子對應地配 置於已完成助焊劑供給之該複數個焊料凸塊上，並在此狀 態之下將該複數個焊料凸塊加熱熔化。 藉此，根據第1手段之製造方法，因在焊料凸塊成形 步驟中將複數個焊料凸塊之頂部加以平坦化，所以，可確 實且容易地獲得具有共面性優良且適合與零件連接之焊料 凸塊群的附帶有零件之配線基板。而且，在焊料凸塊成形 步驟中將複數個焊料凸塊之頂部加以粗化而形成有微小凹 凸，所以，助焊劑容易蓄積於此等部分中。另外，形成於 焊料凸塊之頂部的凹凸，亦成爲加熱熔化時所氣化之助焊 劑的氣體脫出通路，所以，氣化後之助焊劑可通過氣體脫 出通路確實地從頂部釋出至外部。故而，可防止因氣化後 200843598 之助焊劑蓄積於焊料凸塊內而引起之空洞的產生。藉此’ 可提高焊料凸塊與零件之連接端子的連接可靠度。 另外，作爲解決上述課題用之手段（第2手段），採用 一種具有焊料凸塊之配線基板的製造方法，其特徵爲包 含··焊料凸塊配置步驟，係將複數個焊料凸塊配置於配線 基板本體之表面側；及焊料凸塊成形步驟，係將該複數個 焊料凸塊之頂部加以平坦化及粗化。 藉此，根據第2手段之製造方法，在焊料凸塊成形步 驟中將複數個焊料凸塊之頂部加以平坦化，所以，可確實 且容易地獲得具有共面性優良且適合與其他零件連接之焊 料凸塊的配線基板。而且，在焊料凸塊成形步驟中將複數 個焊料凸塊之頂部加以粗化而形成微小凹凸，所以，助焊 劑容易蓄積於此等部分中。另外，形成於焊料凸塊之頂部 的凹凸，亦成爲加熱熔化焊料凸塊時所氣化之助焊劑的氣 體脫出通路，所以，氣化後之助焊劑可通過氣體脫出通路 確實地從頂部釋出至外部。故而，可防止因氣化後之助焊 劑蓄積於焊料凸塊內而引起之空洞的產生。藉此，可提高 焊料凸塊與其他零件之連接可靠度。 構成本發明之配線基板的基板（配線基板本體），可列 舉以樹脂材料或陶瓷材料等爲主體所構成之基板等。作爲 以樹脂材料爲主體所構成之基板的具體例，具有EP樹脂（環 氧樹脂）基板、PI樹脂（聚醯亞胺樹脂）基板、BT樹脂（雙馬 來醯亞胺-三嗪樹脂）基板、PPE樹脂（聚苯醚樹脂）基板等。 200843598 此外’亦可使用由此等之樹脂與玻璃纖維（玻璃織布或玻璃 不織布）及聚醯胺纖維等之有機纖維的複合材料所構成的 基板。或是，亦可使用由將環氧樹脂等之熱硬化性樹脂含 浸於連續多孔質PTFE等之三維網眼狀氟系樹脂基材的樹 脂-樹脂複合材料所構成的基板等。另外，作爲以陶瓷材料 爲主體所構成之基板的具體例，具有由氧化銘、氮化銘、 氮化硼、碳化矽、氮化矽等之陶瓷材料所構成的基板等。 成爲焊料凸塊之形成材料的合金，係可依所搭載之零 件的連接端子等的材質等而適宜選擇，在此，列舉 90Pb -1 OSn、95Pb-5Sn、40Pb-60Sn 等之 Pb-Sn 系焊料、311-35 系焊料、Sn-Ag系焊料、Sn-Ag-Cu系焊料、Au-Ge系焊料、[Technical Field] The present invention relates to a method of manufacturing a wiring board with components attached to planarize solder bumps disposed on a wiring board, and a wiring board having solder bumps. The method and the wiring substrate after the solder bumps are planarized. [Prior Art] Conventionally, a wiring board (semiconductor package) in which solder bumps are formed on a pad for mounting electronic components has been known. Such a wiring board has various types such as a ball grid array (BGA) and a needle grid array (PGA). The solder bumps included in the wiring board can be mounted on the electronic component in a high-density manner by flip chip. Further, the solder bumps are formed, for example, by a solder paste method or the like. Specifically, a solder paste is printed on a pad on the wiring substrate and reflowed. Thereby, it is possible to form a solder bump which is convex in a hemispherical shape. In order to improve the bonding property between the wiring board and the electronic component, it is preferable that the height of each solder bump formed on the wiring board is uniform. In other words, it is preferable that the measurement of the coplanarity of each of the solder bumps is small. Further, the height of the solder bump depends on the volume of the solder or the area of the pad. However, a small-sized solder bump called LVSB (L 〇w V ο 1 ume S ο 1 der Bump) is produced (currently, the incidence is 2 to 3%), and the solder is present in each. A case where a deviation occurs in the height of the bump. As a result, the measurement of the coplanarity is increased, and there is a possibility that a connection failure occurs between the electronic component and the electronic component. 200843598 Here, as shown in FIG. 18, it is proposed to set a jig 61 above each solder bump 52 formed on the wiring substrate 51, and press the respective solder bumps 5 2 using the jig 61. The technique of flattening the top of each solder bump 52 (refer to the broken line portion of Fig. 18) (for example, refer to Patent Document 1). Thus, the generation of LVSB can be prevented, and the measurement of the coplanarity of each solder bump 52 can be reduced. Further, on the wiring board 5 1 in which the top of each solder bump 52 is planarized, the mounting system 0 of the electronic component 7 1 is performed as follows (see Fig. 19). First, the connection terminals 72 on the side of the electronic component 71 are aligned with the positions of the solder bumps 52 on the side of the wiring substrate 51. Then, heating is performed to reflow the solder bumps 52, thereby bonding the solder bumps 52 to the connection terminals 72. Thereby, the electronic component 71 can be mounted on the wiring substrate 51. [Patent Document 1] Japanese Laid-Open Patent Publication No. 2004-6926 (Fig. 2, etc.) [Explanation] (Problems to be solved by the invention) • However, in order to improve the bonding property with the electronic component 71, usually during soldering, The flux 53 is supplied to the top of the solder bump 52 (refer to Fig. 19). This flux 53 is vaporized at the time of reflow and is released from the joint interface with the connection terminal 72 to the outside. However, when the solder bump 52 is flattened as described above, it is easy to form and not accumulate and accumulate in Inside the solder bumps 52. As a result, a void is formed at the joint interface between the solder bump 52 and the connection terminal 72, so that connection failure with the electronic component 71 occurs. The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a method for manufacturing a wiring board with attached components capable of reducing the coplanarity of solder bumps and preventing the occurrence of voids, and having solder bumps. A method of manufacturing a wiring board of a block and a wiring board having solder bumps. (Means for Solving the Problem) As a means for solving the above-mentioned problems (the first means), a method of manufacturing a wiring board with components is used, and a plurality of solder bumps and arrangements disposed on the surface side of the wiring board main body are bonded. A method of manufacturing a wiring board with components attached to a plurality of connection terminals on a bottom surface side of a component, comprising: a solder bump forming step of flattening and roughening a top portion of a plurality of solder bumps; and a flux a supplying step of supplying a flux to the top of the plurality of solder bumps after planarization and roughening; and a heating and melting step of causing the plurality of connection terminals of the component to be correspondingly disposed on the completed flux supply The plurality of solder bumps are on the plurality of solder bumps, and the plurality of solder bumps are heated and melted in this state. According to the manufacturing method of the first means, since the tops of the plurality of solder bumps are flattened in the solder bump forming step, it is possible to reliably and easily obtain the excellent coplanarity and to be connected to the parts. A wiring substrate to which a solder bump group is attached. Further, in the solder bump forming step, the tops of the plurality of solder bumps are roughened to form minute recesses, so that the flux is easily accumulated in the portions. Further, the unevenness formed on the top of the solder bump also serves as a gas escape path for the flux vaporized at the time of heating and melting, so that the vaporized flux can be reliably released from the top through the gas escape path to external. Therefore, it is possible to prevent the occurrence of voids caused by the accumulation of the flux in the solder bumps of 200843598 after vaporization. Thereby, the connection reliability of the solder bumps to the connection terminals of the parts can be improved. Further, as a means for solving the above-described problems (second means), a method of manufacturing a wiring board having solder bumps is provided, characterized in that the solder bump arrangement step is performed, and a plurality of solder bumps are arranged on the wiring. a surface side of the substrate body; and a solder bump forming step of flattening and roughening the tops of the plurality of solder bumps. According to the second method, in the solder bump forming step, the tops of the plurality of solder bumps are planarized, so that it is possible to reliably and easily obtain a surface having excellent coplanarity and being suitable for connection with other components. A wiring substrate of solder bumps. Further, in the solder bump forming step, the tops of the plurality of solder bumps are roughened to form minute irregularities, so that the flux is easily accumulated in the portions. In addition, the unevenness formed on the top of the solder bump also serves as a gas escape path for the flux vaporized when the solder bump is heated, so that the vaporized flux can be surely passed from the top through the gas escape path. Released to the outside. Therefore, it is possible to prevent the occurrence of voids caused by the accumulation of the flux after vaporization in the solder bumps. Thereby, the reliability of connection of the solder bumps to other parts can be improved. The substrate (wiring substrate main body) constituting the wiring board of the present invention may be a substrate made of a resin material, a ceramic material or the like. Specific examples of the substrate mainly composed of a resin material include an EP resin (epoxy resin) substrate, a PI resin (polyimide resin) substrate, and a BT resin (bismaleimide-triazine resin) substrate. , PPE resin (polyphenylene ether resin) substrate, and the like. In addition, a substrate made of a composite material of a resin such as a glass fiber (glass woven fabric or glass non-woven fabric) or a polyamide fiber may be used. Alternatively, a substrate made of a resin-resin composite material in which a thermosetting resin such as an epoxy resin is impregnated into a three-dimensional network-like fluorine-based resin substrate such as continuous porous PTFE can be used. Further, as a specific example of the substrate mainly composed of a ceramic material, a substrate made of a ceramic material such as oxidized, nitrided, boron nitride, tantalum carbide or tantalum nitride is used. The alloy which is a material for forming the solder bumps can be appropriately selected depending on the material of the connection terminals of the mounted components, etc., and examples thereof include Pb-Sn systems such as 90Pb -1 OSn, 95Pb-5Sn, and 40Pb-60Sn. Solder, 311-35 solder, Sn-Ag solder, Sn-Ag-Cu solder, Au-Ge solder,
Au-Sn系焊料、Au-Si系焊料等。尤其是以上述複數種焊料 係由無鉛焊料所構成爲較佳。藉此因爲焊料凸塊內未含有 鉛，所以可減低配線基板對環境造成的負擔。另外，無鉛 焊料係比含鉛焊料的濕潤度更差，而有空洞之產生量增多 的傾向，所以，只要將焊料凸塊之頂部加以粗化而使助焊 劑容易釋出的話，即可更爲有效地防止空洞之產生。在此， 無鉛焊料係可列舉Sn-Sb系焊料、Sn-Ag系焊料、Sn-Ag-Cu 系焊料、Au-Ge系焊料、Au-Sn系焊料、Au-Si系焊料等。 又，焊料凸塊係在該加熱熔化步驟（該零件之接合步驟） 中，藉由加熱熔化而利用表面張力變化成球狀而使其高度 增高。藉此，在該焊料凸塊成形步驟中，若預先將焊料凸 塊之頂部大幅度地加以平坦化而增大其頂部之直徑的話， .200843598 在進行加熱熔化步驟時，可使頂部更爲靠近零件之連接端 子。因此，即使在焊料凸塊頂部的共面性的測定値略大的 情況，亦可容易進行焊料凸塊與連接端子的接合。 以在該焊料凸塊成形步驟中，使用具有按壓用粗面之 按壓治具進行加壓以使複數個焊料凸塊之頂部的高度一 致，藉此，將該頂部加以平坦化及同時粗化爲較佳。根據 此，可效率良好地製造該第1及第2手段的配線基板。 另外，在進行焊料凸塊成形步驟之情況，亦可藉由加 ® 熱器等之加熱手段來加熱按壓治具，亦可不予加熱。在加 熱按壓治具之情況，焊料凸塊會被某程度地軟化。故而， 與在常溫下進行的情況比較，使得焊料凸塊容易變形，而 不用過大地增大按壓治具的應力，可確實地將焊料凸塊之 頂部加以平坦化。另一方面，在不加熱按壓治具的情況， 則不需要加熱手段，而可以簡單之構成將焊料凸塊之頂部 加以平坦化。 φ 在此，以該按壓治具係由鈦或不銹鋼等之金屬材料、 氧化鋁、氮化矽、碳化矽、氮化硼等之陶瓷材料、玻璃材 等所構成爲較佳，以不會沾濕（或是不易沾濕）焊料的材料 爲較佳。尤其是，該按壓治具可由加工精度高且對熱之變 形小的陶瓷材料所構成。另外，以按壓治具之按壓用粗面 係平面爲較佳。根據此，因爲對各焊料凸塊施加均勻之按 壓力，所以，可精度良好地將各焊料凸塊之頂部加以平坦 化。 -10- 亦 亦200843598 又，作爲解決上述課題之另外手段（第3手段），採用 一種具有焊料凸塊之配線基板的製造方法，其特徵爲包 含：焊料凸塊配置步驟，係將複數個焊料凸塊配置於配線 基板本體之表面側；及焊料凸塊成形步驟，係將該複數個 焊料凸塊之頂部加以粗化。 藉此，根據第3手段之製造方法，在焊料凸塊成形步 驟中將複數個焊料凸塊之頂部加以粗化而形成有微小凹 凸，所以，助焊劑容易蓄積於此等部分中。另外，形成於 焊料凸塊之頂部的凹凸，亦成爲加熱熔化焊料凸塊時所氣 化之助焊劑的氣體脫出通路，所以，氣化後之助焊劑可通 過氣體脫出通路確實地從頂部釋出至外部。故而，可防止 因氣化後之助焊劑蓄積於焊料凸塊內而引起之空洞的產 生。藉此，可提高焊料凸塊與其他零件之連接可靠度。 又，作爲解決上述課題之另一手段（第4手段），採用 一種附帶有零件之配線基板的製造方法，係接合有配置於 配線基板本體之表面側的複數個焊料凸塊及配置於零件之 底面側的複數個連接端子的附帶有零件之配線基板的製造 方法，其特徵爲包含：焊料凸塊成形步驟，係將複數個焊 料凸塊之頂部加以粗化；及助焊劑供給步驟，係將助焊劑 供給於粗化後之該複數個焊料凸塊之頂部。 藉此，根據第4手段之製造方法，在焊料凸塊成形步 驟中將複數個焊料凸塊之頂部加以粗化而形成有微小凹 凸，所以，助焊劑容易蓄積於此等部分中。另外，形成於 -11- 200843598 焊料凸塊之頂部的凹凸，亦成爲加熱熔化焊料凸塊時所氣 化之助焊劑的氣體脫出通路，所以，氣化後之助焊劑可通 過氣體脫出通路確實地從頂部釋出至外部。故而，可防止 因氣化後之助焊劑蓄積於焊料凸塊內而引起之空洞的產 生。藉此，可提高焊料凸塊與其他零件之連接可靠度。 又，焊料凸塊之整個表面係由融點比焊料凸塊更高之 氧化膜所被覆，所以，即使因加熱而達到焊料凸塊之融點， 仍不容易將焊料凸塊熔化（迴焊）。故而，焊料凸塊與其他 ® 零件之連接變得困難。在此，在供給該助焊劑前之該複數 個焊料凸塊的該頂部具有凹凸且表面全體由氧化膜所被覆 •的情況，在該助焊劑供給步驟中，以該氧化膜係利用將助 焊劑供給於該複數個焊料凸塊之該頂部而被熔化爲較佳。 藉此，焊料凸塊之表面露出於氧化膜被熔化之部分。其結， 果，使得焊料凸塊在達到焊料凸塊之融點的時間點開始熔 化，所以，使得焊料凸塊變得容易溶化，而可容易進行焊 Φ 料凸塊與其他零件之連接。另外，焊料凸塊之頂部具有凹 凸，所以可於此部分確實地保持助焊劑。故而，容易自處 於頂部之氧化膜起優先作熔化。 又，作爲解決上述課題之另一手段（第5手段），採用 一種具有焊料凸塊之配線基板，其特徵爲：將頂部被平坦 化及粗化後之複數個焊料凸塊配置於配線基板本體之表面 上，同時該頂部之共面性的測定値，每1 cm2爲1 0 μ m以下， 且表面粗度Ra爲0.3"m以上、5/zm以下。 -12- .200843598 藉此，根據第5手段之配線基板，複數個焊料凸塊之 頂部被平坦化，且共面性的測定値，每1 cm2爲1 0 // m以下， 所以，可確實且容易與其他零件進行連接。假設共面性的 測定値爲每1 cm2大於1 0 // m時，會於每個之焊料凸塊的高 度上產生偏差，而有產生與其他零件之間的連接不良的可 能性。 而且，複數個焊料凸塊之頂部被粗化，且表面粗度Ra 爲0.3/zm以上、5/zm以下，所以，焊料凸塊內含有之助 焊劑，在加熱熔化時被氣化而確實地從頂部釋出至外部。 故而，可防止因氣化後之助焊劑蓄積於焊料凸塊內而引起 之空洞的產生。假設表面粗度Ra未滿0.3 /z m時，則氣化 後之助焊劑容易蓄積於焊料凸塊內，而容易產生空洞。另 一方面，若表面粗度Ra大於5 // m時，會於每個之焊料凸 塊的高度上產生偏差，而有造成共面性的測定値增大的可 能性。其結果，恐有焊料凸塊與其他零件之接合強度降低 之虞。另外，在表面粗度Ra大於5 μ m時，會在焊料凸塊 之頂部形成深的凹部，所以，恐有蓄積於凹部內之助焊劑 不容易釋出至外部之虞。 在此，本說明書中所記述之「共面性」，係顯示由「日 本電子機械工業會規格EIAJ ED-7304 BGA規定尺寸的測定 方法」所定義之端子最下面均一性。另外，「共面性之測 定値」，係由「ED-7304 BGA規定尺寸的測定方法」所定 義之測定値，是顯示相對配線基板本體之表面的複數個焊 -13: 200843598 料凸塊頂部的均一性的指標。另外，本說明書中所記述之 「表面粗度Ra」，係由JIS B0601所定義之算術平均粗度 Ra。又，表面粗度Ra之測定方法係依照ns B065 1。 【實施方式】 [第1實施形態] 以下，參照第1至第6圖，詳細說明具體化本發明的 第1實施形態。 第1圖爲焊料凸塊平坦化裝置1 0之槪略圖。第2圖爲 設定於此焊料凸塊平坦化裝置1 0上之配線基板1 1的槪略 俯視圖，第3圖爲同圖之槪略剖視圖。如第1圖所示，焊 料凸塊平坦化裝置1 0具備：用作按壓治具之上治具1 3、用 作支撐治具之下治具1 4、及將配線基板11設定於下治具 1 4上用的移動治具1 5等。 如第2及第3圖等所示，本實施形態之配線基板1 1， 係可對應於MPU等之多端子的高密度覆晶連接的針狀柵極 陣列（PGA)型的半導體封裝體。具體而言，此配線基板1 1 係在由包含玻璃纖維之雙馬來醯亞胺-三嗪等的樹脂所構 成之芯材基板的上下面，藉由公知方法積層複數層之樹脂 絕緣層的多層配線基板。此多層配線基板係厚度約1 mm， 邊長約40mm方形之平板狀構件，並於各樹脂絕緣層之間 具備未圖示之銅配線。 構成配線基板11之配線基板本體12的表面20(第3圖 中爲上面），大致中央的正方形區域，係作爲凸塊形成區域 -14- •200843598 AR1。在凸塊形成區域AR1內，大致格子狀排列地形成有 接合1C晶片45 (參照第4圖等）用之複數個焊墊21，同時於 各焊墊2 1上形成有焊料凸塊22。焊墊2 1係藉由複數之電 鍍層所形成，直徑設定爲150/z m，厚度設定爲20从m。焊 料凸塊22係在配線基板1 1之表面20的焊墊21上印刷焊 料膏並利用迴焊所形成者，具有凸起成半球狀的形狀。又， 本實施形態之焊料凸塊22，係由無鉛焊料之Sn-Ag系焊料 所構成。 另外，在配線基板本體12之背面23 (第3圖中爲下面） 的全範圍，大致格子狀排列地形成有複數個焊墊24，同時 藉由焊接而於各焊墊24上接合有插座裝設用之複數根針 腳25。又，配置於配線基板1 1之背面23側的各針腳25， 係由比表面20側之焊料凸塊22更高之融點的焊料所焊接。 如第3圖等所示，各針腳25具有截面圓形之軸部及直 徑比其軸部更大之頭部26。頭部26係對焊墊24賦與焊料。 φ 又，各針腳25係一次性地設定於未圖示之專用的定位治具 的針腳插入孔內，並以一次的焊接步驟接合於配線基板1 1 上。因此，可使配線基板1 1之各針腳25彼此的位置精度 變得較高。 第1圖所示之該移動治具15，係在支撐配線基板11 之四個角的狀態下，藉由未圖示之運送裝置沿運送軌道朝 水平方向移動，並朝垂直方向移動。藉由此移動治具1 5之 水平、垂直移動，將配線基板11設定於下治具1 4。 -15- 200843598 該上治具13之下面係平坦之按壓用粗面3 0。在本實施 形態中，按壓用粗面30之平坦度係設定爲每lcm2爲10 μ m 以下，且按壓用粗面3 0之表面粗度Ra係設定爲0.4/zm。 上治具13係藉由未圖示之加壓裝置（氣壓加壓裝置或油壓 加壓裝置等）而朝下方驅動，並藉由按壓用粗面30按壓該 焊料凸塊22。藉此，焊料凸塊22被平坦化，同時焊料凸塊 22之頂部27的上面亦被粗化（參照第4圖）。又，在本實施 形態中，由陶瓷材料（氮化硼）構成上治具1 3。 如第1圖所示，該下治具14於其中央部具備四方形柱 狀突出之支撐部3 1。支撐部3 1之前端面（上端面）係成爲可 接觸於該配線基板本體12之背面23的接觸面32。在支撐 部3 1之接觸面32，以與該針腳25相等之間距，格子狀地 排列有朝上開口之複數個針腳逃孔34。 本實施形態之針腳逃孔34，係將比開口部深之部分形 成爲等截面形狀，並隨著開口部朝開口端（上端）方向漸漸 φ 增大截面積般地形成。另外，此等之針腳逃孔3 4的開口部 係具有可收容針腳25之頭部26的大小之孔徑，且對於針 腳尖端側的直徑具有些微之空隙。又，較佳爲下治具14之 支撐部3 1係由機械強度高之金屬材料所形成，例如可使用 由鎢碳化物（WC)及鈷（Co)等所構成之超硬合金所形成。 如第1圖所示，在本實施形態之焊料凸塊平坦化裝置 1 0上設有將上治具1 3及下治具1 4加熱爲指定溫度用的電 熱加熱器41，42。在藉由此電熱加熱器41，42加熱各治具 -16- .200843598 13,14之狀態下，進行該焊料凸塊22之頂部27的平坦化及 粗化處理。 在第4圖所示之平坦化及粗化後之焊料凸塊22，自該 配線基板本體12之表面20至焊料凸塊22之頂部27的高 度，在本實施形態中係設定爲3 0 // m。另外，頂部2 7之表 面粗度Ra係設定爲〇.4/zm，在頂部27之平坦面產生有凹 凸。又，頂部27之共面性的測定値，係與上治具13之按 壓用粗面30的平坦度相等，設定爲每lcm2爲l〇/zm以下。 ® 又，平坦化及粗化後之焊料凸塊2 2的最大徑，係設定 爲該焊墊21之直徑的0.5倍以上、1.2倍以下爲較佳。假 設焊料凸塊2 2之最大徑係比焊墊2 1之直徑的1.2倍更大 的話，則在加熱熔化焊料凸塊22而進行該1C晶片45之接 合時，從焊墊21溢出之焊料接觸於鄰接之焊墊2 1的焊料 凸塊22，恐有產生短路之虞。另一方面，若焊料凸塊22 的最大徑未滿焊墊21的0.5倍時，即使加熱熔化焊料凸塊 φ 22仍不會增加太高，使得頂部27不容易接近於1C晶片45 之連接端子47，所以，不容易進行°焊料凸塊22與連接端子 47的接合。又，在本實施形態中，焊墊21之直徑爲150// m，所以，以焊料凸塊22的最大徑爲75 // m以上、180 μ m 以下爲較佳。另外，焊料凸塊22之頂部27的直徑係設定 爲焊料凸塊22的最大徑的0.5倍以上、未滿1.0倍爲較佳， 且設定爲焊料凸塊22的最大徑的0.8倍以上、未滿1.0倍 爲更佳。假設頂部27之直徑係未滿焊料凸塊22之最大徑 -17- 200843598 的0.5倍時，使得無法將在接合ic晶片45時所需要的助 焊劑28蓄積於頂部27之平坦面。另一方面，若頂部27之 直徑係焊料凸塊22之最大徑的1.0倍以上時，在加熱熔化 焊料凸塊22而進行1C晶片45之接合時，構成頂部27之 焊料接觸於鄰接之焊墊21的焊料凸塊22,恐有產生短路之 虞。又，在本實施形態中，焊料凸塊22的最大徑爲75 μ m 以上、180// m以下，所以，頂部27之直徑較佳爲37.5// m 以上、未滿180/zm。 ® 其次，說明本實施形態之配線基板1 1 (及附帶有零件之 配線基板）的製造方法。 配線基板11係依以下般所製造。首先，於芯材基板上 形成由環氧樹脂所構成之樹脂絕緣層，同時於芯材基板及 樹脂絕緣層之表面，藉由使用無電解銅電鍍及電解銅電鍍 之半加法形成銅配線。藉此，形成配線基板本體1 2。又， 亦可藉由減色法或全添加法形成銅配線。 φ 接著，在配線基板本體1 2之表面20的複數個部位， 藉由實施無電解Ni-P電鍍，並實施無電解Au電鍍，形成 由Ni-P電鍍層及Au電鍍層所構成之焊墊21。又，在配線 基板本體12之表面20未形成有焊墊21的部位，使用丙烯 樹脂或環氧樹脂等來形成阻焊1 9(參照第4圖等）。 然後，在焊料凸塊配置步驟中，在形成於配線基板本 體12之表面20的焊墊21上，使用未圖示之金屬遮罩印刷 焊料膏。然後將印刷完焊料膏之配線基板本體1 2配置於迴 -18- 200843598 焊爐內，加熱至比焊料之融點更高出10〜40 °C的溫度，之 後冷卻。藉此，在配線基板本體1 2之表面20側配置凸起 成半球狀之形狀的複數個焊料凸塊22。另外，在配線基板 本體12之背面23形成複數個焊墊24,並將針腳25焊接於 各焊墊24上。其結果，完成配線基板11(參照第1至第3 圖）。 接著，在表面20側向上之狀態下將配線基板1 1設定 於移動治具1 5上。另外，藉由電熱加熱器4 1，42將上治具 W 1 3及下治具1 4加熱爲1 1 〇 °C。然後，藉由移動治具1 5之 運送及昇降動作，使配線基板1 1支撐於下治具1 4之支撐 部31上。其結果，在配線基板1 1之背面23，處於被支撐 區域AR2(參照第1及第3圖）內之複數根針腳25，被確實 地導引於形成於支撐部3 1上之針腳逃孔34內，而在配線 基板1 1密接於支撐部3 1的接觸面32之狀態下被支撐。 接著，在焊料凸塊成形步驟中，降下上治具1 3，由上 φ 治具13之按壓用粗面30對配線基板11上之各焊料凸塊22 的頂部27進行加壓。此時，以加壓至各頂部27的高度成 爲一致的方式進行。於是，各焊料凸塊22之頂部27被確 實且均勻地施加壓力（在本實施形態中，每一凸塊爲 〇.〇7kg)，而將頂部27壓潰的結果，焊料凸塊22被平坦化 及粗化。然後，完成焊料凸塊成形步驟之配線基板1 1，藉 由移動治具15之運送及昇降動作而被運送至裝置外部。其 後’在助焊劑供給步驟中，將助焊劑28供給於平坦化及粗 -19- ‘200843598 化後之各焊料凸塊22之頂部27。又，作爲供給助焊劑28 之方法，可列舉於頂部27塗佈液狀之助焊劑28的方法、 藉由助焊劑分配器將液狀之助焊劑28供給於頂部27的方 法、使泡沬狀之助焊劑28與頂部27接觸的發泡式方法、 將霧狀之助焊劑28噴射於頂部27上之噴霧式的方法等。 又，助焊劑28之種類並無特別之限定，可使用習知之公知 方法。 又，在加熱熔化步驟中，使配置於1C晶片45之底面 46側的複數個連接端子47對應地配置於已被配置於配線 基板11之表面20側的完成助焊劑供給之複數個焊料凸塊 22上（參照第4圖）。並且，在此狀態之下將各焊料凸塊22 加熱熔化（迴焊），藉以使助焊劑28氣化，同時對各焊料凸 塊22與各連接端子47進行焊接（參照第5及第6圖）。藉 此，完成在配線基板1 1上搭載有1C晶片45的附帶有零件 之配線基板。 φ 再者’說明有關共面性及空洞之評價方法及其結果。 首先，依如下方式準備測定用樣品。準備配置有與本 實施形態相同之焊料凸塊22(平坦化及粗化後之焊料凸塊） 的基板，並以此作爲實施例。另外，準備配置有既未平坦 化亦未被粗化之焊料凸塊81的基板82(參照第7圖），並以 此作爲第1比較例。又，準備配置有與習知技術相同之焊 料凸塊9 1 (雖被平坦化但未被粗化之焊料凸塊）的基板 9 2 (參照第10圖），並以此作爲第2比較例。又，實施例之 -20- 200843598 焊料凸塊22的頂部27的表面粗度Ra係爲0.4 // m，第2 比較例之焊料凸塊91的頂部的表面粗度Ra係爲0.05 # m。 其次，對各測定用樣品（實施例、第1及第2比較例） 進行共面性之測定。另外，爲了提高評價可靠度，變更測 定用樣品之作成日而實施了 2次測定。又，無法使用相同 之測定器來實施未被平坦化之焊料凸塊81的共面性測定 及被平坦化之焊料凸塊22,9 1的共面性測定。在此，於焊 料凸塊81的共面性測定上，使用Solvi si on公司製的測定 ^ 器，而於焊料凸塊22,91的共面性測定上，使用高野股份 有限公司製之測定器。 進行共面性測定之結果，未被平坦化之第1比較例的 焊料凸塊8 1的共面性的測定値成爲最大。另一方面，可以 確認在實施例之焊料凸塊22及第2比較例之焊料凸塊9 1 中，皆可減小共面性之測定値。另外，可確認進行第2次 之共面性測定之結果，亦與第1次之測定有相同的結果。 φ 另外，對各測定用樣品（實施例、第1及第2比較例） 進行空洞之測定。具體而言，將焊料凸塊22,81，91與配置 於假晶片1 〇 1之底面側的連接端子1 02接合，並觀察此時 之狀態，藉以進行空洞之測定（參照第8,第9,第11及第12 圖）。詳細而言，雖在假晶片1 0 1之接合前未確認有空洞， 但在假晶片1 0 1之接合後才開始確認有空洞的部位，藉由X 射線繞射裝置（XRD)進行觀察（XRD觀察），以計數空洞之個 數。另外，亦藉由觀察（交叉觀察）焊料凸塊22,81，91之截 -21 - 200843598 面，以計數空洞之個數。另外，爲了提升各種觀察 的可靠度，變更測定用樣品之作成日而實施了各2 定。又，亦可在加上與使焊料凸塊22,81，91加熱熔 之溫度相同的溫度之熱量的狀態下進行空洞之測定 藉由XRD觀察而計數空洞之個數的結果，確認 比較例之焊料凸塊91上產生最多的空洞93。另一方 認實施例及第1比較例之焊料凸塊2 2，8 1所產生之 個數，係比第2比較例要少。另外，亦確認實施例 凸塊22所產生之空洞的個數，與第1比較例之焊料 所產生之空洞的個數，幾乎不存在差異。又，雖藉 次之XRD觀察而再次計數空洞之個數，但確認仍與 之XRD觀察結果相同。 另外，藉由交叉觀察而計數空洞之個數的結果 2比較例之焊料凸塊9 1上產生較多的空洞93。具儀 在第2比較例中，在9 8個中的9個焊料凸塊91產 93，空洞93之產生率成爲9/98 =約9.2%。另一方面 實施例及第1比較例之焊料凸塊22,81所產生之空 數，係比第2比較例要少。具體而言，在實施例中 個中的2個焊料凸塊22產生空洞，空洞之產生率成 約2.0%。在第1比較例中，在98個中的1個焊料 產生空洞，空洞之產生率成爲1/9 8 =約1·〇%。另夕1 在第2比較例之焊料凸塊91上產生的空洞93,比名 及第1比較例之焊料凸塊22,81所產生之空洞更3 之評價 次之測 化所需 〇 在第2 面，確 空洞的 之焊料 凸塊81 由第2 第1次 ，在第 I而言， 生空洞 ，確認 ί洞的個 ，在98 爲 2/98= 凸塊81 卜，確認 Ε實施例 r 〇 ▽， -22- 200843598 確認實施例之焊料凸塊2 2所產生之空洞的個數’比第1比 較例之焊料凸塊81所產生之空洞的個數略多’但大小相 同。 又，進行第2次之交叉觀察，再次計數第1及第2比 較例之焊料凸塊81,91所產生之空洞的個數。又’因爲實 施例之焊料凸塊22所產生之空洞的個數’係與第1比較例 之情況大致相同’所以’不特別進行第2次之交叉觀察。 其結果，確認看到有與第1次之交叉觀察相同的傾向。即， ^ 在第2比較例中，在144個中的3個焊料凸塊91產生空洞 93，空洞93之產生率成爲3/144 =約2.0%。另一方面’在第 1比較例中，在144個中的1個焊料凸塊8 1產生空洞，空 洞之產生率成爲1/144 =約0.7%。 藉由上述評價，可確認實施例及第2比較例之焊料凸 塊22，9 1的共面性之測定値，係比第1比較例之焊料凸塊 8 1的共面性之測定値更小。藉此，證明若於配線基板11 φ 採用實施例及第2比較例的話，在與假設晶片1 〇 1之連接 端子102的連接上不容易產生連接不良。但是，亦確認第2 比較例之焊料凸塊9 1所產生之空洞9 3的個數，係比實施 例及第1比較例之焊料凸塊22,81所產生之空洞的個數更 多，且更大。藉此，確認共面性之測定値小且對空洞之產 生的掛慮亦小的實施例較適合應用於配線基板Π。 藉此，根據本實施形態’可獲得如下之功效。 (1)在本實施形態之配線基板11，在焊料凸塊成形步 -23- 200843598 驟中複數個焊料凸塊22之頂部27被平坦化’且共面性的 測定値，每lcm2爲10/zm以下，所以，可確實且容易與1C 晶片45之連接端子47進行連接。故而，可防止焊料凸塊 22之一部分與連接端子47成爲未連接狀態的問題（開路不 良）的產生。 而且，在焊料凸塊成形步驟中各個焊料凸塊22之頂部 27被粗化，且表面粗度Ra爲0.4 A m，而在頂部27之平坦 面形成有微小凹凸，所以，助焊劑28容易蓄積於此等部分 ® 中。另外，形成於頂部27之凹凸，亦成爲加熱熔化時所氣 化之助焊劑的氣體脫出通路，所以，氣化後之助焊劑28可 通過氣體脫出通路確實地從頂部27釋出至外部。故而，可 防止因氣化後之助焊劑28蓄積於焊料凸塊22內而引起之 空洞的產生。藉此，可提高焊料凸塊22與1C晶片45之連 接端子47的連接可靠度。 (2) 在本實施形態中，在頂部27之平坦面生成有凹凸’ φ 使得提高與連接端子47之接合性用的助焊劑28容易蓄積 於頂部27，所以，在加熱熔化步驟中，助焊劑28容易接觸 於連接端子47。故而，可提高焊料凸塊22與連接端子47 的接合性。 (3) 在本實施形態中，在按壓焊料凸塊22時，按壓力容 易集中於被支撐區域AR2,而可藉由下治具14之支撐部31 來支撐被支撐區域AR2整體。因此，可防止配線基板11 之彎曲，可確實且容易地獲得具有共面性優良之焊料凸塊 -24- 200843598 群的配線基板11。故而，藉由上治具1 3可確保地按壓處於 凸塊形成區域AR1內之複數個焊料凸塊22而平坦化。 [第2實施形態] 其次，參照第1 3至第16圖，詳細說明具體化本發明 的第2實施形態。在此，以與第1實施形態相異之部分爲 重點進行說明，而針對共同部分，則賦予相同之元件符號， 並改而省略說明。 在本實施形態中，係在供給助焊劑28前之焊料凸塊 ® 111的頂部112具有凹凸且表面全體由氧化膜113所被覆之 點，及未藉由焊料凸塊平坦化裝置1 0加以平坦化之點，係 與上述第1實施形態相異（參照第1 3圖）。以下，說明本實 施形態之配線基板11a(附帶有零件之配線基板）的製造方 法。 首先，在焊料凸塊配置步驟中，將焊墊2 1上印刷有焊 料膏之配線基板本體1 2配置於迴焊爐內，加熱至比焊料之 φ 融點更高出1 〇〜40°c的溫度。在此時間點，將焊料膏熔化， 成爲凸起成半球狀之形狀的焊料凸塊1 1 1。接著，在焊料凸 塊成形步驟中，於配線基板11 a上配置模具（省略圖示），在 使模具之粗面接觸於焊料凸塊1 11之表面的狀態下冷卻焊 料凸塊1 1 1。其結果，形成在頂部1 1 2形成有凹凸（粗化）之 焊料凸塊11 1 (參照第1 3圖）。另外，將焊料凸塊1 1 1之表 面氧化，且由鉛構成之氧化膜11 3被覆焊料凸塊1 11之整 個表面。又，亦可藉由CZ處理或使用硏磨裝置之硏磨等的 -25- 200843598 其他方法將焊料凸塊111之頂部112粗化。 接著，在助焊劑供給步驟中，將助焊劑28供給於各焊 料凸塊1 1 1之表面全體（頂部11 2及側面）。藉此，以形成於 頂部1 1 2之凹凸爲起點將氧化膜1 1 3熔化，露出構成凹凸 之突起的前端（參照第14圖）。其後，只要於配線基板本體 12之背面23形成複數個焊墊24，並於各焊墊24上焊接上 針腳25，即可完成配線基板11a。 又，在加熱熔化步驟中，使1C晶片45之複數個連接 端子47對應地配置於複數個焊料凸塊111上（參照第15 圖），並將各焊料凸塊111加熱熔化（迴焊）。藉此，使助焊 劑28氣化，同時對各焊料凸塊11 1與各連接端子47進行 接合（參照第1 5及第1 6圖），完成附帶有零件之配線基板。 藉此，在本實施形態中，氧化膜113之一部分，在助 焊劑供給步驟中利用將助焊劑28供給於各焊料凸塊111而 被熔化，使使焊料凸塊Π 1之表面露出於被熔化之部分。 其結果，在達到焊料凸塊11 1之融點（本實施形態中爲1 8 3 °C )的時間點，焊料凸塊Π 1開始熔化，所以，使得焊料凸 塊111容易熔化，而容易進行焊料凸塊111與1C晶片45 之連接。 又，本發明之實施形態亦可依如下方式進行變更。 在上述第1實施形態中，在焊料凸塊成形步驟中，在 將焊料凸塊22之頂部27平坦化的同時亦進行了粗化’但 是，在焊料凸塊成形步驟中，亦可分別進行將頂部27平坦 -26- 200843598 化之平坦化步驟及將頂部27粗化的粗化步驟。 在上述第1實施形態中，藉由使用上治具13來加壓複 數個焊料凸塊22之頂部27，而將頂部27加以平坦化及粗 化。但是，亦可藉由平面硏磨而將焊料凸塊22之頂部27 加以平坦化及粗化。例如，將具有複數個焊料凸塊22之配 線基板1 1載置於具有多個通孔的真空吸附板上，並減低真 空吸附板之下面側的氣壓，藉由真空吸附來固定配線基板 11。其次，使用具有類似硏磨機之旋轉硏磨板的硏磨裝置， 整體地硏磨複數個焊料凸塊22之頂部27。具體而言，使粗 度爲#1000之圓板狀的旋轉硏磨板，以120rpm進行旋轉， 並以0.2mm/秒之速度下降，整體地硏磨複數個焊料凸塊22 之頂部27，而加以平坦化及粗化。又，硏磨方式可使用乾 式及濕式之兩種方法。 在上述第2實施形態中，雖製造了具有頂部112未被 平坦化之焊料凸塊1 1 1的配線基板1 1 a(附帶有零件之配線 φ 基板），但如第17圖所示，亦可製造具有頂部122被平坦 化之焊料凸塊1 2 1的配線基板1 1 b (附帶有零件之配線基 板）。 上述實施形態之焊料凸塊22,1 1 1係可應用於配線基板 1 1，1 1 a及1C晶片45之接合用者，但例如，亦可應用於配 線基板1 1，1 1 a及主機板之接合。 再者，在申請專利範圍所記載之技術思想之外，以下， 列舉由該實施形態所把握之技術思想。 -27· 200843598 (1) 一種附帶有零件之配線基板的製造方法，係接合有 配置於配線基板本體之表面側的複數個焊料凸塊及配置於 零件之底面側的複數個連接端子的附帶有零件之配線基板 的製造方法，其特徵爲包含：平坦化步驟，係以高度成爲 一致的方式對複數個焊料凸塊之頂部加壓而加以平坦化； 粗化步驟，係將複數個焊料凸塊之頂部加以粗化；助焊劑 供給步驟，係將助焊劑供給於平坦化及粗化後之複數個焊 料凸塊之頂部；及加熱熔化步驟，係使該零件之該複數個 ® 連接端子對應地配置於已完成助焊劑供給之該複數個焊料 凸塊上，並在此狀態之下將該複數個焊料凸塊加熱熔化。 (2) —種附帶有零件之配線基板的製造方法，係接合有 配置於配線基板本體之表面側的複數個焊料凸塊及配置於 零件之底面側的複數個連接端子的附帶有零件之配線基板 的製造方法，其特徵爲包含：焊料凸塊成形步驟，係使複 數個焊料凸塊之頂部加以平坦化及粗化；助焊劑供給步 ^ 驟，係將助焊劑供給於平坦化及粗化後之該複數個焊料凸 塊之頂部；及加熱熔化步驟，係將該零件之該複數個連接 端子對應地配置於已完成助焊劑供給之該複數個焊料凸塊 上，並在此狀態之下將該複數個焊料凸塊加熱熔化，在該 焊料凸塊成形步驟中，使用具有按壓用粗面之按壓治具進 行加壓以使複數個焊料凸塊之頂部的高度一致，藉此，將 該頂部加以平坦化同時粗化，該按壓治具係具有加熱該按 壓治具用之加熱手段。 -28- 200843598 (3)—種附帶有零件之配線基板的製造方法，係 配置於配線基板本體之表面側的複數個焊料凸塊及 零件之底面側的複數個連接端子的附帶有零件之配 的製造方法，其特徵爲包含：焊料凸塊成形步驟， 數個焊料凸塊之頂部加以平坦化及粗化；助焊劑 驟，係將助焊劑供給於平坦化及粗化後之該複數個 塊之該頂部；及加熱熔化步驟，係使該零件之該複 接端子對應地配置於已完成助焊劑供給之該複數個 塊上，並在此狀態之下將該複數個焊料凸塊加熱熔 該焊料凸塊成形步驟中，使用具有按壓用粗面之 壓治具進行加壓以使複數個焊料凸塊之頂部的高 藉此，將該頂部加以平坦化而同時粗化，該按壓 有加熱該按壓治具用之加熱手段。 (4)一種具有焊料凸塊之配線基板，其特徵爲： 被平坦化及粗化之複數個焊料凸塊配置於配線基® 表面上，同時該頂部之共面性的測定値，每1 cm2 I 以下，且表面粗度Ra爲0·3 // m以上、5 // m以下， 線基板本體之表面至該頂部的高度，係1 〇 M m以」 m以下。 (5)—種焊料凸塊平坦化裝置，係將表面側設 焊料凸塊之配線基板支撐於支撐治具上，並在此 藉由按壓治具按壓該複數個焊料凸塊而加以平 置，其特徵爲：該支撐治具具備支撐部，其具有 接合有 配置於 線基板 係將複 供給步 焊料凸 數個連 焊料凸 化，在 瓷製按 一致， 具係具 將頂部 本體之 I 1 0 // m 自該配 :、30 μ f複數個 〔態下， ,化之裝 『接觸於 -29- •200843598 該配線基板本體之背面的接觸面，該按壓治具具備表面粗 度Ra爲〇.3/zm以上、2//m以下之按壓用粗面。 【圖式簡單說明】 第1圖爲顯示第1實施形態之焊料凸塊平坦化裝置的 槪略構成圖。 第2圖爲實施焊料凸塊成形步驟前之配線基板的槪略 俯視圖。 第3圖爲實施焊料凸塊成形步驟前之配線基板的槪略 _剖視圖。 第4圖爲顯示1C晶片與實施焊料凸塊成形步驟後之配 線基板的要部剖視圖。 第5圖爲加熱熔化步驟之說明圖。 第6圖爲加熱熔化步驟之說明圖。 第7圖爲第1比較例之說明圖。 第8圖爲第1比較例之說明圖。 φ 第9圖爲第1比較例之說明圖。 第1 0圖爲第2比較例之說明圖。 第1 1圖爲第2比較例之說明圖。 第12圖爲第2比較例之說明圖。 第1 3圖爲顯示第2實施形態之焊料凸塊成形步驟實施 後之配線基板的要部剖視圖。 第1 4圖爲顯示同樣實施形態之助焊劑供給步驟實施 時之配線基板的要部剖視圖。 -30- 200843598 第1 5圖爲同樣實施形態之加熱熔化步驟之說明圖。 第1 6圖爲同樣實施形態之加熱熔化步驟之說明圖。 弟17圖爲顯75其他之實施形態之焊料凸塊成形步驟 實施後之配線基板的要部剖視圖。 第18圖爲習知技術之焊料凸塊成形步驟的說明圖° 第1 9圖爲顯示同樣習知技術之1C晶片與焊料凸塊成 形後之配線基板的要部剖視圖。 【主要元件符號說明】Au-Sn-based solder, Au-Si-based solder, and the like. In particular, it is preferable that the plurality of solders are made of lead-free solder. Thereby, since the lead is not contained in the solder bump, the burden on the environment of the wiring board can be reduced. In addition, lead-free solders are less wet than lead-containing solders, and there is a tendency for the amount of voids to increase. Therefore, if the top of the solder bumps is roughened and the flux is easily released, it is even more Effectively prevent the creation of voids. Here, examples of the lead-free solder include Sn-Sb-based solder, Sn-Ag-based solder, Sn-Ag-Cu solder, Au-Ge solder, Au-Sn solder, and Au-Si solder. Further, in the heating and melting step (joining step of the member), the solder bump is heated to be melted to change its surface tension into a spherical shape to increase its height. Thereby, in the solder bump forming step, if the top of the solder bump is largely flattened to increase the diameter of the top portion. 200843598 When performing the heating and melting step, the top can be brought closer to the connection terminals of the part. Therefore, even when the measurement of the coplanarity at the top of the solder bump is slightly large, the bonding of the solder bump to the connection terminal can be easily performed. In the solder bump forming step, pressurization is performed using a pressing jig having a pressing rough surface to make the heights of the tops of the plurality of solder bumps uniform, thereby flattening and simultaneously roughening the top portion into Preferably. According to this, the wiring board of the first and second means can be efficiently manufactured. Further, in the case of performing the solder bump forming step, the pressing jig may be heated by a heating means such as a heater or may not be heated. In the case of heating the jig, the solder bumps are softened to some extent. Therefore, the solder bump is easily deformed as compared with the case where it is performed at a normal temperature, and the top of the solder bump can be surely flattened without excessively increasing the stress of the pressing jig. On the other hand, in the case where the jig is not heated, the heating means is not required, and the top of the solder bump can be flattened by a simple configuration. Here, the pressing jig is preferably made of a metal material such as titanium or stainless steel, a ceramic material such as alumina, tantalum nitride, niobium carbide or boron nitride, or a glass material. A wet (or less wettable) solder material is preferred. In particular, the pressing jig can be composed of a ceramic material having high processing precision and small deformation to heat. Further, it is preferable to press the rough surface of the pressing jig. According to this, since a uniform pressing force is applied to each of the solder bumps, the top of each solder bump can be planarized with high precision. -10- also 200843598 Further, as another means for solving the above problem (third means), a method of manufacturing a wiring board having solder bumps, comprising: a solder bump disposing step, which is a plurality of solders The bump is disposed on the surface side of the wiring substrate body; and the solder bump forming step is to roughen the tops of the plurality of solder bumps. According to the third method, in the solder bump forming step, the tops of the plurality of solder bumps are roughened to form minute recesses, so that the flux is easily accumulated in the portions. In addition, the unevenness formed on the top of the solder bump also serves as a gas escape path for the flux vaporized when the solder bump is heated, so that the vaporized flux can be surely passed from the top through the gas escape path. Released to the outside. Therefore, it is possible to prevent the occurrence of voids caused by the accumulation of the flux after vaporization in the solder bumps. Thereby, the reliability of connection of the solder bumps to other parts can be improved. Further, as another means for solving the above-described problems (fourth means), a method of manufacturing a wiring board with components is used, in which a plurality of solder bumps disposed on the surface side of the wiring board main body are bonded and disposed on the components. A method of manufacturing a wiring board with a component of a plurality of connection terminals on the bottom surface side, comprising: a solder bump forming step of roughening a top portion of the plurality of solder bumps; and a flux supply step A flux is supplied to the top of the plurality of solder bumps after roughening. According to the fourth method, in the solder bump forming step, the tops of the plurality of solder bumps are roughened to form minute recesses, so that the flux is easily accumulated in the portions. In addition, the unevenness formed on the top of the solder bump of -11-200843598 also serves as a gas escape path for the flux vaporized when the solder bump is heated, so that the vaporized flux can pass through the gas escape path. It is reliably released from the top to the outside. Therefore, it is possible to prevent the occurrence of voids caused by the accumulation of the flux after vaporization in the solder bumps. Thereby, the reliability of connection of the solder bumps to other parts can be improved. Moreover, the entire surface of the solder bump is covered by an oxide film having a higher melting point than the solder bump, so that even if the melting point of the solder bump is reached by heating, it is not easy to melt the solder bump (reflow). . Therefore, the connection of solder bumps to other ® parts becomes difficult. Here, in the case where the top portion of the plurality of solder bumps before the supply of the flux has irregularities and the entire surface is covered with an oxide film, in the flux supply step, the flux is utilized as the oxide film. It is preferable to supply the top portion of the plurality of solder bumps to be melted. Thereby, the surface of the solder bump is exposed to a portion where the oxide film is melted. As a result, the solder bumps are melted at the point of reaching the melting point of the solder bumps, so that the solder bumps are easily melted, and the solder bumps can be easily connected to other parts. In addition, the top of the solder bump has a convex shape, so that the flux can be surely held in this portion. Therefore, the oxide film which is easy to be used at the top is preferentially melted. Further, as another means for solving the above-described problems (the fifth means), a wiring board having solder bumps is provided, in which a plurality of solder bumps whose top portion is flattened and roughened are disposed on a wiring board body On the surface, at the same time, the measurement of the coplanarity of the top portion is 10 μm or less per 1 cm 2 , and the surface roughness Ra is 0. 3"m or more, 5/zm or less. -12- . According to the wiring board of the fifth aspect, the tops of the plurality of solder bumps are flattened, and the measurement of the coplanarity is 1 0 // m or less per 1 cm 2 , so that it can be surely and easily Parts are connected. Assuming that the measurement of coplanarity is greater than 10 // m per 1 cm 2 , a deviation occurs in the height of each solder bump, and there is a possibility of poor connection with other parts. Moreover, the tops of the plurality of solder bumps are roughened, and the surface roughness Ra is 0. Since it is 3/zm or more and 5/zm or less, the flux contained in the solder bump is vaporized at the time of heating and melting, and is reliably released from the top to the outside. Therefore, it is possible to prevent the occurrence of voids caused by the accumulation of the flux after vaporization in the solder bumps. Assume that the surface roughness Ra is less than 0. At 3 / z m, the flux after vaporization is likely to accumulate in the solder bumps, and voids are likely to occur. On the other hand, if the surface roughness Ra is larger than 5 // m, a deviation occurs in the height of each solder bump, and there is a possibility that the measurement of coplanarity is increased. As a result, there is a fear that the bonding strength between the solder bumps and other components is lowered. Further, when the surface roughness Ra is larger than 5 μm, a deep concave portion is formed on the top of the solder bump, so that the flux accumulated in the concave portion may not be easily released to the outside. Here, the "coplanarity" described in the present specification is the lowermost uniformity of the terminal defined by "Measurement method for the size specified by the Japan Electromechanical Industry Association EIAJ ED-7304 BGA". In addition, the "measurement of coplanarity" is a measurement which is defined by the "method of measuring the size of ED-7304 BGA" and is a plurality of welds 13 on the surface of the main body of the wiring board: 200843598 The indicator of homogeneity. In addition, the "surface roughness Ra" described in the present specification is an arithmetic mean roughness Ra defined by JIS B0601. Further, the method of measuring the surface roughness Ra is in accordance with ns B065 1. [Embodiment] [First Embodiment] Hereinafter, a first embodiment of the present invention will be described in detail with reference to Figs. 1 to 6 . Fig. 1 is a schematic view of a solder bump flattening device 10. Fig. 2 is a schematic plan view of the wiring board 1 1 set on the solder bump flattening device 10, and Fig. 3 is a schematic cross-sectional view of the same figure. As shown in Fig. 1, the solder bump flattening device 10 includes a jig 13 for pressing the jig, a jig 14 for supporting the jig, and a wiring substrate 11 for treatment. It has a mobile fixture 1 for 5 and so on. As shown in the second and third figures, the wiring board 1 of the present embodiment is a pin-shaped gate array (PGA) type semiconductor package which can be connected to a multi-terminal high-density flip-chip connection such as an MPU. Specifically, the wiring board 1 1 is formed on the upper and lower surfaces of a core material substrate made of a resin such as a bismaleimide-triazine containing glass fibers, and a plurality of layers of the resin insulating layer are laminated by a known method. Multilayer wiring substrate. The multilayer wiring board is a flat member having a thickness of about 1 mm and a side length of about 40 mm, and a copper wiring (not shown) is provided between the resin insulating layers. The surface 20 (the upper surface in Fig. 3) of the wiring board main body 12 constituting the wiring board 11 is a substantially square central region as a bump forming region -14- • 200843598 AR1. In the bump formation region AR1, a plurality of pads 21 for bonding the 1C wafer 45 (see Fig. 4 and the like) are formed in a substantially lattice-like arrangement, and solder bumps 22 are formed on the pads 2 1 . The pad 2 1 is formed by a plurality of electroplated layers having a diameter of 150/z m and a thickness of 20 m. The solder bump 22 is formed by printing a solder paste on the pad 21 of the surface 20 of the wiring substrate 1 and forming it by reflow, and has a convex hemispherical shape. Further, the solder bumps 22 of the present embodiment are made of a Sn-Ag-based solder of lead-free solder. Further, a plurality of pads 24 are formed in a substantially lattice-arranged manner over the entire range of the back surface 23 (the lower surface in FIG. 3) of the wiring board main body 12, and a socket is bonded to each of the pads 24 by soldering. A plurality of pins 25 are provided. Further, each of the stitches 25 disposed on the back surface 23 side of the wiring board 1 1 is soldered with a solder having a higher melting point than the solder bumps 22 on the surface 20 side. As shown in Fig. 3 and the like, each of the stitches 25 has a shaft portion having a circular cross section and a head portion 26 having a larger diameter than the shaft portion. The head 26 is provided with solder to the pad 24. φ Further, each of the stitches 25 is once set in a pin insertion hole of a dedicated positioning jig (not shown), and is joined to the wiring board 1 1 by a single soldering step. Therefore, the positional accuracy of each of the stitches 25 of the wiring substrate 1 can be made high. The movable jig 15 shown in Fig. 1 is moved in the horizontal direction along the transport path by a transport device (not shown) while supporting the four corners of the wiring board 11, and is moved in the vertical direction. The wiring board 11 is set to the lower jig 14 by moving the horizontal and vertical movement of the jig 15 by this. -15- 200843598 The lower part of the upper jig 13 is a flat pressing surface 3 0. In the present embodiment, the flatness of the pressing rough surface 30 is set to be 10 μm or less per 1 cm 2 , and the surface roughness Ra of the pressing rough surface 30 is set to 0. 4/zm. The upper jig 13 is driven downward by a pressing device (a pneumatic pressurizing device or a hydraulic pressurizing device, etc.) (not shown), and the solder bump 22 is pressed by the pressing rough surface 30. Thereby, the solder bumps 22 are planarized while the upper surface of the top portion 27 of the solder bumps 22 is also roughened (refer to Fig. 4). Further, in the present embodiment, the upper jig 13 is made of a ceramic material (boron nitride). As shown in Fig. 1, the lower jig 14 has a support portion 31 which protrudes in a quadrangular column shape at its central portion. The front end surface (upper end surface) of the support portion 31 is a contact surface 32 that can be in contact with the back surface 23 of the wiring board main body 12. On the contact surface 32 of the support portion 31, a plurality of stitch escape holes 34 that are open upward are arranged in a lattice shape at equal distances from the stitches 25. In the stitch escape hole 34 of the present embodiment, a portion deeper than the opening portion is formed into an equal cross-sectional shape, and is formed such that the opening portion gradually increases toward the open end (upper end) direction by φ. Further, the opening portion of the stitch escape hole 34 has an aperture which can accommodate the size of the head portion 26 of the stitch 25, and has a slight gap with respect to the diameter of the tip end side of the stitch. Further, it is preferable that the support portion 31 of the lower jig 14 is formed of a metal material having high mechanical strength, and for example, a superhard alloy composed of tungsten carbide (WC), cobalt (Co) or the like can be used. As shown in Fig. 1, the solder bump flattening device 10 of the present embodiment is provided with electric heaters 41, 42 for heating the upper jig 13 and the lower jig 14 to a predetermined temperature. The fixtures are heated by the electric heaters 41, 42. In the state of 200843598 13, 14, the flattening and roughening treatment of the top portion 27 of the solder bump 22 is performed. The height of the solder bumps 22 after planarization and roughening shown in FIG. 4 from the surface 20 of the wiring substrate body 12 to the top 27 of the solder bumps 22 is set to 3 0 in the present embodiment. / m. In addition, the surface roughness Ra of the top 2 7 is set to 〇. 4/zm, a convex surface is produced on the flat surface of the top portion 27. Further, the measurement of the coplanarity of the top portion 27 is equal to the flatness of the pressing rough surface 30 of the upper jig 13, and is set to be l〇/zm or less per 1 cm 2 . ® Further, the maximum diameter of the solder bump 2 2 after planarization and roughening is set to be 0 of the diameter of the pad 21. 5 times or more, 1. 2 times or less is preferred. It is assumed that the maximum diameter of the solder bumps 2 2 is 1. If it is twice as large, when the solder bumps 22 are heated and melted to bond the 1C wafer 45, the solder overflowing from the pads 21 contacts the solder bumps 22 of the adjacent pads 2 1 , which may cause a short circuit. Hey. On the other hand, if the maximum diameter of the solder bump 22 is less than 0 of the pad 21. At 5 times, even if the heating and melting of the solder bumps φ 22 is not increased too high, the top portion 27 is not easily accessible to the connection terminals 47 of the 1C wafer 45, so that the bonding of the solder bumps 22 to the connection terminals 47 is not easily performed. . Further, in the present embodiment, since the diameter of the pad 21 is 150 / m, the maximum diameter of the solder bumps 22 is preferably 75 // m or more and 180 μm or less. In addition, the diameter of the top portion 27 of the solder bump 22 is set to be 0 of the maximum diameter of the solder bump 22. 5 times or more, less than 1. 0 times is preferred, and is set to 0 of the maximum diameter of the solder bumps 22. 8 times or more, less than 1. 0 times is better. Assume that the diameter of the top portion 27 is less than the maximum diameter of the solder bumps 22 -17- 200843598. At 5 times, it is impossible to accumulate the flux 28 required for bonding the ic wafer 45 to the flat surface of the top portion 27. On the other hand, if the diameter of the top portion 27 is the maximum diameter of the solder bumps 22. When it is 0 or more times, when the solder bumps 22 are heated and melted to bond the 1C wafer 45, the solder constituting the top portion 27 is in contact with the solder bumps 22 of the adjacent pads 21, which may cause a short circuit. Further, in the present embodiment, the maximum diameter of the solder bumps 22 is 75 μm or more and 180//m or less. Therefore, the diameter of the top portion 27 is preferably 37. 5// m or more, less than 180/zm. ® Next, a method of manufacturing the wiring board 1 1 (and a wiring board with components attached thereto) according to the present embodiment will be described. The wiring board 11 is manufactured as follows. First, a resin insulating layer made of an epoxy resin is formed on a core material substrate, and copper wiring is formed on the surface of the core material substrate and the resin insulating layer by semi-addition using electroless copper plating and electrolytic copper plating. Thereby, the wiring substrate body 12 is formed. Further, the copper wiring can be formed by a subtractive color method or a full addition method. φ Next, a plurality of pads on the surface 20 of the wiring substrate main body 12 are subjected to electroless Ni-P plating, and electroless Au plating is performed to form a pad composed of a Ni-P plating layer and an Au plating layer. twenty one. Further, on the surface 20 of the wiring board main body 12 where the pad 21 is not formed, a solder resist 19 is formed using an acrylic resin, an epoxy resin or the like (see Fig. 4 and the like). Then, in the solder bump disposing step, the solder paste is printed on the pad 21 formed on the surface 20 of the wiring substrate body 12 by using a metal mask (not shown). Then, the wiring substrate body 1 2 on which the solder paste has been printed is placed in the -18-200843598 soldering furnace, heated to a temperature higher than the melting point of the solder by 10 to 40 ° C, and then cooled. Thereby, a plurality of solder bumps 22 which are convex in a hemispherical shape are disposed on the surface 20 side of the wiring board main body 12. Further, a plurality of pads 24 are formed on the back surface 23 of the wiring substrate main body 12, and the pins 25 are soldered to the pads 24. As a result, the wiring board 11 is completed (refer to the first to third figures). Next, the wiring board 1 1 is set on the moving jig 15 in a state where the surface 20 side is upward. Further, the upper jig W 1 3 and the lower jig 14 are heated to 1 1 〇 ° C by the electric heaters 4 1,42. Then, the wiring board 1 1 is supported by the support portion 31 of the lower jig 14 by the transport and lifting operation of the movable jig 15 . As a result, on the back surface 23 of the wiring board 1 1 , the plurality of stitches 25 in the supported area AR2 (see FIGS. 1 and 3 ) are reliably guided to the stitch escape holes formed on the support portion 31 . 34 is supported while the wiring board 1 1 is in close contact with the contact surface 32 of the support portion 31. Next, in the solder bump forming step, the upper jig 13 is lowered, and the top surface 27 of each solder bump 22 on the wiring substrate 11 is pressurized by the pressing rough surface 30 of the upper φ jig 13. At this time, the pressure is applied to the height of each of the top portions 27 so as to be uniform. Thus, the top portion 27 of each solder bump 22 is positively and uniformly applied with pressure (in this embodiment, each bump is 〇. 〇 7 kg), and as a result of crushing the top portion 27, the solder bumps 22 are flattened and roughened. Then, the wiring substrate 1 1 which has completed the solder bump forming step is transported to the outside of the apparatus by the transport and lifting operation of the moving jig 15 . Thereafter, in the flux supply step, the flux 28 is supplied to the top 27 of each of the solder bumps 22 after planarization and thickening. Further, as a method of supplying the flux 28, a method of applying the liquid flux 28 to the top portion 27, a method of supplying the liquid flux 28 to the top portion 27 by the flux distributor, and a bubble shape may be mentioned. A foaming method in which the flux 28 is in contact with the top portion 27, a spray method in which the mist-like flux 28 is sprayed on the top portion 27, and the like. Further, the type of the flux 28 is not particularly limited, and a known method can be used. Further, in the heating and melting step, the plurality of connection terminals 47 disposed on the bottom surface 46 side of the 1C wafer 45 are disposed correspondingly to the plurality of solder bumps that have been disposed on the surface 20 side of the wiring substrate 11 to complete the flux supply. 22 (refer to Figure 4). Further, in this state, each of the solder bumps 22 is heated and melted (reflowed), whereby the flux 28 is vaporized, and each solder bump 22 is soldered to each of the connection terminals 47 (see FIGS. 5 and 6). ). As a result, the wiring board with the components of the 1C wafer 45 mounted on the wiring board 1 is completed. φ □ ′′ Describes the evaluation methods and results of coplanarity and voids. First, a sample for measurement was prepared as follows. A substrate in which solder bumps 22 (flattened and roughened solder bumps) similar to those in the present embodiment are prepared is used as an embodiment. Further, a substrate 82 (see Fig. 7) in which the solder bumps 81 which are not flattened or roughened are disposed is prepared, and this is taken as the first comparative example. Further, a substrate 9 2 (see FIG. 10) in which the solder bumps 9 1 (thin but not flattened but not roughened) are disposed in the same manner as the conventional technique, and this is used as the second comparative example. . Further, in the embodiment -20- 200843598, the surface roughness Ra of the top portion 27 of the solder bump 22 is 0. 4 // m, the surface roughness Ra of the top of the solder bump 91 of the second comparative example is 0. 05 # m. Next, the samples for measurement (Examples, First and Second Comparative Examples) were measured for coplanarity. Further, in order to improve the evaluation reliability, the measurement was performed twice and the measurement was performed twice. Further, the coplanarity measurement of the solder bumps 81 which are not flattened and the measurement of the coplanarity of the planarized solder bumps 22, 91 cannot be performed using the same measuring device. Here, in the measurement of the coplanarity of the solder bumps 81, a measuring device manufactured by Solvi Si on Co., Ltd. was used, and in the measurement of the coplanarity of the solder bumps 22 and 91, a measuring instrument manufactured by Kono Co., Ltd. was used. . As a result of the coplanarity measurement, the measurement of the coplanarity of the solder bumps 8 1 of the first comparative example which was not planarized was the largest. On the other hand, it was confirmed that in the solder bumps 22 of the embodiment and the solder bumps 9 1 of the second comparative example, the measurement of the coplanarity can be reduced. Further, it was confirmed that the results of the second coplanarity measurement were the same as those of the first measurement. φ Further, voids were measured for each of the measurement samples (Examples, First and Second Comparative Examples). Specifically, the solder bumps 22, 81, and 91 are joined to the connection terminal 102 disposed on the bottom surface side of the dummy wafer 1 〇1, and the state at this time is observed, thereby measuring the cavity (refer to the eighth, ninth , 11th and 12th). Specifically, although the cavity was not confirmed before the bonding of the dummy wafer 110, the portion where the cavity was confirmed was started after the bonding of the dummy wafer 110, and the X-ray diffraction apparatus (XRD) was observed (XRD). Observe) to count the number of holes. In addition, the number of holes is also counted by observing (cross-observing) the faces of the solder bumps 22, 81, 91 from -21 to 200843598. In addition, in order to improve the reliability of various observations, the creation date of the sample for measurement was changed and each of the two was determined. In addition, the number of voids can be counted by XRD observation in a state where the heat of the same temperature as the temperature at which the solder bumps 22, 81, and 91 are heated and melted is added, and the comparative example is confirmed. The largest number of voids 93 are created on the solder bumps 91. It is to be noted that the number of the solder bumps 2 2, 8 1 of the first embodiment and the first comparative example is smaller than that of the second comparative example. Further, it was also confirmed that the number of voids generated by the bumps 22 of the example was almost the same as the number of voids generated by the solder of the first comparative example. Further, although the number of voids was counted again by the XRD observation, it was confirmed that the results were the same as those of the XRD observation. Further, the number of voids was counted by cross observation. 2 A large number of voids 93 were formed in the solder bumps 9 1 of the comparative example. In the second comparative example, 9 of the 9 solder bumps 91 were produced 93, and the generation rate of the void 93 was 9/98 = about 9. 2%. On the other hand, the number of spaces generated by the solder bumps 22, 81 of the first embodiment and the first comparative example is smaller than that of the second comparative example. Specifically, the two solder bumps 22 in the embodiment generate voids, and the generation rate of voids is about 2. 0%. In the first comparative example, voids were generated in one of the 98 solders, and the generation rate of voids was 1/9 8 = about 1·〇%. On the other hand, the cavity 93 generated in the solder bump 91 of the second comparative example is more than the cavity generated by the solder bumps 22 and 81 of the first comparative example. The 2nd surface, the solder bump 81 which is indeed empty, is the 2nd and the 1st time. In the 1st, the cavity is confirmed, and the ί hole is confirmed. At 98, it is 2/98=bump 81. -22, -22- 200843598 It was confirmed that the number of voids generated by the solder bumps 2 of the embodiment was slightly larger than the number of voids generated by the solder bumps 81 of the first comparative example, but the size was the same. Further, the second cross observation is performed, and the number of voids generated by the solder bumps 81, 91 of the first and second comparative examples is counted again. Further, the number of voids generated by the solder bumps 22 of the embodiment is substantially the same as that of the first comparative example. Therefore, the second cross observation is not particularly performed. As a result, it was confirmed that there was a tendency to observe the same as the first cross observation. That is, ^ In the second comparative example, the cavity 93 is generated in the three solder bumps 91 of 144, and the generation rate of the cavity 93 is 3/144 = about 2. 0%. On the other hand, in the first comparative example, a void is generated in one of the 144 solder bumps 8 1 , and the generation rate of the cavity becomes 1/144 = about 0. 7%. From the above evaluation, it was confirmed that the measurement of the coplanarity of the solder bumps 22 and 91 of the second comparative example was better than the measurement of the coplanarity of the solder bumps 8 1 of the first comparative example. small. As a result, it has been confirmed that when the wiring substrate 11 φ is used in the embodiment and the second comparative example, connection failure is unlikely to occur in connection with the connection terminal 102 of the wafer 1 假设 1 . However, it is also confirmed that the number of voids 9 3 generated by the solder bumps 9 1 of the second comparative example is larger than the number of voids generated by the solder bumps 22 and 81 of the first and comparative examples. And bigger. As a result, it has been confirmed that the embodiment in which the measurement of the coplanarity is small and the occurrence of voids is small is suitable for application to the wiring board. Thereby, according to the present embodiment, the following effects can be obtained. (1) In the wiring substrate 11 of the present embodiment, the top portion 27 of the plurality of solder bumps 22 is flattened in the solder bump forming step -23-200843598, and the measurement of the coplanarity is 10/ per 1 cm 2 . Since zm is equal to or less, it is possible to reliably and easily connect to the connection terminal 47 of the 1C wafer 45. Therefore, it is possible to prevent the problem that one of the solder bumps 22 and the connection terminal 47 become unconnected (poor opening). Moreover, in the solder bump forming step, the top portion 27 of each solder bump 22 is roughened, and the surface roughness Ra is 0. 4 A m, and fine irregularities are formed on the flat surface of the top portion 27, so that the flux 28 easily accumulates in the portion ® . Further, the unevenness formed on the top portion 27 also serves as a gas escape passage for the flux vaporized at the time of heating and melting, so that the vaporized flux 28 can be surely released from the top portion 27 to the outside through the gas escape passage. . Therefore, it is possible to prevent the occurrence of voids caused by the accumulation of the flux 28 after the vaporization in the solder bumps 22. Thereby, the connection reliability of the solder bumps 22 and the connection terminals 47 of the 1C wafer 45 can be improved. (2) In the present embodiment, the unevenness 'φ is formed on the flat surface of the top portion 27 so that the flux 28 for improving the adhesion to the connection terminal 47 is easily accumulated in the top portion 27. Therefore, in the heating and melting step, the flux is fluxed. 28 is easily accessible to the connection terminal 47. Therefore, the bondability between the solder bumps 22 and the connection terminals 47 can be improved. (3) In the present embodiment, when the solder bumps 22 are pressed, the pressing force is easily concentrated on the supported region AR2, and the support portion AR2 can be supported by the support portion 31 of the lower jig 14. Therefore, it is possible to prevent the wiring substrate 11 from being bent, and it is possible to reliably and easily obtain the wiring substrate 11 having the solder bumps -24-200843598 group excellent in the coplanarity. Therefore, the upper jig 13 can be surely pressed by pressing a plurality of solder bumps 22 in the bump forming region AR1. [Second Embodiment] Next, a second embodiment of the present invention will be described in detail with reference to the first to sixth figures. Here, the differences from the first embodiment will be mainly described, and the same reference numerals will be given to the common elements, and the description will be omitted. In the present embodiment, the top portion 112 of the solder bumps 111 before the supply of the flux 28 has irregularities and the entire surface is covered by the oxide film 113, and is not flattened by the solder bump flattening device 10 The point of the change is different from that of the first embodiment described above (see Fig. 3). Hereinafter, a method of manufacturing the wiring board 11a (a wiring board with components) of the present embodiment will be described. First, in the solder bump disposing step, the wiring substrate body 1 2 on which the solder paste is printed on the pad 2 is disposed in the reflow furnace, and is heated to a temperature higher than the melting point of the solder by 1 〇 40 ° C. temperature. At this point of time, the solder paste was melted to become a solder bump 1 1 1 which was convex in a hemispherical shape. Then, in the solder bump forming step, a mold (not shown) is placed on the wiring board 11a, and the solder bumps 1 1 1 are cooled while the rough surface of the mold is brought into contact with the surface of the solder bumps 1 11 . As a result, solder bumps 11 1 having irregularities (roughening) formed on the top portion 112 are formed (see Fig. 3). Further, the surface of the solder bump 1 1 1 is oxidized, and the oxide film 11 3 made of lead covers the entire surface of the solder bump 1 11 . Further, the top 112 of the solder bump 111 may be roughened by a CZ process or other method of honing using a honing device, for example, -25-200843598. Next, in the flux supply step, the flux 28 is supplied to the entire surface (top portion 11 2 and side surface) of each of the solder bumps 1 1 1 . Thereby, the oxide film 141 is melted starting from the unevenness formed on the top portion 112, and the tip end of the projection constituting the uneven portion is exposed (see Fig. 14). Thereafter, a plurality of pads 24 are formed on the back surface 23 of the wiring substrate main body 12, and the pins 25 are soldered to the pads 24 to complete the wiring substrate 11a. Further, in the heating and melting step, a plurality of connection terminals 47 of the 1C wafer 45 are placed correspondingly on the plurality of solder bumps 111 (see Fig. 15), and each of the solder bumps 111 is heated and melted (reflowed). Thereby, the flux 28 is vaporized, and the solder bumps 11 1 are bonded to the respective connection terminals 47 (see FIGS. 15 and 16), and the wiring board with the components is completed. Therefore, in the present embodiment, a part of the oxide film 113 is melted by supplying the flux 28 to each of the solder bumps 111 in the flux supply step, so that the surface of the solder bump Π 1 is exposed to be melted. Part of it. As a result, the solder bumps 开始 1 start to melt at the point of reaching the melting point of the solder bumps 11 1 (180 ° C in the present embodiment), so that the solder bumps 111 are easily melted, which is easy to carry out. The solder bumps 111 are connected to the 1C wafer 45. Further, the embodiment of the present invention can be modified as follows. In the first embodiment, in the solder bump forming step, the top portion 27 of the solder bump 22 is flattened while being flattened. However, in the solder bump forming step, the solder bump forming step may be performed separately. The top 27 is flat -26-200843598 flattening step and the roughening step of roughening the top portion 27. In the first embodiment described above, the top portion 27 is flattened and roughened by pressing the top portion 27 of the plurality of solder bumps 22 by using the upper jig 13. However, the top 27 of the solder bump 22 can also be planarized and roughened by planar honing. For example, the wiring substrate 11 having a plurality of solder bumps 22 is placed on a vacuum suction plate having a plurality of through holes, and the air pressure on the lower side of the vacuum adsorption plate is reduced, and the wiring substrate 11 is fixed by vacuum suction. Next, the top 27 of the plurality of solder bumps 22 is integrally honed using a honing device having a rotary honing plate similar to a honing machine. Specifically, a disk-shaped rotary honing plate having a thickness of #1000 was rotated at 120 rpm and was set to 0. The speed of 2 mm/sec is lowered, and the top 27 of the plurality of solder bumps 22 is integrally honed and planarized and roughened. Also, the honing method can be either dry or wet. In the second embodiment, the wiring substrate 11a (the wiring φ substrate with components) having the solder bumps 1 1 1 whose top portion 112 is not flattened is manufactured, but as shown in Fig. 17, A wiring substrate 1 1 b (a wiring substrate with components) having a solder bump 1 2 1 whose top portion 122 is flattened can be manufactured. The solder bumps 22 and 11 1 of the above-described embodiment can be applied to the bonding users of the wiring substrate 1 1,1 1 a and the 1C wafer 45. However, for example, the wiring can be applied to the wiring substrate 1 1,1 1 a and the host. The joint of the boards. In addition to the technical ideas described in the patent application scope, the technical idea grasped by the embodiment will be listed below. -27. 200843598 (1) A method of manufacturing a wiring board with a component attached to a plurality of solder bumps disposed on a surface side of a wiring board main body and a plurality of connection terminals disposed on a bottom surface side of the component A method of manufacturing a wiring board of a component, comprising: a planarizing step of flattening a top of a plurality of solder bumps in such a manner that a height is uniform; and a roughening step of forming a plurality of solder bumps The top portion is roughened; the flux supply step is to supply the flux to the top of the plurality of solder bumps after planarization and roughening; and the heating and melting step is such that the plurality of connection terminals of the part are correspondingly The plurality of solder bumps are disposed on the plurality of solder bumps that have completed the flux supply, and the plurality of solder bumps are heated and melted in this state. (2) A method of manufacturing a wiring board with a component attached thereto, wherein a plurality of solder bumps disposed on a surface side of the wiring board main body and wirings with a plurality of connection terminals disposed on a bottom surface side of the component are bonded A method of manufacturing a substrate, comprising: a solder bump forming step of flattening and roughening a top portion of a plurality of solder bumps; and a flux supply step of supplying a flux to planarization and roughening And the heating and melting step, wherein the plurality of connection terminals of the part are correspondingly disposed on the plurality of solder bumps on which the flux supply has been completed, and in this state Heating and melting the plurality of solder bumps, and in the solder bump forming step, pressurizing with a pressing jig having a pressing rough surface to make the heights of the tops of the plurality of solder bumps uniform, thereby The top portion is flattened and roughened, and the pressing jig has heating means for heating the pressing jig. -28-200843598 (3) A method of manufacturing a wiring board with a component attached thereto, which is a plurality of solder bumps disposed on the surface side of the wiring board main body and a plurality of connection terminals on the bottom surface side of the component The manufacturing method is characterized by comprising: a solder bump forming step of flattening and roughening the tops of the plurality of solder bumps; and a fluxing step of supplying the flux to the plurality of blocks after planarization and roughening And the heating and melting step, wherein the multiplexed terminals of the component are correspondingly disposed on the plurality of blocks on which the flux supply has been completed, and in the state, the plurality of solder bumps are heated and melted In the solder bump forming step, the pressurization tool having the rough surface for pressing is pressed to raise the top of the plurality of solder bumps, and the top portion is flattened while being roughened, and the pressing is heated. Press the heating means for the fixture. (4) A wiring board having solder bumps, characterized in that a plurality of solder bumps which are flattened and roughened are disposed on a surface of the wiring base®, and the coplanarity of the top is measured, per 1 cm 2 I is as follows, and the surface roughness Ra is 0·3 // m or more and 5 // m or less, and the height from the surface of the wire substrate main body to the top portion is 1 m or less. (5) A solder bump flattening device for supporting a wiring substrate having a solder bump on a surface side thereof on a support jig, and pressing the plurality of solder bumps by a pressing jig to be flattened, The support fixture has a support portion, and has a joint disposed on the wire substrate to fix the solder bumps of the plurality of solder bumps, and the ceramics are uniformly aligned, and the top body is I 1 0 //m from the matching:, 30 μf in multiples [in the state, the device is in contact with the contact surface of the back of the wiring substrate body of -29- •200843598, the pressing fixture has a surface roughness Ra of 〇 . 3/zm or more and 2//m or less. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic block diagram showing a solder bump flattening apparatus according to a first embodiment. Fig. 2 is a schematic plan view showing a wiring board before the solder bump forming step. Fig. 3 is a schematic cross-sectional view showing the wiring board before the solder bump forming step. Fig. 4 is a cross-sectional view of an essential part showing a 1C wafer and a wiring substrate after the solder bump forming step. Figure 5 is an explanatory view of the heating and melting step. Figure 6 is an explanatory view of the heating and melting step. Fig. 7 is an explanatory view of the first comparative example. Fig. 8 is an explanatory view of the first comparative example. φ Fig. 9 is an explanatory view of the first comparative example. Fig. 10 is an explanatory diagram of the second comparative example. Fig. 1 is an explanatory view of a second comparative example. Fig. 12 is an explanatory view of a second comparative example. Fig. 1 is a cross-sectional view of a principal part of the wiring board after the solder bump forming step of the second embodiment is performed. Fig. 14 is a cross-sectional view of an essential part showing a wiring board in the case where the flux supply step of the embodiment is carried out. -30- 200843598 Figure 15 is an explanatory view of the heating and melting step of the same embodiment. Fig. 16 is an explanatory view showing a heating and melting step of the same embodiment. Figure 17 is a cross-sectional view of a principal part of a wiring board after the implementation of the solder bump forming step of the other embodiment. Fig. 18 is an explanatory view showing a solder bump forming step of the prior art. Fig. 19 is a cross-sectional view of a principal part showing a wiring board in which a 1C wafer and a solder bump of the same conventional technique are formed. [Main component symbol description]
1 1，1la，llb 配線基板 12 配線基板本體 13 作爲按壓治具之上治具 20 配線基板本體之表面 22,111,121 焊料凸塊 27,112,122 頂部 28 助焊劑 30 按壓粗面 45 作爲零件之1C晶片 46 零件之底面 47 連接端子 113 氧化膜 -31-1 1,1la,llb Wiring board 12 Wiring board body 13 As a jig upper fixture 20 Wiring board body surface 22, 111, 121 Solder bumps 27, 112, 122 Top 28 Flux 30 Pressing rough surface 45 As part of 1C wafer 46 Part of the bottom surface 47 connection terminal 113 oxide film-31-