CN107731786B - 重配置线路结构、封装体及导电特征的制造方法 - Google Patents
重配置线路结构、封装体及导电特征的制造方法 Download PDFInfo
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Abstract
一种重配置线路结构的制造方法至少包括以下步骤。首先,在衬底上形成层间介电层。接着,在层间介电层上形成种子层。然后,在种子层上形成多个导电图案,且种子层以及导电图案包括相同材料。通过执行干蚀刻工艺选择性地将被导电图案暴露出的种子层移除,以形成多个种子层图案,其中导电图案的宽度在干蚀刻工艺前后实质上维持一致。多个导电图案以及多个种子层图案形成多个重配置导电图案。
Description
技术领域
本发明实施例是涉及一种重配置线路结构的制造方法,且尤其涉及一种使用干蚀刻的重配置线路结构的制造方法。
背景技术
近年来,由于各种电子组件(例如晶体管、二极管、电阻器、电容器等)的积集度不断提升,半导体工业因而快速成长。这种积集度的提升是起因于最小特征尺寸的持续缩小,因而可以将更多的组件整合在一特定的区域中。相较于以前的封装体,这些较小的电子组件所需要占用的封装体面积也较小。一般而言,较小型的半导体组件封装包括有方型扁平式封装(Quad Flat Packages;QFPs)、插针网格阵列(Pin Grid Array;PGA)封装、球栅阵列(Ball Grid Array;BGA)封装等等。
目前来说,基于其紧密度,整合扇出型(Integrated Fan-Out;INFO)封装体日益受到欢迎。整合扇出型封装体通常具有重配置线路结构,其设置在被复合成型的集成电路组件上且用以读取集成电路组件的信号。为了达到小尺寸以及高封装密度的需求,重配置线路结构的制造方法成为本领域中一个重要的议题。
发明内容
根据本发明的一些实施例,一种重配置线路结构的制造方法至少包括以下步骤。首先,在衬底上形成层间介电层。接着,在层间介电层上形成种子层。然后,在种子层上形成多个导电图案,其中种子层以及导电图案包括相同材料。通过执行干蚀刻工艺选择性地将被导电图案暴露出的种子层移除,以形成多个种子层图案,其中导电图案的宽度在干蚀刻工艺前后实质上维持一致。多个导电图案以及多个种子层图案形成多个重配置导电图案。
附图说明
图1A至图1G为根据一些实施例所示出的一种整合扇出型封装体的制造方法的剖面图;
图1H为根据一些实施例所示出的一种叠层封装(Package on Package;POP)结构的剖面图;
图2A至图2H为根据一些实施例所示出的在图1D中的一种重配置线路结构的制造方法的剖面图。
具体实施方式
以下发明内容提供用于实施所提供的目标之不同特征的许多不同实施例或实例。以下所描述的构件及配置的具体实例是为了以简化的方式传达本发明为目的。当然,这些仅仅为实例而非用以限制。举例来说,于以下描述中,在第一特征上方或在第一特征上形成第二特征可包括第二特征与第一特征形成为直接接触的实施例,且也可包括第二特征与第一特征之间可形成有额外特征使得第二特征与第一特征可不直接接触的实施例。此外,本发明在各种实例中可使用相同的组件符号及/或字母来指代相同或类似的部件。组件符号的重复使用是为了简单及清楚起见,且并不表示所欲讨论的各个实施例及/或配置本身之间的关系。
另外,为了易于描述附图中所示出的一个构件或特征与另一组件或特征的关系,本文中可使用例如”在...下”、”在...下方”、”下部”、”在…上”、”在…上方”、”上部”及类似术语的空间相对术语。除了附图中所示出的定向之外,所述空间相对术语意欲涵盖组件在使用或操作时的不同定向。设备可被另外定向(旋转90度或在其他定向),而本文所用的空间相对术语相应地作出解释。
图1A至图1G为根据一些实施例所示出的一种整合扇出型封装体的制造方法的剖面图。请参照图1A,提供载板C,其中剥离层(de-bonding layer)DB与介电层DI依序堆叠在载板C上。在一些实施例中,剥离层DB形成在载板C的上表面,且剥离层DB位于载板C以及介电层DI之间。载板C例如是玻璃衬底或类似衬底。另一方面,在一些实施例中,剥离层DB例如是形成在玻璃衬底上的光热转换(light-to-heat conversion;LTHC)离型层或类似膜层。在一些实施例中,介电层DI例如是聚酰亚胺(polyimide;PI)、苯环丁烷(benzocyclobuten;BCB)、聚苯并恶唑(polybenzoxazole;PBO)或是类似材料等聚合物。在一些替代性实施例中,介电层DI可以包括氧化硅(silicon oxide)、氮化硅(silicon nitride)、碳化硅(silicon carbide)、氮氧化硅(silicon oxynitride)或类似材料等无机介电材料。然而,以上所提出的剥离层DB、载板C以及介电层DI的材料仅为例示,而本发明实施例不限于此。
在介电层DI上形成多个预先制造的导电柱102以及多个预先制造的集成电路104。具体来说,集成电路104安装在形成有导电柱102的介电层DI上。另一方面,可以进一步形成晶粒贴合膜(die attach film;DAF;未示出),使其位于集成电路104以及介电层DI之间,以使得集成电路104附着在介电层DI上。集成电路104例如是阵列排列且被导电柱102环绕。集成电路104例如是半导体晶粒。每一集成电路104包括有源表面104a、分散在有源表面104a的多个接垫104b、遮盖有源表面104a的钝化层104c、多个导电柱体104d以及保护层104e。部分的接垫104b被钝化层104c暴露出。导电柱体104d配置在接垫104b上且与接垫104b电性连接。保护层104e覆盖导电柱体104d以及钝化层104c。举例来说,导电柱体104d包括铜柱或是其他合适的金属柱体。在一些实施例中,保护层104e例如是聚苯并恶唑(PBO)层、聚酰亚胺(polyimide)层或是通过其他类似聚合物所形成的膜层。在一些替代性实施例中,保护层104e可以由无机材料所形成。如图1A所示,集成电路104的上表面低于导电柱102的上表面。然而,本发明实施例不限于此。在一些替代性实施例中,集成电路104的上表面与导电柱102的上表面实质上可以为共平面。
请参照图1B,绝缘材料106形成在介电层DI上,以密封导电柱102以及集成电路104。在一些实施例中,绝缘材料106可以是通过复合成型工艺(molding process)所形成的复合成型化合物(molding compound)。绝缘材料106密封导电柱102以及集成电路104的保护层104e。换言之,导电柱102以及集成电路104的保护层104e并不会露出来,而是被绝缘材料106很好的保护住。在一些实施例中,绝缘材料106可以包括环氧树脂(epoxy)或其他合适的材料。
请参照图1C,研磨绝缘材料106以及集成电路104的保护层104e直到暴露出导电柱体104d的上表面为止。在研磨绝缘材料106之后,会在介电层DI上形成绝缘密封体106’。在前述的研磨过程中,部分的保护层104e也会被研磨而形成保护层104e’。在一些实施例中,在前述的绝缘材料106以及保护层104e的研磨过程中,部分的导电柱体104d以及部分的导电柱102会被研磨直到暴露出导电柱体104d的上表面以及导电柱102的上表面为止。换言之,绝缘密封体106’暴露出至少部分的集成电路104以及至少部分的导电柱102。在一些实施例中,绝缘密封体106’例如是通过机械研磨(mechanical grinding)、化学机械研磨(chemical mechanical polishing;CMP)或是其他类似的研磨机制来形成。
绝缘密封体106’密封集成电路104的侧壁,且绝缘密封体106’被导电柱102贯穿。换言之,集成电路104以及导电柱102嵌在绝缘密封体106’中。值得注意的是,尽管集成电路104以及导电柱102嵌在绝缘密封体106’中,但绝缘密封体106’还是暴露出集成电路104与导电柱102的上表面。换句话说,导电柱102的上表面、保护层104e’的上表面以及导电柱体104d的上表面实质上与绝缘密封体106’的上表面为共平面。
请参照图1D,在形成绝缘密封体106’以及保护层104e’之后,在导电柱102的上表面、绝缘密封体106’的上表面、导电柱体104d的上表面以及保护层104e’的上表面上形成与导电柱102以及集成电路104的导电柱体104d电性连接的重配置线路结构108。如图1D所示,重配置线路结构108包括交互堆叠的多个层间介电层(inter-dielectric layer)108a以及多个重配置导电图案108b。重配置导电图案108b与嵌在绝缘密封体106’中的导电柱102以及集成电路104的导电柱体104d电性连接。在一些实施例中,导电柱体104d的上表面以及导电柱102的上表面与重配置线路结构108最底层的重配置导电图案108b接触。另一方面,导电柱体104d的上表面以及导电柱102的上表面被最底层的层间介电层108a部分遮盖。除此之外,最上层的重配置导电图案108b包括多个接垫。在一些实施例中,前述接垫包括用来植球(ball mount)的多个球底金属层(under-ball metallurgy;UBM)图案108b1及/或用来设置无源器件的至少一个连接垫108b2。本发明实施例并不限制球底金属层图案108b1以及连接垫108b2的数目。
以下将详细解说重配置线路结构108的制造方法。图2A至图2H为根据一些实施例所示出的在图1D中的一种重配置线路结构108的制造方法的剖面图。值得注意的是,图2A至图2H所示出的内容仅为示范性的例子。因此,图2A至图2H中所示出的重配置线路结构108的比例、尺寸以及形状可能不会完全地反映出图1D所示出的重配置线路结构108。然而,相同的构件会标示为相同的附图标记,以建立图2A至图2H以及图1D之间的关联性。
请参照图2A,提供衬底SUB,且衬底SUB具有第一区R1以及第二区R2。接着,在衬底SUB上形成层间介电层108a。请同时参照图2A以及图1D,在一些实施例中,由于最底层的层间介电层108a是形成在载板C、剥离层DB、介电层DI、导电柱102、集成电路104以及绝缘密封体106’上,故载板C、剥离层DB、介电层DI、导电柱102、集成电路104以及绝缘密封体106’构成衬底SUB。然而,本发明实施例不限于此。在一些替代性实施例中,当重配置线路结构108在形成集成电路104之前形成时,则衬底SUB可以作为载板。在一些实施例中,多个接触开口108c形成在层间介电层108a中,以使得衬底SUB以及之后形成的导电材料之间能够电性连接。举例来说,如图1D以及图2A所示,接触开口108c可以作为导电柱102、导电柱体104d以及重配置线路结构108之间的导电接触窗。然而,在一些替代性实施例中,接触开口108c并未在此阶段形成。也就是说,在一些替代性实施例中,接触开口108c可以在重配置线路结构108完全形成之后才形成。
请参照图2B,在层间介电层108a上依序形成阻障层210以及种子层220。在一些实施例中,阻障层210以及种子层220共形(conformally)地配置在层间介电层108a上。也就是说,阻障层210以及种子层220延伸进接触开口108c中并覆盖接触开口108c的底面以及侧壁。在一些替代性实施例中,如前述,接触开口108c在此阶段还未形成。在此状况下,阻障层210以及种子层220例如是在层间介电层108a上延伸的平坦膜层。阻障层210例如是包括钛(Titanium;Ti)、氮化钛(Titanium nitride;TiN)、钽(Tantalum;Ta)、氮化钽(Tantalumnitride;TaN)、其他合适的材料或其组合。另一方面,种子层220的材料例如是包括铜、铜合金或其他合适的材料。在一些实施例中,阻障层210以及种子层220例如是通过物理气相沉积(physical vapor deposition;PVD)或是其他适用的方法所形成。阻障层210可以具有0.01微米至1微米的厚度。另一方面,种子层220的厚度可以介于0.01微米至1微米之间。在一些替代性实施例中,可以省略阻障层210。
请参照图2C,在阻障层210以及种子层220上形成掩膜M。掩膜M具有通过图案化工艺所形成的多个开口OP。在一些实施例中,开口OP对应接触开口108c设置。换言之,开口OP所设置的位置会使得其在衬底SUB上的垂直投影(亦即其平面轮廓/轨迹覆盖区域(footprint))分别与对应的其中一个接触开口108c重叠。如前述,阻障层210以及种子层220共形地配置在接触开口108c中。因此,开口OP暴露出至少部分的种子层210。除此之外,位于第一区R1中的两相邻的开口OP之间的距离d1小于位于第二区R2中的两相邻的开口OP之间的距离d2。换言之,第一区R1为对应的开口OP排列较为紧密的高密度区而第二区R2为对应的开口OP排列较为稀疏的低密度区。在一些实施例中,掩膜M例如是由光刻胶(photoresist)或是干膜(dry film)所形成。
请参照图2D,将导电材料230填入掩膜M的开口OP中。在一些实施例中,导电材料230可以通过镀膜工艺所形成。举例来说,镀膜工艺包括电镀(electro-plating)、无电电镀(electroless-plating)、浸镀(immersion plating)或类似的工艺。导电材料230例如是铜、铜合金或其他合适的材料。也就是说,种子层220以及导电材料230包括相同材料。举例来说,种子层220以及导电材料230是通过相同材料所制成。
请参照图2E,接着移除掩膜M以得到多个导电图案230a。如前述,开口OP在第一区R1中排列较为密集而在第二区R2中排列较为稀疏。由于导电图案230a是通过填入开口OP所形成,故导电图案230a也会与开口OP具有相同的配置。也就是说,位于第一区R1中的两相邻的导电图案230a之间的距离d1小于位于第二区R2中的两相邻的导电图案230a之间的距离d2。换言之,在第一区R1内的导电图案230a的图案密度大于在第二区R2内的导电图案230a的图案密度。因此,第一区R1可以被称为密集区而第二区R2可以被称为稀疏区。在一些实施例中,每一导电图案230a具有第一宽度W1。第一宽度W1例如是0.1微米至10微米之间。在一些应用上,导电图案230a可以具有0.6微米的特征宽度(亦即W1)而被定义为细间距(finepitch)图案。
请参照图2F,图案化种子层220以得到多个种子层图案220a。详细来说,通过非等向性蚀刻(anisotropic etching)工艺,选择性地将被导电图案230a暴露出的部分的种子层220移除。在一些实施例中,非等向性蚀刻工艺例如是包括干蚀刻(dry etch)。在干蚀刻中所使用的蚀刻气体包括氩气(Argon;Ar)。具体来说,在移除种子层220的步骤中,蚀刻气体可以包括氩气以及氢气(Hydrogen;H2)。蚀刻气体的流量可以介于10sccm至3000sccm之间。另一方面,在蚀刻的过程中,气体的压强可以介于0.1Pa至100Pa之间。除此之外,氩气与氢气之间的比例(Ar:H2)例如是介于1:100至100:1之间。值得注意的是,在蚀刻的过程中,可能会形成不想要的副产物。然而,除了蚀刻气体外,氢气也可以作为清洁气体以将副产物移除。据此,对于在蚀刻工艺中使用氢气的实施例来说,并不需要执行额外的清洁程序。
值得注意的是,导电图案230a的材料无可避免的会在种子层220的蚀刻过程中被部分移除。具体来说,每一导电图案230a的高度以及第一宽度W1会减少而形成多个剩余导电图案230b。然而,在蚀刻工艺中,剩余导电图案230b的宽度一致性实质上能够被维持。换言之,导电图案230a,230b的宽度在干蚀刻工艺前(导电图案230a)与干蚀刻工艺后(导电图案230b)实质上维持一致在一些实施例中,每一个剩余导电图案230b具有蚀刻后的第二宽度W2。值得注意的是,在种子层220的移除过程中,通过使用本发明实施例的干蚀刻,能够维持在第一区R1内的每一导电图案230a的材料损失实质上等于在第二区R2内的每一导电图案230a的材料损失。也就是说,每一导电图案230a在密集区的材料损失以及稀疏区的材料损失实质上为一致。换言之,通过本发明实施例的干蚀刻,无论图案密度如何,还是能得到图案的材料损失的均匀性。因此,在蚀刻过程中的负载效应(loading effect)能够被减少或甚至被消除。据此,在稀疏区内容易断线等问题能够被缓解,进而确保重配置线路结构108(如图2G所示)内的组件彼此之间电性连接的信赖性。
如前述,在种子层220的蚀刻过程中,每一导电图案230a的第一宽度W1会无可避免的被减少。在一些实施例中,导电图案230a的单侧材料损失例如是0微米至0.05微米之间。换言之,导电图案230a的第一宽度W1以及剩余导电图案230b的第二宽度W2之间的差异可以被维持在0.1微米内。对于许多实际应用来说,这样的材料损失是可以被忽略的。值得注意的是,在本发明实施例的干蚀刻中,导电图案230a的材料损失相较于使用广泛被采用的湿式蚀刻显著的少。因此,重配置导电图案108b的第二宽度W2可以被有效地控制,进而确保具有细间距走线的重配置线路结构108(如图2G所示)的产量以及质量。在一些实施例中,在第一区R1内的导电图案230a的第一宽度W1等于在第二区R2内的导电图案230a的第一宽度W1的状况仅为例示,然本发明实施例并不限于此。换言之,在第一区R1内的导电图案230a的宽度可以与在第二区R2内的导电图案230a的宽度不同。然而,由图案化种子层220所造成在第一区R1内的导电图案230a的材料损失还是会与在第二区R2内的导电图案230a的材料损失实质上相同。
如图2F所示,在移除部分的种子层220后,部分的阻障层210会被剩余导电图案230b以及种子层图案220a所暴露出。请参照图2G,可以通过干蚀刻来移除被暴露出的部分阻障层210,以形成多个阻障层图案210a。移除阻障层210的蚀刻气体例如是包括四氟化碳(Tetrafluoromethane;CF4)以及三氟甲烷(Fluoroform;CHF3)的氟系(fluorine-based)气体、其他合适的气体或其组合。其反应式如下:
Ti+F-→TiFx
其中x为等于1、2等的整数。其中,所形成的TiFx气体会从反应室中被移除。当阻障层210的厚度约为0.1微米时,整个干蚀刻过程可以进行数分钟。
如图2G所示,剩余导电图案230b的侧壁与种子层图案220a的侧壁还有阻障层图案210a的侧壁实质上切齐。通过上述工艺(干蚀刻),剩余导电图案230b的侧壁与种子层图案220a的侧壁还有阻障层图案210a的侧壁实质上对齐。由于在本发明实施例中上层与下层实质上对齐,当与现行采用的湿式蚀刻工艺(常会造成阻障层及/或种子层严重的过度蚀刻,并导致不良的底切轮廓)所形成的蚀刻轮廓比较时,能够得知本发明实施例的干蚀刻工艺会有效地减少或避免阻障层图案210a以及种子层图案220a的底切(undercut)问题。因此,阻障层图案210a以及种子层图案220a之间的连接面积可以增加,进而增强此两膜层之间的附着力。因此,形成在阻障层图案210a上的剩余导电图案230b以及种子层图案220a的剥离问题(peeling issue)能够被解决。剩余导电图案230b、种子层图案220a以及阻障层图案210a构成重配置导电图案108b。
请参照图2H,对重配置导电图案108b执行处理工艺T。处理工艺T例如是等离子处理工艺或是其他合适的工艺。由于阻障层210以及种子层220是通过干蚀刻所移除,在其之后的处理工艺T可以与干蚀刻工艺在同一个反应室中进行。换言之,移除种子层220以及阻障层210的步骤与执行处理工艺T的步骤为原位工艺(in-situ process)。因此,前述步骤可以被视为单一步骤,且能够减少生产时间以及成本。
在一些实施例中,重配置线路结构108为单层结构。因此,在进行如图2A至图2H所示的步骤后,重配置线路结构108实质上已完成。然而,在一些替代性实施例中,重配置线路结构108为多层结构(举例来说,如图1D所示出的重配置线路结构108)。在此状况下,可以重复进行图2A至图2H所示出的步骤,以得到重配置线路结构108。
值得注意的是,图2A至图2H所示出的步骤并不限于制造如图1D所示出的重配置线路结构108。上述步骤也可以用来制造位于封装体内其他位置的重配置线路结构。举例来说,上述步骤可以用在集成电路内的重配置线路结构。在一些替代性实施例中,上述步骤可以用在制造球底金属层及形成在球底金属层上的导电柱(作为与其他封装体电性连接的导电端子)。
请参照图1E,在形成重配置线路结构108之后,将多个导电端子110设置在球底金属层图案108b1上,并将多个无源器件112设置在连接垫108b2上。在一些实施例中,导电端子110可以通过植球工艺或其他合适的工艺设置在球底金属层图案108b1上,而无源器件112可通过焊接工艺(soldering process)、回焊工艺(reflowing process)或其他合适的工艺设置在连接垫108b2上。
请参照图1F,在将导电端子110以及无源器件112设置在重配置线路结构108之后,将形成在绝缘密封体106’的下表面的介电层DI从剥离层DB上剥离,以使介电层DI与载板C分离。也就是说,移除载板C。在一些实施例中,剥离层DB(例如光热转换离型层)可被紫外激光照射而使黏在绝缘密封体106’的下表面的介电层DI从载板C上剥离。如图1F所示,接着图案化介电层DI,以形成暴露出部分导电柱102的多个接触开口O。接触开口O的数量对应于导电柱102的数量。在一些实施例中,介电层DI的接触开口O例如是通过激光钻孔(laserdrilling)工艺、机械钻孔(mechanical drilling)工艺或其他合适的工艺所形成。
请参照图1G,在介电层DI中形成接触开口O后,在接触开口O中配置多个导电端子114。导电端子114与导电柱102电性连接。于此,整合扇出型(Integrated Fan-Out;INFO)封装体阵列已初步完成。如图1G所示,在导电端子110以及导电端子114形成之后,切割整合扇出型封装体阵列以形成具有双面端子设计(dual-side terminal design)的多个整合扇出型封装体10。在一些实施例中,切割工艺或是单一化(singulation)工艺通常包括利用旋转刀片或是激光切割。换言之,切割或单一化工艺例如是激光切割工艺、机械切割工艺或是其他适合的工艺。
图1H为根据一些实施例所示出的一种叠层封装(Package on Package;POP)结构的剖面图。在一些实施例中,整合扇出型封装体10可以与其他的电子组件堆叠。举例来说,请参照图1H,提供另一个封装体20。封装体20例如是集成电路封装体(IC package)。封装体20堆叠在整合扇出型封装体10上且通过导电端子114与整合扇出型封装体10电性连接,以形成叠层封装结构。值得注意的是,图1H仅为示范性说明,而本发明实施例不限于此。在一些替代性实施例中,整合扇出型封装体10可以与其他电子组件堆叠,例如另一个整合扇出型封装体、存储器装置、球栅阵列封装(ball grid array;BGA)或是晶片。此外,堆叠的步骤可以在切割步骤之前执行。举例来说,图1G所示出的整合扇出型封装体阵列可以与晶片堆叠,而单一化工艺可以同时针对扇出型封装体阵列以及晶片执行。
根据本发明的一些实施例,一种重配置线路结构的制造方法至少包括以下步骤。首先,在衬底上形成层间介电层。接着,在层间介电层上形成种子层。然后,在种子层上形成多个导电图案,其中种子层以及导电图案包括相同材料。通过执行干蚀刻工艺选择性地将被导电图案暴露出的种子层移除,以形成多个种子层图案,其中导电图案的宽度在干蚀刻工艺前后实质上维持一致。多个导电图案以及多个种子层图案形成多个重配置导电图案。
根据本发明的一些实施例,干蚀刻的蚀刻气体包括氩气(Argon;Ar)、氢气(Hydrogen;H2)或其组合。
根据本发明的一些实施例,重配置线路结构的制造方法还包括对重配置导电图案执行处理工艺。
根据本发明的一些实施例,移除种子层的步骤与执行处理工艺的步骤为原位工艺(in-situ process)。
根据本发明的一些实施例,重配置线路结构的制造方法还包括在种子层以及层间介电层之间形成阻障层。
根据本发明的一些实施例,重配置线路结构的制造方法还包括移除被导电图案暴露出的阻障层,以形成多个阻障层图案,且重配置导电图案还包括阻障层图案。
根据本发明的一些实施例,种子层以及导电图案包括铜。
根据本发明的一些替代性实施例,一种重配置线路结构的制造方法至少包括以下步骤。首先,在衬底上形成层间介电层,其中衬底具有第一区以及第二区。接着,在层间介电层上形成种子层。然后,在种子层上形成多个导电图案,其中种子层以及导电图案包括相同材料,且在第一区内的导电图案的图案密度大于在第二区内的导电图案的图案密度。通过执行干蚀刻工艺,将被导电图案暴露出的种子层移除,以形成多个种子层图案。在第一区内的每一导电图案的材料损失实质上等于在第二区内的每一导电图案的材料损失。导电图案以及种子层图案形成多个重配置导电图案。
根据本发明的一些替代性实施例,在执行干蚀刻之前与之后,每一导电图案的宽度差异小于0.1微米。
根据本发明的一些替代性实施例,在干蚀刻中所使用的蚀刻气体包括氩气(Argon;Ar)。
根据本发明的一些替代性实施例,蚀刻气体还包括氢气(Hydrogen;H2)。
根据本发明的一些替代性实施例,重配置线路结构的制造方法还包括对重配置导电图案执行处理工艺。
根据本发明的一些替代性实施例,移除种子层的步骤与执行处理工艺的步骤为原位工艺(in-situ process)。
根据本发明的另一些替代性实施例,一种整合扇出型封装体的制造方法至少包括以下步骤。首先,提供具有多个集成电路以及多个导电柱形成在其上的载板。通过绝缘密封体将集成电路以及导电柱密封,且绝缘密封体暴露出至少部分的集成电路以及至少部分的导电柱。接着,在绝缘密封体上形成重配置线路结构以与集成电路以及导电柱电性连接。然后,将载板移除。形成重配置线路结构的方法至少包括以下步骤。首先,在绝缘密封体上形成层间介电层。接着,在层间介电层上依序形成阻障层以及种子层。在种子层上提供具有多个开口的掩膜,且开口暴露出至少部分的种子层。然后,在开口中填入导电材料,以形成多个导电图案,其中种子层以及导电材料包括相同材料。紧接着,移除掩膜。通过执行干蚀刻工艺,将被导电图案暴露出的种子层以及阻障层移除,以形成多个种子层图案以及多个阻障层图案。导电图案、种子层图案以及阻障层图案形成多个重配置导电图案。之后,对重配置导电图案执行处理工艺。
根据本发明的另一些替代性实施例,移除种子层以及阻障层的步骤与执行处理工艺的步骤为原位工艺(in-situ process)。
根据本发明的另一些替代性实施例,在移除种子层的步骤中,蚀刻气体包括氩气(Argon;Ar)。
根据本发明的另一些替代性实施例,蚀刻气体还包括氢气(Hydrogen;H2)。
根据本发明的另一些替代性实施例,在移除阻障层的步骤中,蚀刻气体包括四氟化碳(Tetrafluoromethane;CF4)、三氟甲烷(Fluoroform;CHF3)或其组合。
根据本发明的另一些替代性实施例,整合扇出型封装体的制造方法还包括在重配置线路结构上形成多个导电端子。
根据本发明的另一些替代性实施例,种子层以及导电材料包括铜。
以上概述了数个实施例的特征,使本领域具有通常知识者可更佳了解本揭露的态样。本领域具有通常知识者应理解,其可轻易地使用本发明作为设计或修改其他工艺与结构的依据,以实行本文所介绍的实施例的相同目的及/或达到相同优点。本领域具有通常知识者还应理解,这种等效的配置并不悖离本发明的精神与范畴,且本领域具有通常知识者在不悖离本揭露的精神与范畴的情况下可对本文做出各种改变、置换以及变更。
虽然本发明已以实施例揭示如上,然其并非用以限定本发明,任何所属技术领域中普通技术人员,在不脱离本发明的精神和范围内,当可作些许的改动与润饰,均在本发明范围内。
Claims (40)
1.一种重配置线路结构的制造方法,包括:在衬底上形成层间介电层;
在所述层间介电层上形成种子层;
在所述种子层上形成多个导电图案,其中所述种子层以及所述导电图案包括相同材料;
通过执行干蚀刻工艺选择性地将被所述导电图案暴露出的所述种子层移除,以形成多个种子层图案,其中所述多个导电图案以及所述多个种子层图案形成多个重配置导电图案;以及
对所述重配置导电图案执行等离子处理工艺,其中移除所述种子层的步骤与执行所述等离子处理工艺的步骤为原位工艺。
2.根据权利要求 1 所述的重配置线路结构的制造方法,还包括在所述种子层以及所述层间介电层之间形成阻障层。
3.根据权利要求 2 所述的重配置线路结构的制造方法,还包括移除被所述导电图案暴露出的所述阻障层,以形成多个阻障层图案,其中所述重配置导电图案还包括所述阻障层图案。
4.根据权利要求 1 所述的重配置线路结构的制造方法,其中所述种子层以及所述导电图案包括铜。
5.根据权利要求 1 所述的重配置线路结构的制造方法,其中在执行所
述干蚀刻之前与之后,每一所述导电图案的宽度差异小于 0.1 微米。
6.根据权利要求 1 所述的重配置线路结构的制造方法,其中在所述干蚀刻中所使用的蚀刻气体包括氩气、氢气或其组合。
7.根据权利要求 1 所述的重配置线路结构的制造方法,其中在所述干蚀刻中所使用的蚀刻气体包括氩气。
8.根据权利要求 7 所述的重配置线路结构的制造方法,其中所述蚀刻气体还包括氢气。
9.一种重配置线路结构的制造方法,包括:
在衬底上形成层间介电层,其中所述衬底具有第一区以及第二区;在所述层间介电层上形成种子层;
在所述种子层上形成多个导电图案,其中所述种子层以及所述导电图案包括相同材料,且在所述第一区内的所述导电图案的图案密度大于在所述第二区内的所述导电图案的图案密度;
通过执行干蚀刻工艺将被所述导电图案暴露出的所述种子层移除,以形成多个种子层图案,其中在所述第一区内的每一所述导电图案的材料损失实质上等于在所述第二区内的每一所述导电图案的材料损失,且所述导电图案以及所述种子层图案形成多个重配置导电图案;以及
在执行所述干蚀刻工艺之后,对所述重配置导电图案执行等离子处理工艺,其中移除所述种子层的步骤与执行所述等离子处理工艺的步骤为原位工艺。
10.根据权利要求 9 所述的重配置线路结构的制造方法,其中在执行所
述干蚀刻之前与之后,每一所述导电图案的宽度差异小于 0.1 微米。
11.根据权利要求 9 所述的重配置线路结构的制造方法,其中在所述干蚀刻中所使用的蚀刻气体包括氩气。
12.根据权利要求 11 所述的重配置线路结构的制造方法,其中所述蚀刻气体还包括氢气。
13.根据权利要求 9 所述的重配置线路结构的制造方法,其中在执行所
述干蚀刻之前与之后,每一所述导电图案的单侧宽度差异小于 0.05 微米。
14.一种整合扇出型封装体的制造方法,包括:
提供具有多个集成电路以及多个导电柱形成在其上的载板;
通过绝缘密封体将所述集成电路以及所述导电柱密封,其中所述绝缘密封体暴露出至少部分的所述集成电路以及至少部分的所述导电柱;
在所述绝缘密封体上形成重配置线路结构以与所述集成电路以及所述导电柱电连接,包括:
在所述绝缘密封体上形成层间介电层;
在所述层间介电层上依序形成阻障层以及种子层;
在所述种子层上提供具有多个开口的掩膜,且所述开口暴露出至少部分的所述种子层;
在所述开口中填入导电材料,以形成多个导电图案,其中所述种子层以及所述导电材料包括相同材料;
移除所述掩膜;
通过执行干蚀刻工艺将被所述导电图案暴露出的所述种子层以及所述阻障层移除,以形成多个种子层图案以及多个阻障层图案,其中所述导电图案、所述种子层图案以及所述阻障层图案形成多个重配置导电图案;以及
在部分移除所述种子层以及所述阻障层之后,对所述重配置导电图案执行等离子处理工艺,其中移除所述种子层以及所述阻障层的步骤与执行所述等离子处理工艺的步骤为原位工艺;以及
将所述载板移除。
15.根据权利要求 14 所述的整合扇出型封装体的制造方法,其中在移除所述种子层的步骤中,蚀刻气体包括氩气。
16.根据权利要求 15 所述的整合扇出型封装体的制造方法,其中所述蚀刻气体还包括氢气。
17.根据权利要求 14 所述的整合扇出型封装体的制造方法,其中在移除所述阻障层的步骤中,蚀刻气体包括四氟化碳、三氟甲烷或其组合。
18.根据权利要求 14 所述的整合扇出型封装体的制造方法,还包括在所述重配置线路结构上形成多个导电端子。
19.根据权利要求 14 所述的整合扇出型封装体的制造方法,其中所述种子层以及所述导电材料包括铜。
20.根据权利要求 14 所述的整合扇出型封装体的制造方法,其中在执
行所述干蚀刻之前与之后,每一所述导电图案的宽度差异小于 0.1 微米。
21.一种导电特征的制造方法,包括:形成种子层;
在所述种子层上形成导电图案,其中所述种子层以及所述导电图案包括
相同材料;
通过执行干蚀刻工艺将被所述导电图案暴露出的所述种子层部分移除,以形成种子层图案;以及
对所述种子层图案以及位在其上的所述导电图案执行等离子处理工艺,其中部分移除所述种子层的步骤与执行所述等离子处理工艺的步骤为原位工艺。
22.根据权利要求 21 所述的导电特征的制造方法,其中在所述干蚀刻中所使用的蚀刻气体包括氩气、氢气或其组合。
23.根据权利要求 21 所述的导电特征的制造方法,其中所述种子层以及所述导电图案包括铜。
24.根据权利要求 21 所述的导电特征的制造方法,其中在执行所述干
蚀刻之前与之后,每一所述导电图案的宽度差异小于 0.1 微米。
25.根据权利要求 21 所述的导电特征的制造方法,其中所述种子层图案的侧壁与所述导电图案的侧壁实质上切齐。
26.根据权利要求 21 所述的导电特征的制造方法,还包括在所述种子层下形成阻障层;以及
部分移除被所述导电图案暴露出的阻障层,以形成阻障层图案。
27.根据权利要求 26 所述的导电特征的制造方法,其中部分移除所述阻障层的步骤与执行所述等离子处理工艺的步骤为原位工艺。
28.根据权利要求 26 所述的导电特征的制造方法,其中所述阻障层图案的侧壁与所述种子层图案以及所述导电图案的侧壁实质上切齐。
29.一种导电特征的制造方法,包括:
在种子层上形成多个导电图案,其中所述种子层以及所述导电图案包括相同材料,且在第一区内的所述导电图案之间的距离小于在第二区内的所述导电图案之间的距离;
通过执行干蚀刻工艺将被所述导电图案暴露出的所述种子层移除,以形成多个种子层图案,其中在所述第一区内的每一所述导电图案的移除量实质
上等于在所述第二区内的每一所述导电图案的移除量;以及
在执行所述干蚀刻工艺之后,对所述导电图案以及所述种子层图案执行等离子处理工艺,其中移除所述种子层的步骤与执行所述等离子处理工艺的步骤为原位工艺。
30.根据权利要求 29 所述的导电特征的制造方法,其中在执行所述干
蚀刻之前与之后,每一所述导电图案的宽度差异小于 0.1 微米。
31.根据权利要求 29 所述的导电特征的制造方法,其中在执行所述干
蚀刻之前与之后,每一所述导电图案的单侧宽度差异小于 0.05 微米。
32.根据权利要求 29 所述的导电特征的制造方法,其中在所述干蚀刻中所使用的蚀刻气体包括氩气。
33.根据权利要求 32 所述的导电特征的制造方法,其中所述蚀刻气体还包括氢气。
34.根据权利要求 29 所述的导电特征的制造方法,其中所述第一区为密集区且所述第二区为稀疏区。
35.一种封装体的制造方法,包括:通过绝缘密封体将多个集成电路密封;在所述绝缘密封体上形成层间介电层;
在所述层间介电层上依序形成阻障层以及种子层;在所述种子层上形成多个导电图案;
通过干蚀刻将被所述导电图案暴露出的所述种子层以及所述阻障层移除,以形成多个种子层图案以及多个阻障层图案,其中所述导电图案、所述种子层图案以及所述阻障层图案形成与所述集成电路电连接的多个导电特征;以及
在部分移除所述种子层以及所述阻障层之后,对所述导电特征执行等离子处理工艺,其中移除所述种子层以及所述阻障层的步骤与执行所述等离子处理工艺的步骤在同一个反应室中进行。
36.根据权利要求 35 所述的封装体的制造方法,其中在移除所述种子
层的步骤中蚀刻气体包括氩气。
37.根据权利要求 36 所述的封装体的制造方法,其中所述蚀刻气体还包括氢气。
38.根据权利要求 35 所述的封装体的制造方法,还包括在所述导电特征上形成多个导电端子。
39.根据权利要求 35 所述的封装体的制造方法,其中所述种子层以及所述导电图案包括铜。
40.根据权利要求 35 所述的封装体的制造方法,其中在执行所述干蚀
刻之前与之后,每一所述导电图案的宽度差异小于 0.1 微米。
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US10431549B2 (en) * | 2018-01-10 | 2019-10-01 | Powertech Technology Inc. | Semiconductor package and manufacturing method thereof |
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US11063019B2 (en) * | 2019-07-17 | 2021-07-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure, chip structure and method of fabricating the same |
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US20210118786A1 (en) * | 2019-10-16 | 2021-04-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Conductive structure, semiconductor package and methods of forming the same |
US11145614B2 (en) * | 2019-10-18 | 2021-10-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
US11862594B2 (en) * | 2019-12-18 | 2024-01-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure with solder resist underlayer for warpage control and method of manufacturing the same |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5607879A (en) * | 1995-06-28 | 1997-03-04 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for forming buried plug contacts on semiconductor integrated circuits |
US6849173B1 (en) * | 2002-06-12 | 2005-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Technique to enhance the yield of copper interconnections |
CN1901161A (zh) * | 2005-07-22 | 2007-01-24 | 米辑电子股份有限公司 | 连续电镀制作线路组件的方法及线路组件结构 |
CN101232008A (zh) * | 2007-01-03 | 2008-07-30 | 育霈科技股份有限公司 | 多晶粒封装及其方法 |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6395642B1 (en) * | 1999-12-28 | 2002-05-28 | Taiwan Semiconductor Manufacturing Company | Method to improve copper process integration |
US8759964B2 (en) | 2007-07-17 | 2014-06-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level package structure and fabrication methods |
US7964965B2 (en) * | 2008-03-31 | 2011-06-21 | Intel Corporation | Forming thick metal interconnect structures for integrated circuits |
WO2010096544A1 (en) * | 2009-02-19 | 2010-08-26 | Commscope Inc. Of North Carolina | Patch panel cable information detection systems and methods |
US9048233B2 (en) | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
US20120009777A1 (en) * | 2010-07-07 | 2012-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | UBM Etching Methods |
US8361842B2 (en) | 2010-07-30 | 2013-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Embedded wafer-level bonding approaches |
US9064879B2 (en) | 2010-10-14 | 2015-06-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures using a die attach film |
US8884431B2 (en) | 2011-09-09 | 2014-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods and structures for semiconductor devices |
US8829676B2 (en) | 2011-06-28 | 2014-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for wafer level package |
KR101906860B1 (ko) * | 2011-11-24 | 2018-10-12 | 삼성전자주식회사 | 반도체 소자 및 이를 제조하는 방법 |
US9000584B2 (en) | 2011-12-28 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor device with a molding compound and a method of forming the same |
US8680647B2 (en) | 2011-12-29 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with passive devices and methods of forming the same |
US9111949B2 (en) | 2012-04-09 | 2015-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of wafer level package for heterogeneous integration technology |
US8703542B2 (en) | 2012-05-18 | 2014-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer-level packaging mechanisms |
US9991190B2 (en) | 2012-05-18 | 2018-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging with interposer frame |
US20140374907A1 (en) * | 2012-06-21 | 2014-12-25 | Applied Materials, Inc. | Ultra-thin copper seed layer for electroplating into small features |
US8809996B2 (en) | 2012-06-29 | 2014-08-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with passive devices and method of forming the same |
US9137948B2 (en) * | 2012-07-20 | 2015-09-22 | Cnh Industrial America Llc | System and method for changing a lid height of a harvester |
US10245639B2 (en) * | 2012-07-31 | 2019-04-02 | United Technologies Corporation | Powder metallurgy method for making components |
US8785299B2 (en) | 2012-11-30 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with a fan-out structure and method of forming the same |
US8803306B1 (en) | 2013-01-18 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out package structure and methods for forming the same |
US8778738B1 (en) | 2013-02-19 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor devices and packaging devices and methods |
US9263511B2 (en) | 2013-02-11 | 2016-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package with metal-insulator-metal capacitor and method of manufacturing the same |
US9048222B2 (en) * | 2013-03-06 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating interconnect structure for package-on-package devices |
US9368460B2 (en) | 2013-03-15 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out interconnect structure and method for forming same |
US8877554B2 (en) | 2013-03-15 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices |
US10340143B1 (en) * | 2018-06-12 | 2019-07-02 | Lam Research Corporation | Anodic aluminum oxide as hard mask for plasma etching |
-
2016
- 2016-08-12 US US15/235,109 patent/US10297551B2/en active Active
- 2016-12-09 TW TW105140858A patent/TWI710083B/zh active
- 2016-12-12 CN CN201611137825.3A patent/CN107731786B/zh active Active
-
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- 2019-05-20 US US16/416,294 patent/US10892228B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5607879A (en) * | 1995-06-28 | 1997-03-04 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for forming buried plug contacts on semiconductor integrated circuits |
US6849173B1 (en) * | 2002-06-12 | 2005-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Technique to enhance the yield of copper interconnections |
CN1901161A (zh) * | 2005-07-22 | 2007-01-24 | 米辑电子股份有限公司 | 连续电镀制作线路组件的方法及线路组件结构 |
CN101232008A (zh) * | 2007-01-03 | 2008-07-30 | 育霈科技股份有限公司 | 多晶粒封装及其方法 |
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US10297551B2 (en) | 2019-05-21 |
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US10892228B2 (en) | 2021-01-12 |
US20190273045A1 (en) | 2019-09-05 |
TW201806113A (zh) | 2018-02-16 |
TWI710083B (zh) | 2020-11-11 |
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