TW201806113A - 重配置線路結構的製造方法 - Google Patents

重配置線路結構的製造方法 Download PDF

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TW201806113A
TW201806113A TW105140858A TW105140858A TW201806113A TW 201806113 A TW201806113 A TW 201806113A TW 105140858 A TW105140858 A TW 105140858A TW 105140858 A TW105140858 A TW 105140858A TW 201806113 A TW201806113 A TW 201806113A
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Taiwan
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conductive
layer
seed layer
pattern
conductive pattern
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TW105140858A
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English (en)
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TWI710083B (zh
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蔡惠榕
郭宏瑞
謝昀蓁
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台灣積體電路製造股份有限公司
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Abstract

一種重配置線路結構的製造方法至少包括以下步驟。首先，在基板上形成層間介電層。接著，在層間介電層上形成種子層。然後，在種子層上形成多個導電圖案，且種子層以及導電圖案包括相同材料。藉由執行乾式蝕刻製程選擇性地將被導電圖案暴露出的種子層移除，以形成多個種子層圖案，其中導電圖案的寬度在乾式蝕刻製程前後實質上維持一致。多個導電圖案以及多個種子層圖案形成多個重配置導電圖案。

Description

重配置線路結構的製造方法
本發明實施例是有關於一種重配置線路結構的製造方法，且特別是有關於一種使用乾式蝕刻的重配置線路結構的製造方法。
近年來，由於各種電子元件（例如電晶體、二極體、電阻器、電容器等）的積集度不斷提升，半導體工業因而快速成長。這種積集度的提升是起因於最小特徵尺寸的持續縮小，因而可以將更多的元件整合在一特定的區域中。相較於以前的封裝體，這些較小的電子元件所需要占用的封裝體面積亦較小。一般而言，較小型的半導體元件封裝包括有四面扁平封裝（Quad Flat Packages；QFPs）、接腳柵格陣列（Pin Grid Array；PGA）封裝、球狀柵格陣列（Ball Grid Array；BGA）封裝等等。
目前來說，基於其緊密度，整合扇出型（Integrated Fan-Out；INFO）封裝體日益受到歡迎。整合扇出型封裝體通常具有重配置線路結構，其配置於被模塑的積體電路元件上且用以讀取積體電路元件的訊號。為了達到小尺寸以及高封裝密度的需求，重配置線路結構的製造方法成為本領域中一個重要的議題。
根據本發明的一些實施例，一種重配置線路結構的製造方法至少包括以下步驟。首先，在基板上形成層間介電層。接著，在層間介電層上形成種子層。然後，在種子層上形成多個導電圖案，其中種子層以及導電圖案包括相同材料。藉由執行乾式蝕刻製程選擇性地將被導電圖案暴露出的種子層移除，以形成多個種子層圖案，其中導電圖案的寬度在乾式蝕刻製程前後實質上維持一致。多個導電圖案以及多個種子層圖案形成多個重配置導電圖案。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本揭露在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地作出解釋。
圖1A至圖1G為根據一些實施例所繪示的一種整合扇出型封裝體的製造方法的剖面圖。請參照圖1A，提供載板C，其中剝離層（de-bonding layer）DB與介電層DI依序堆疊於載板C上。在一些實施例中，剝離層DB形成於載板C的上表面，且剝離層DB位於載板C以及介電層DI之間。載板C例如是玻璃基板或類似基板。另一方面，在一些實施例中，剝離層DB例如是形成於玻璃基板上的光熱轉換（light-to-heat conversion；LTHC）離型層或類似膜層。在一些實施例中，介電層DI例如是聚醯亞胺（polyimide；PI）、苯環丁烷（benzocyclobuten；BCB）、聚苯并噁唑（polybenzoxazole；PBO）或是類似材料等聚合物。在一些替代性實施例中，介電層DI可以包括氧化矽（silicon oxide）、氮化矽（silicon nitride）、碳化矽（silicon carbide）、氮氧化矽（silicon oxynitride）或類似材料等無機介電材料。然而，以上所提出的剝離層DB、載板C以及介電層DI的材料僅為例示，而本發明實施例不限於此。
在介電層DI上形成多個預先製造的導電柱102以及多個預先製造的積體電路104。具體來說，積體電路104安裝於形成有導電柱102的介電層DI上。另一方面，可以進一步形成晶粒貼合膜（die attach film；DAF；未繪示），使其位於積體電路104以及介電層DI之間，以使得積體電路104附著於介電層DI上。積體電路104例如是陣列排列且被導電柱102環繞。積體電路104例如是半導體晶粒。每一積體電路104包括主動表面104a、分散於主動表面104a的多個接墊104b、遮蓋主動表面104a的鈍化層104c、多個導電柱體104d以及保護層104e。部分的接墊104b被鈍化層104c暴露出。導電柱體104d配置於接墊104b上且與接墊104b電性連接。保護層104e覆蓋導電柱體104d以及鈍化層104c。舉例來說，導電柱體104d包括銅柱或是其他合適的金屬柱體。在一些實施例中，保護層104e例如是聚苯并噁唑（PBO）層、聚醯亞胺（polyimide）層或是藉由其他類似聚合物所形成的膜層。在一些替代性實施例中，保護層104e可以由無機材料所形成。如圖1A所示，積體電路104的上表面低於導電柱102的上表面。然而，本發明實施例不限於此。在一些替代性實施例中，積體電路104的上表面與導電柱102的上表面實質上可以為共平面。
請參照圖1B，絕緣材料106形成於介電層DI上，以密封導電柱102以及積體電路104。在一些實施例中，絕緣材料106可以是藉由模造成型製程（molding process）所形成的模造成型化合物（molding compound）。絕緣材料106密封導電柱102以及積體電路104的保護層104e。換言之，導電柱102以及積體電路104的保護層104e並不會露出來，而是被絕緣材料106很好的保護住。在一些實施例中，絕緣材料106可以包括環氧樹脂（epoxy）或其他合適的材料。
請參照圖1C，研磨絕緣材料106以及積體電路104的保護層104e直到暴露出導電柱體104d的上表面為止。在研磨絕緣材料106之後，會在介電層DI上形成絕緣密封體106’。在前述的研磨過程中，部分的保護層104e也會被研磨而形成保護層104e’。在一些實施例中，在前述的絕緣材料106以及保護層104e的研磨過程中，部分的導電柱體104d以及部分的導電柱102會被研磨直到暴露出導電柱體104d的上表面以及導電柱102的上表面為止。換言之，絕緣密封體106’暴露出至少部分的積體電路104以及至少部分的導電柱102。在一些實施例中，絕緣密封體106’例如是藉由機械研磨（mechanical grinding）、化學機械研磨（chemical mechanical polishing；CMP）或是其他類似的研磨機制來形成。
絕緣密封體106’密封積體電路104的側壁，且絕緣密封體106’被導電柱102貫穿。換言之，積體電路104以及導電柱102嵌在絕緣密封體106’中。值得注意的是，儘管積體電路104以及導電柱102嵌在絕緣密封體106’中，但絕緣密封體106’還是暴露出積體電路104與導電柱102的上表面。換句話說，導電柱102的上表面、保護層104e’的上表面以及導電柱體104d的上表面實質上與絕緣密封體106’的上表面為共平面。
請參照圖1D，在形成絕緣密封體106’以及保護層104e’之後，在導電柱102的上表面、絕緣密封體106’的上表面、導電柱體104d的上表面以及保護層104e’的上表面上形成與導電柱102以及積體電路104的導電柱體104d電性連接的重配置線路結構108。如圖1D所示，重配置線路結構108包括交互堆疊的多個層間介電層（inter-dielectric layer）108a以及多個重配置導電圖案108b。重配置導電圖案108b與嵌在絕緣密封體106’中的導電柱102以及積體電路104的導電柱體104d電性連接。在一些實施例中，導電柱體104d的上表面以及導電柱102的上表面與重配置線路結構108最底層的重配置導電圖案108b接觸。另一方面，導電柱體104d的上表面以及導電柱102的上表面被最底層的層間介電層108a部分遮蓋。除此之外，最上層的重配置導電圖案108b包括多個接墊。在一些實施例中，前述接墊包括用來植球（ball mount）的多個球底金屬層（under-ball metallurgy；UBM）圖案108b1及/或用來設置被動元件的至少一個連接墊108b2。本發明實施例並不限制球底金屬層圖案108b1以及連接墊108b2的數目。
以下將詳細解說重配置線路結構108的製造方法。圖2A至圖2H為根據一些實施例所繪示的在圖1D中的一種重配置線路結構108的製造方法的剖面圖。值得注意的是，圖2A至圖2H所繪示的內容僅為示範性的例子。因此，圖2A至圖2H中所繪示的重配置線路結構108的比例、尺寸以及形狀可能不會完全地反映出圖1D所繪示的重配置線路結構108。然而，相同的構件會標示為相同的元件符號，以建立圖2A至圖2H以及圖1D之間的關聯性。
請參照圖2A，提供基板SUB，且基板SUB具有第一區R1以及第二區R2。接著，在基板SUB上形成層間介電層108a。請同時參照圖2A以及圖1D，在一些實施例中，由於最底層的層間介電層108a是形成於載板C、剝離層DB、介電層DI、導電柱102、積體電路104以及絕緣密封體106’上，故載板C、剝離層DB、介電層DI、導電柱102、積體電路104以及絕緣密封體106’構成基板SUB。然而，本發明實施例不限於此。在一些替代性實施例中，當重配置線路結構108在形成積體電路104之前形成時，則基板SUB可以作為載板。在一些實施例中，多個接觸開口108c形成於層間介電層108a中，以使得基板SUB以及之後形成的導電材料之間能夠電性連接。舉例來說，如圖1D以及圖2A所示，接觸開口108c可以作為導電柱102、導電柱體104d以及重配置線路結構108之間的導電接觸窗。然而，在一些替代性實施例中，接觸開口108c並未在此階段形成。也就是說，在一些替代性實施例中，接觸開口108c可以在重配置線路結構108完全形成之後才形成。
請參照圖2B，在層間介電層108a上依序形成阻障層210以及種子層220。在一些實施例中，阻障層210以及種子層220共形（conformally）地配置於層間介電層108a上。也就是說，阻障層210以及種子層220延伸進接觸開口108c中並覆蓋接觸開口108c的底面以及側壁。在一些替代性實施例中，如前述，接觸開口108c在此階段還未形成。在此狀況下，阻障層210以及種子層220例如是在層間介電層108a上延伸的平坦膜層。阻障層210例如是包括鈦（Titanium；Ti）、氮化鈦（Titanium nitride；TiN）、鉭（Tantalum；Ta）、氮化鉭（Tantalum nitride；TaN）、其他合適的材料或其組合。另一方面，種子層220的材料例如是包括銅、銅合金或其他合適的材料。在一些實施例中，阻障層210以及種子層220例如是藉由物理氣相沉積（physical vapor deposition；PVD）或是其他適用的方法所形成。阻障層210可以具有0.01微米至1微米的厚度。另一方面，種子層220的厚度可以介於0.01微米至1微米之間。在一些替代性實施例中，可以省略阻障層210。
請參照圖2C，在阻障層210以及種子層220上形成罩幕M。罩幕M具有藉由圖案化製程所形成的多個開口OP。在一些實施例中，開口OP對應接觸開口108c設置。換言之，開口OP所設置的位置會使得其在基板SUB上的垂直投影（亦即其平面輪廓/軌跡覆蓋區域（footprint））分別與對應的其中一個接觸開口108c重疊。如前述，阻障層210以及種子層220共形地配置於接觸開口108c中。因此，開口OP暴露出至少部分的種子層210。除此之外，位於第一區R1中的兩相鄰的開口OP之間的距離d1小於位於第二區R2中的兩相鄰的開口OP之間的距離d2。換言之，第一區R1為對應的開口OP排列較為緊密的高密度區而第二區R2為對應的開口OP排列較為稀疏的低密度區。在一些實施例中，罩幕M例如是由光阻（photoresist）或是乾膜（dry film）所形成。
請參照圖2D，將導電材料230填入罩幕M的開口OP中。在一些實施例中，導電材料230可以藉由鍍膜製程所形成。舉例來說，鍍膜製程包括電鍍（electro-plating）、無電電鍍（electroless-plating）、浸鍍（immersion plating）或類似的製程。導電材料230例如是銅、銅合金或其他合適的材料。也就是說，種子層220以及導電材料230包括相同材料。舉例來說，種子層220以及導電材料230是藉由相同材料所製成。
請參照圖2E，接著移除罩幕M以得到多個導電圖案230a。如前述，開口OP在第一區R1中排列較為密集而在第二區R2中排列較為稀疏。由於導電圖案230a是藉由填入開口OP所形成，故導電圖案230a也會與開口OP具有相同的配置。也就是說，位於第一區R1中的兩相鄰的導電圖案230a之間的距離d1小於位於第二區R2中的兩相鄰的導電圖案230a之間的距離d2。換言之，在第一區R1內的導電圖案230a的圖案密度大於在第二區R2內的導電圖案230a的圖案密度。因此，第一區R1可以被稱為密集區而第二區R2可以被稱為稀疏區。在一些實施例中，每一導電圖案230a具有第一寬度W1。第一寬度W1例如是0.1微米至10微米之間。在一些應用上，導電圖案230a可以具有0.6微米的特徵寬度（亦即W1）而被定義為細間距（fine pitch）圖案。
請參照圖2F，圖案化種子層220以得到多個種子層圖案220a。詳細來說，藉由非等向性蝕刻（anisotropic etching）製程，選擇性地將被導電圖案230a暴露出的部分的種子層220移除。在一些實施例中，非等向性蝕刻製程例如是包括乾式蝕刻（dry etch）。在乾式蝕刻中所使用的蝕刻氣體包括氬氣（Argon；Ar）。具體來說，在移除種子層220的步驟中，蝕刻氣體可以包括氬氣以及氫氣（Hydrogen；H2 ）。蝕刻氣體的流量可以介於10 sccm至3000 sccm之間。另一方面，在蝕刻的過程中，氣體的壓力可以介於0.1 Pa至100 Pa之間。除此之外，氬氣與氫氣之間的比例（Ar:H2 ）例如是介於1:100至100:1之間。值得注意的是，在蝕刻的過程中，可能會形成不想要的副產物。然而，除了蝕刻氣體外，氫氣也可以作為清潔氣體以將副產物移除。據此，對於在蝕刻製程中使用氫氣的實施例來說，並不需要執行額外的清潔程序。
值得注意的是，導電圖案230a的材料無可避免的會在種子層220的蝕刻過程中被部分移除。具體來說，每一導電圖案230a的高度以及第一寬度W1會減少而形成多個剩餘導電圖案230b。然而，在蝕刻製程中，剩餘導電圖案230b的寬度一致性實質上能夠被維持。換言之，導電圖案230a、230b的寬度在乾式蝕刻製程前（導電圖案230a）與乾式蝕刻製程後（導電圖案230b）實質上維持一致。在一些實施例中，每一個剩餘導電圖案230b具有蝕刻後的第二寬度W2。值得注意的是，在種子層220的移除過程中，藉由使用本發明實施例的乾式蝕刻，能夠維持在第一區R1內的每一導電圖案230a的材料損失實質上等於在第二區R2內的每一導電圖案230a的材料損失。也就是說，每一導電圖案230a在密集區的材料損失以及稀疏區的材料損失實質上為一致。換言之，藉由本發明實施例的乾式蝕刻，無論圖案密度如何，還是能得到圖案的材料損失的均勻性。因此，在蝕刻過程中的負載效應（loading effect）能夠被減少或甚至被消除。據此，在稀疏區內容易斷線等問題能夠被緩解，進而確保重配置線路結構108（如圖2G所示）內的元件彼此之間電性連接的信賴性。
如前述，在種子層220的蝕刻過程中，每一導電圖案230a的第一寬度W1會無可避免的被減少。在一些實施例中，導電圖案230a的單側材料損失例如是0微米至0.05微米之間。換言之，導電圖案230a的第一寬度W1以及剩餘導電圖案230b的第二寬度W2之間的差異可以被維持在0.1微米內。對於許多實際應用來說，這樣的材料損失是可以被忽略的。值得注意的是，在本發明實施例的乾式蝕刻中，導電圖案230a的材料損失相較於使用廣泛被採用的濕式蝕刻顯著的少。因此，重配置導電圖案108b的第二寬度W2可以被有效地控制，進而確保具有細間距走線的重配置線路結構108（如圖2G所示）的產量以及品質。在一些實施例中，在第一區R1內的導電圖案230a的第一寬度W1等於在第二區R2內的導電圖案230a的第一寬度W1的狀況僅為例示，然本發明實施例並不限於此。換言之，在第一區R1內的導電圖案230a的寬度可以與在第二區R2內的導電圖案230a的寬度不同。然而，由圖案化種子層220所造成在第一區R1內的導電圖案230a的材料損失還是會與在第二區R2內的導電圖案230a的材料損失實質上相同。
如圖2F所示，在移除部分的種子層220後，部分的阻障層210會被剩餘導電圖案230b以及種子層圖案220a所暴露出。請參照圖2G，可以藉由乾式蝕刻來移除被暴露出的部分阻障層210，以形成多個阻障層圖案210a。移除阻障層210的蝕刻氣體例如是包括四氟化碳（Tetrafluoromethane；CF4 ）以及三氟甲烷（Fluoroform；CHF3 ）的氟系（fluorine-based）氣體、其他合適的氣體或其組合。其反應式如下： Ti+F- → TiFx 其中ｘ為等於1、2等的整數。其中，所形成的TiFx 氣體會從反應室中被移除。當阻障層210的厚度約為0.1微米時，整個乾式蝕刻過程可以進行數分鐘。
如圖2G所示，剩餘導電圖案230b的側壁與種子層圖案220a的側壁還有阻障層圖案210a的側壁實質上切齊。藉由上述製程（乾式蝕刻），剩餘導電圖案230b的側壁與種子層圖案220a的側壁還有阻障層圖案210a的側壁實質上對齊。由於在本發明實施例中上層與下層實質上對齊，當與現行採用的濕式蝕刻製程（常會造成阻障層及/或種子層嚴重的過度蝕刻，並導致不良的底切輪廓）所形成的蝕刻輪廓比較時，能夠得知本發明實施例的乾式蝕刻製程會有效地減少或避免阻障層圖案210a以及種子層圖案220a的底切（undercut）問題。因此，阻障層圖案210a以及種子層圖案220a之間的連接面積可以增加，進而增強此兩膜層之間的附著力。因此，形成於阻障層圖案210a上的剩餘導電圖案230b以及種子層圖案220a的剝離問題（peeling issue）能夠被解決。剩餘導電圖案230b、種子層圖案220a以及阻障層圖案210a構成重配置導電圖案108b。
請參照圖2H，對重配置導電圖案108b執行處理製程T。處理製程T例如是電漿處理製程或是其他合適的製程。由於阻障層210以及種子層220是藉由乾式蝕刻所移除，在其之後的處理製程T可以與乾式蝕刻製程在同一個反應室中進行。換言之，移除種子層220以及阻障層210的步驟與執行處理製程T的步驟為原位製程（in-situ process）。因此，前述步驟可以被視為單一步驟，且能夠減少生產時間以及成本。
在一些實施例中，重配置線路結構108為單層結構。因此，在進行如圖2A至圖2H所示的步驟後，重配置線路結構108實質上已完成。然而，在一些替代性實施例中，重配置線路結構108為多層結構（舉例來說，如圖1D所繪示的重配置線路結構108）。在此狀況下，可以重覆進行圖2A至圖2H所示的步驟，以得到重配置線路結構108。
值得注意的是，圖2A至圖2H所示的步驟並不限於製造如圖1D所繪示的重配置線路結構108。上述步驟也可以用來製造位於封裝體內其他位置的重配置線路結構。舉例來說，上述步驟可以用在積體電路內的重配置線路結構。在一些替代性實施例中，上述步驟可以用在製造球底金屬層及形成在球底金屬層上的導電柱（作為與其他封裝體電性連接的導電端子）。
請參照圖1E，在形成重配置線路結構108之後，將多個導電端子110置於球底金屬層圖案108b1上，並將多個被動元件112設置於連接墊108b2上。在一些實施例中，導電端子110可以藉由植球製程或其他合適的製程設置於球底金屬層圖案108b1上，而被動元件112可藉由焊接製程（soldering process）、迴焊製程（reflowing process）或其他合適的製程設置於連接墊108b2上。
請參照圖1F，在將導電端子110以及被動元件112設置於重配置線路結構108之後，將形成於絕緣密封體106’的下表面的介電層DI從剝離層DB上剝離，以使介電層DI與載板C分離。也就是說，移除載板C。在一些實施例中，剝離層DB（例如光熱轉換離型層）可被紫外光雷射照射而使黏於絕緣密封體106’的下表面的介電層DI從載板C上剝離。如圖1F所示，接著圖案化介電層DI，以形成暴露出部分導電柱102的多個接觸開口O。接觸開口O的數量對應於導電柱102的數量。在一些實施例中，介電層DI的接觸開口O例如是藉由雷射鑽孔（laser drilling）製程、機械鑽孔（mechanical drilling）製程或其他合適的製程所形成。
請參照圖1G，在介電層DI中形成接觸開口O後，在接觸開口O中配置多個導電端子114。導電端子114與導電柱102電性連接。於此，整合扇出型（Integrated Fan-Out；INFO）封裝體陣列已初步完成。如圖1G所示，在導電端子110以及導電端子114形成之後，切割整合扇出型封裝體陣列以形成具有雙面端子設計（dual-side terminal design）的多個整合扇出型封裝體10。在一些實施例中，切割製程或是單一化（singulation）製程通常包括利用旋轉刀片或是雷射光切割。換言之，切割或單一化製程例如是雷射切割製程、機械切割製程或是其他適合的製程。
圖1H為根據一些實施例所繪示的一種疊層封裝（Package on Package；POP）結構的剖面圖。在一些實施例中，整合扇出型封裝體10可以與其他的電子元件堆疊。舉例來說，請參照圖1H，提供另一個封裝體20。封裝體20例如是積體電路封裝體（IC package）。封裝體20堆疊於整合扇出型封裝體10上且藉由導電端子114與整合扇出型封裝體10電性連接，以形成疊層封裝結構。值得注意的是，圖1H僅為示範性說明，而本發明實施例不限於此。在一些替代性實施例中，整合扇出型封裝體10可以與其他電子元件堆疊，例如另一個整合扇出型封裝體、記憶體裝置、球柵陣列封裝（ball grid array；BGA）或是晶圓。此外，堆疊的步驟可以在切割步驟之前執行。舉例來說，圖1G所繪示的整合扇出型封裝體陣列可以與晶圓堆疊，而單一化製程可以同時針對扇出型封裝體陣列以及晶圓執行。
根據本發明的一些實施例，一種重配置線路結構的製造方法至少包括以下步驟。首先，在基板上形成層間介電層。接著，在層間介電層上形成種子層。然後，在種子層上形成多個導電圖案，其中種子層以及導電圖案包括相同材料。藉由執行乾式蝕刻製程選擇性地將被導電圖案暴露出的種子層移除，以形成多個種子層圖案，其中導電圖案的寬度在乾式蝕刻製程前後實質上維持一致。多個導電圖案以及多個種子層圖案形成多個重配置導電圖案。
根據本發明的一些實施例，乾式蝕刻的蝕刻氣體包括氬氣（Argon；Ar）、氫氣（Hydrogen；H2 ）或其組合。
根據本發明的一些實施例，重配置線路結構的製造方法更包括對重配置導電圖案執行處理製程。
根據本發明的一些實施例，移除種子層的步驟與執行處理製程的步驟為原位製程（in-situ process）。
根據本發明的一些實施例，重配置線路結構的製造方法更包括在種子層以及層間介電層之間形成阻障層。
根據本發明的一些實施例，重配置線路結構的製造方法更包括移除被導電圖案暴露出的阻障層，以形成多個阻障層圖案，且重配置導電圖案更包括阻障層圖案。
根據本發明的一些實施例，種子層以及導電圖案包括銅。
根據本發明的一些替代性實施例，一種重配置線路結構的製造方法至少包括以下步驟。首先，在基板上形成層間介電層，其中基板具有第一區以及第二區。接著，在層間介電層上形成種子層。然後，在種子層上形成多個導電圖案，其中種子層以及導電圖案包括相同材料，且在第一區內的導電圖案的圖案密度大於在第二區內的導電圖案的圖案密度。藉由執行乾式蝕刻製程，將被導電圖案暴露出的種子層移除，以形成多個種子層圖案。在第一區內的每一導電圖案的材料損失實質上等於在第二區內的每一導電圖案的材料損失。導電圖案以及種子層圖案形成多個重配置導電圖案。
根據本發明的一些替代性實施例，在執行乾式蝕刻之前與之後，每一導電圖案的寬度差異小於0.1微米。
根據本發明的一些替代性實施例，在乾式蝕刻中所使用的蝕刻氣體包括氬氣（Argon；Ar）。
根據本發明的一些替代性實施例，蝕刻氣體更包括氫氣（Hydrogen；H2 ）。
根據本發明的一些替代性實施例，重配置線路結構的製造方法更包括對重配置導電圖案執行處理製程。
根據本發明的一些替代性實施例，移除種子層的步驟與執行處理製程的步驟為原位製程（in-situ process）。
根據本發明的另一些替代性實施例，一種整合扇出型封裝體的製造方法至少包括以下步驟。首先，提供具有多個積體電路以及多個導電柱形成於其上的載板。藉由絕緣密封體將積體電路以及導電柱密封，且絕緣密封體暴露出至少部分的積體電路以及至少部分的導電柱。接著，在絕緣密封體上形成重配置線路結構以與積體電路以及導電柱電性連接。然後，將載板移除。形成重配置線路結構的方法至少包括以下步驟。首先，在絕緣密封體上形成層間介電層。接著，在層間介電層上依序形成阻障層以及種子層。在種子層上提供具有多個開口的罩幕，且開口暴露出至少部分的種子層。然後，在開口中填入導電材料，以形成多個導電圖案，其中種子層以及導電材料包括相同材料。緊接著，移除罩幕。藉由執行乾式蝕刻製程，將被導電圖案暴露出的種子層以及阻障層移除，以形成多個種子層圖案以及多個阻障層圖案。導電圖案、種子層圖案以及阻障層圖案形成多個重配置導電圖案。之後，對重配置導電圖案執行處理製程。
根據本發明的另一些替代性實施例，移除種子層以及阻障層的步驟與執行處理製程的步驟為原位製程（in-situ process）。
根據本發明的另一些替代性實施例，在移除種子層的步驟中，蝕刻氣體包括氬氣（Argon；Ar）。
根據本發明的另一些替代性實施例，蝕刻氣體更包括氫氣（Hydrogen；H2 ）。
根據本發明的另一些替代性實施例，在移除阻障層的步驟中，蝕刻氣體包括四氟化碳（Tetrafluoromethane；CF4 ）、三氟甲烷（Fluoroform；CHF3 ）或其組合。
根據本發明的另一些替代性實施例，整合扇出型封裝體的製造方法更包括在重配置線路結構上形成多個導電端子。
根據本發明的另一些替代性實施例，種子層以及導電材料包括銅。
以上概述了數個實施例的特徵，使本領域具有通常知識者可更佳了解本揭露的態樣。本領域具有通常知識者應理解，其可輕易地使用本揭露作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本揭露的精神與範疇，且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
10‧‧‧整合扇出型封裝體
20‧‧‧封裝體
102‧‧‧導電柱
104‧‧‧積體電路
104a‧‧‧主動表面
104b‧‧‧接墊
104c‧‧‧鈍化層
104d‧‧‧導電柱體
104e、104e’‧‧‧保護層
106‧‧‧絕緣材料
106’‧‧‧絕緣密封體
108‧‧‧重配置線路結構
108a‧‧‧層間介電層
108b‧‧‧重配置導電圖案
108b1‧‧‧球底金屬層圖案
108b2‧‧‧連接墊
108c、O‧‧‧接觸開口
110‧‧‧導電端子
112‧‧‧被動元件
114‧‧‧導電端子
210‧‧‧阻障層
210a‧‧‧阻障層圖案
220‧‧‧種子層
220a‧‧‧種子層圖案
230‧‧‧導電材料
230a‧‧‧導電圖案
230b‧‧‧剩餘導電圖案
C‧‧‧載板
DI‧‧‧介電層
DB‧‧‧剝離層
M‧‧‧罩幕
OP‧‧‧開口
SUB‧‧‧基板
T‧‧‧處理製程
R1‧‧‧第一區
R2‧‧‧第二區
W1‧‧‧第一寬度
W2‧‧‧第二寬度
d1、d2‧‧‧距離
圖1A至圖1G為根據一些實施例所繪示的一種整合扇出型封裝體的製造方法的剖面圖。 圖1H為根據一些實施例所繪示的一種疊層封裝（Package on Package；POP）結構的剖面圖。 圖2A至圖2H為根據一些實施例所繪示的在圖1D中的一種重配置線路結構的製造方法的剖面圖。
108a‧‧‧層間介電層
108b‧‧‧重配置導電圖案
210a‧‧‧阻障層圖案
220a‧‧‧種子層圖案
230b‧‧‧剩餘導電圖案
SUB‧‧‧基板
R1‧‧‧第一區
R2‧‧‧第二區
W2‧‧‧第二寬度

Claims (1)

  1. 一種重配置線路結構的製造方法，包括： 在基板上形成層間介電層； 在所述層間介電層上形成種子層； 在所述種子層上形成多個導電圖案，其中所述種子層以及所述導電圖案包括相同材料；以及 藉由執行乾式蝕刻製程選擇性地將被所述導電圖案暴露出的所述種子層移除，以形成多個種子層圖案，其中所述導電圖案的寬度在所述乾式蝕刻製程前後實質上維持一致，所述多個導電圖案以及所述多個種子層圖案形成多個重配置導電圖案。
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