TW201801271A - 半導體裝置 - Google Patents

半導體裝置 Download PDF

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Publication number
TW201801271A
TW201801271A TW105134369A TW105134369A TW201801271A TW 201801271 A TW201801271 A TW 201801271A TW 105134369 A TW105134369 A TW 105134369A TW 105134369 A TW105134369 A TW 105134369A TW 201801271 A TW201801271 A TW 201801271A
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Taiwan
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layer
conductive
protective layer
contact opening
dielectric layer
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TW105134369A
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English (en)
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王景德
謝正賢
陳憲偉
許立翰
許子訓
吳偉誠
林彥甫
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台灣積體電路製造股份有限公司
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Publication of TW201801271A publication Critical patent/TW201801271A/zh

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Abstract

一種包括積體電路、保護層及導電通孔的半導體裝置。積體電路包括至少一個導電接墊。保護層覆蓋積體電路。保護層包括接觸開口，且導電接墊被保護層的接觸開口暴露出。導電通孔嵌置在保護層的接觸開口中，且導電通孔藉由接觸開口電性連接至導電接墊。還提供一種製作上述半導體裝置的方法及一種包括上述半導體裝置的整合扇出型封裝體。

Description

半導體裝置
本發明一實施例是有關於一種半導體裝置。
由於各種電子元件（即，電晶體、二極體、電阻器、電容器等）的積集度的持續提高，半導體行業已經歷快速增長。在很大程度上，集成密度的提高來自於最小特徵尺寸的不斷減小，此使得更多較小的元件能夠被整合到特定區域中。與先前的封裝體相比，這些較小的電子元件需要採用體積的封裝體。半導體元件的某些較小類型的封裝體包括方型扁平封裝體（quad flat package，QFP）、引腳柵陣列（pin grid array，PGA）封裝體、球柵陣列（ball grid array，BGA）封裝體等等。
當前，整合扇出型封裝體因其緊湊性(compactness)而逐漸成為主流產品。如何確保整合扇出型封裝體的可靠性是一重要問題。
本發明一實施例提供一種包括積體電路、保護層及導電通孔的半導體裝置。積體電路包括至少一個導電接墊。保護層覆蓋積體電路。保護層包括接觸開口，且導電接墊被保護層的接觸開口暴露出。導電通孔嵌置在保護層的接觸開口中，且導電通孔藉由接觸開口電性連接至導電接墊。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本揭露在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地做出解釋。
圖1至圖7示意性地說明根據本發明某些實施例的製作半導體裝置的製造流程。
參照圖1，提供包括排列成陣列的多個晶片或積體電路100的晶圓W。在對晶圓W進行晶圓切割製程（wafer dicing process）之前，晶圓W中的積體電路100是彼此連接的。在某些實施例中，晶圓W包括半導體基板110、形成在半導體基板110上的多個焊墊120及鈍化層130。鈍化層130形成在半導體基板110之上且包括多個接觸開口132，以使得焊墊120被鈍化層130的接觸開口132局部地暴露出。舉例而言，半導體基板110可為矽基板，所述矽基板包括形成在所述矽基板中的主動元件（例如，電晶體等）及被動元件（例如，電阻器、電容器、電感器等）；焊墊120可為銅焊墊或其他適合的金屬焊墊；且鈍化層130可為氧化矽層、氮化矽層、氮氧化矽層、或由其他適合的介電材料形成的介電層。
參照圖2，在晶圓W的鈍化層130之上形成多個導電圖案140，且藉由鈍化層130的接觸開口132將導電圖案140電性連接至焊墊120。導電圖案140由例如鋁或其他金屬製成。如圖2中所示，導電圖案140中的每一者包括第一端及第二端，導電圖案140的第一端藉由鈍化層130的接觸開口132電性連接至焊墊120，且導電圖案140的第二端可包括導電接墊140a。
在形成包括導電接墊140a的導電圖案140之後，在鈍化層130之上形成保護層150（即，後鈍化層（post-passivation layer））以局部地覆蓋導電圖案140。保護層150包括多個接觸開口152，且導電圖案140的導電接墊140a被保護層150的接觸開口152局部地暴露出。在某些實施例中，保護層150可包括堆疊在鈍化層130上的多個圖案化介電層150a、150b及150c。圖案化介電層150a覆蓋鈍化層130及導電圖案140，圖案化介電層150a包括多個接觸開口152a，且導電圖案140的導電接墊140a被圖案化介電層150a的接觸開口152a局部地暴露出。圖案化介電層150b覆蓋圖案化介電層150a且覆蓋被接觸開口152a局部地暴露出的導電接墊140a。圖案化介電層150b包括多個接觸開口152b，且導電接墊140a被圖案化介電層150b的接觸開口152b局部地暴露出。圖案化介電層150c局部地覆蓋圖案化介電層150b，圖案化介電層150c包括多個接觸開口152c，且圖案化介電層150c的接觸開口152c位於圖案化介電層150b的接觸開口152b上方。
圖案化介電層150a可例如為氧化矽層、氮化矽層、氮氧化矽層、或由其他適合的無機介電材料形成的介電層。例如，圖案化介電層150b可為聚醯亞胺（polyimide，PI）層、聚苯並惡唑（polybenzoxazole，PBO）層、或其他適合的聚合物（或有機）層，且圖案化介電層150c可為聚醯亞胺（PI）層、聚苯並惡唑（PBO）層、或其他適合的聚合物（或有機）層。圖案化介電層150b及圖案化介電層150c可由相同的材料或不同的材料製成。在製作聚合物層期間，需要在所述聚合物層的圖案化製程之後進行固化製程（curing process）。
如圖2中所示，接觸開口152b的尺寸（例如，直徑）例如小於接觸開口152a的尺寸（例如，直徑），且接觸開口152c的尺寸（例如，直徑）例如大於接觸開口152b的尺寸（例如，直徑）。在某些實施例中，接觸開口152a的尺寸（例如，直徑）可實質上等於接觸開口152c的尺寸（例如，直徑）。由於接觸開口152b的尺寸小於接觸開口152a的尺寸，因此圖案化介電層150a被圖案化介電層150b完全覆蓋，且保護層150的接觸開口152由接觸開口152b及接觸開口152c構成。值得注意的是，闡述接觸開口152a、152b及152c的尺寸僅是為了說明，本發明並不僅限於此。
如圖2中所示，堆疊的圖案化介電層150a、150b及150c可為無機介電層、有機介電層或其組合。保護層150內的圖案化介電層的數目在本發明中不受限制。在某些實施例中，可在鈍化層130上形成無機介電層，且可形成有機介電層來覆蓋所述無機介電層。在某些替代實施例中，可在鈍化層130上形成無機介電層，且可在所述無機介電層之上形成及堆疊多個有機介電層。
參照圖3，在形成包括接觸開口152的保護層150（即，後鈍化層）之後，將阻障層B濺鍍至被接觸開口152暴露出的保護層150及導電接墊140a上。阻障層B共形地或順應地覆蓋被接觸開口152暴露出的保護層150的表面及導電接墊140a。在某些實施例中，阻障層B可為藉由濺鍍製程（sputtering process）形成的導電層（例如，Ti/Cu層）。
參照圖4，在阻障層B上形成包括多個開口OP的圖案化光阻層PR。圖案化光阻層PR的開口OP對應於保護層150的接觸開口152。換句話說，圖案化光阻層PR的開口OP位於保護層150的接觸開口152上方。阻障層B被圖案化光阻層PR的開口OP局部地暴露出。圖案化光阻層PR被形成以定義導電通孔或導電柱（圖4中未示出）的形成位置。
在某些實施例中，為了方便製作依序形成的導電通孔或導電柱（圖4中未示出），開口OP的尺寸（例如，直徑）例如大於接觸開口152的尺寸（例如，直徑）。然而，開口OP的尺寸僅是為了說明，本發明並不僅限於此。
參照圖5，進行電鍍製程（plating process）。在電鍍製程期間，阻障層B的功能為電鍍製程中的種子層（seed layer），且將多個柱部P電鍍至阻障層B上。在接觸開口152及開口OP中電鍍形成柱部P。柱部P例如為銅柱或其他適合的金屬柱。在某些實施例中，可藉由上述電鍍製程在柱部P的頂表面上可選擇性地形成多個帽部CA。在某些實施例中，帽部CA為焊料帽（solder cap）或其他適合的合金帽（alloy cap）。
當帽部CA的材料與柱部P的材料不同時，可在後續熱處理期間形成金屬間化合物（intermetallic compound）。如圖5中所示，柱部P不直接接觸保護層150。換句話說，柱部P與保護層150被阻障層B間隔開。因此，阻障層B能夠阻擋金屬間化合物擴散至保護層150的表面上，且保護層150與導電通孔160之間的黏著不會因所述金屬間化合物而劣化。
在進行所述電鍍製程之後，移除圖案化光阻層PR，且局部地暴露出阻障層B。此外，導電通孔160的頂表面的水準高度高於保護層150的頂表面的水準高度。
參照圖5及圖6，使用柱部P作為硬罩幕，藉由刻蝕製程（etching process）來移除阻障層B的未被柱部P覆蓋的部分直至暴露出保護層150為止。在對阻障層B進行圖案化之後，在柱部P之下形成多個阻障襯層BL。阻障襯層BL與柱部P會自對準(self-aligned)。
如圖6中所示，在形成阻障襯層BL之後，多個導電通孔160便已完成。導電通孔160中的每一者包括阻障襯層BL及柱部P。阻障襯層BL配置於接觸開口152中，且阻障襯層BL覆蓋導電接墊140a的被接觸開口152暴露出的表面。柱部P嵌置在接觸開口152中，且阻障襯層BL位於柱部P與保護層150之間。此外，柱部P與保護層150被阻障襯層BL間隔開。
在形成導電通孔160之後，可選擇性地對晶圓W的背面進行背面研磨製程（back side grinding process）。在晶圓W的背面研磨製程期間，半導體基板110被研磨以降低晶圓W的厚度。
由於保護層150（示出於圖2中）是在製作導電通孔160（示出於圖6中）之前形成，因此保護層150與導電通孔160之間的黏著性可不受保護層150中的聚合物層的熱處理（即，固化製程）影響，也因此，所述半導體裝置的可靠性得到強化。
參照圖7，對晶圓W進行晶圓切割製程以製作出多個半導體裝置SE。半導體裝置SE中的每一者包括積體電路100a、保護層150’及至少一個導電通孔160，積體電路100a包括形成在積體電路100a上的至少一個導電接墊140a。保護層150’覆蓋積體電路100a，保護層150’包括至少一個接觸開口152，且導電接墊140a被保護層150’的接觸開口152暴露出。所述至少一個導電通孔160嵌置在保護層150’的接觸開口152中，且所述至少一個導電通孔160藉由接觸開口152電性連接至導電接墊140a。如圖7中所示，繪示出兩個導電接墊140a、兩個接觸開口152及兩個導電通孔160是用於說明，然而本發明並不僅限於此。
如圖7中所示，保護層150’可包括堆疊在鈍化層130上的多個圖案化介電層150a’、150b’及150c’。圖案化介電層150a’覆蓋鈍化層130a及導電圖案140，圖案化介電層150a’包括多個接觸開口152a’，且導電圖案140的導電接墊140a被圖案化介電層150a’的接觸開口152a’局部地暴露出。圖案化介電層150b’覆蓋圖案化介電層150a’且覆蓋被接觸開口152a’局部地暴露出的導電接墊140a，圖案化介電層150b’包括多個接觸開口152b’，且導電接墊140a被圖案化介電層150b’的接觸開口152b’局部地暴露出。圖案化介電層150c’局部地覆蓋圖案化介電層150b’，圖案化介電層150c’包括多個接觸開口152c’，且圖案化介電層150c’的接觸開口152c’位於圖案化介電層150b’的接觸開口152b’上方。
在某些實施例中，導電通孔160的頂表面的水準高度高於保護層150’的頂表面的水準高度。
在某些實施例中，積體電路100a可包括半導體基板110a、形成在半導體基板110a上的焊墊120、鈍化層130a及導電圖案140。如圖6及圖7中所示，半導體基板110a、鈍化層130a及保護層150’的材料及特性均相同於半導體基板110、鈍化層130及保護層150。因此，不再對半導體基板110a、鈍化層130a及保護層150’予以詳細說明。
圖8至圖15示意性地說明根據本發明某些實施例的製作整合扇出型封裝體的製造流程。
參照圖8，提供上面形成有剝離層DB及介電層DI的載板C，其中剝離層DB位於載板C與介電層DI之間。在某些實施例中，例如，載板C是玻璃基板，剝離層DB是形成在所述玻璃基板上的光-熱轉換（light-to-heat conversion，LTHC）釋放層，且介電層DI是形成在剝離層DB上的聚苯並惡唑（PBO）層。在提供所述上面形成有剝離層DB及介電層DI的載板C之後，在介電層DI上形成多個貫穿絕緣體的導電通孔TIV。在某些實施例中，所述多個貫穿絕緣體的導電通孔TIV是藉由光阻層塗布（photoresist coating）、微影（photolithography）、電鍍及光阻層剝除製程（photoresist stripping process）形成。例如，貫穿絕緣體的導電通孔TIV包括銅杆或其他適合的金屬杆。
如圖8中所示，在某些實施例中，拾取上面分佈有導電通孔160的半導體裝置SE中的一者並放置在介電層DI上。藉由晶片貼合膜（die attachment film，DAF）、黏著膏（adhesion paste）等將半導體裝置SE貼合或黏著在介電層DI上。在某些替代實施例中，拾取多於一個半導體裝置SE並放置在介電層DI上，其中可將放置在介電層DI上的半導體裝置SE排列成陣列。當放置在介電層DI上的半導體裝置SE被排列成陣列時，貫穿絕緣體的導電通孔TIV可被分成多個組，且半導體裝置SE的數目對應於貫穿絕緣體的導電通孔TIV的所述組的數目。
如圖8中所示，在形成貫穿絕緣體的導電通孔TIV之後，拾取半導體裝置SE並放置在介電層DI上。然而，本發明並不僅限於此。在某些替代實施例中，可在形成貫穿絕緣體的導電通孔TIV之前拾取半導體裝置SE並放置在介電層DI上。
參照圖9，在介電層DI上形成絕緣材料210，以覆蓋半導體裝置SE及貫穿絕緣體的導電通孔TIV。在某些實施例中，絕緣材料210是由鑄模製程（molding process）形成的封裝膠體（molding compound）。半導體裝置SE的導電通孔160及保護層150’被絕緣材料210覆蓋。換句話說，半導體裝置SE的導電通孔160及保護層150’不會顯露出且被絕緣材料210很好地保護。在某些實施例中，絕緣材料210包括環氧樹脂或其他適合的介電材料。
參照圖10，接著對絕緣材料210進行研磨直至暴露出導電通孔160的頂表面及保護層150’的頂表面為止。在某些實施例中，絕緣層210是藉由機械研磨製程（mechanical grinding process）及/或化學機械研磨（chemical mechanical polishing，CMP）製程進行研磨。在絕緣材料210被研磨之後，在介電層DI之上形成絕緣封裝體210’。在絕緣材料210的研磨製程期間，導電通孔160a的位於接觸開口152外的部分受到研磨，進而使得在接觸開口152中形成多個導電通孔160a。在某些實施例中，在絕緣材料210的研磨製程期間，貫穿絕緣體的導電通孔TIV的部分也受到研磨。
如圖10中所示，絕緣封裝體210’會包覆住半導體裝置SE的側壁，且絕緣封裝體210’被貫穿絕緣體的導電通孔TIV穿透。換句話說，半導體裝置SE及貫穿絕緣體的導電通孔TIV嵌置在絕緣封裝體210’中。值得注意的是，貫穿絕緣體的導電通孔TIV的頂表面、絕緣封裝體210’的頂表面及導電通孔160a的頂表面與保護層150’的頂表面實質上共面。
參照圖11，在形成絕緣封裝體210’及保護層150’之後，在貫穿絕緣體的導電通孔TIV的頂表面上、絕緣封裝體210’的頂表面上、導電通孔160a的頂表面上及保護層150’的頂表面上形成與半導體裝置SE的導電通孔160a電性連接的重佈線路結構220。以下將搭配圖11針對重佈線路結構220進行詳細的描述。
參照圖11，重佈線路結構220包括交替地堆疊的多個層間介電層（inter-dielectric layer）222及多個重佈線導電層224，且重佈線導電層224電性連接至半導體裝置SE的導電通孔160a及嵌置在絕緣封裝體210’中的貫穿絕緣體的導電通孔TIV。在某些實施例中，導電通孔160a的頂表面及貫穿絕緣體的導電通孔TIV的頂表面會與重佈線路結構220接觸。導電通孔160a的頂表面及貫穿絕緣體的導電通孔TIV的頂表面被最底部的層間介電層222局部地覆蓋。
如圖12中所示，在形成重佈線路結構220之後，接著在重佈線路結構220的最頂部的重佈線導電層224上形成多個焊墊230。焊墊230包括用於植球的多個球下金屬（under-ball metallurgy，UBM）圖案230a及用於安裝被動元件的多個連接墊230b。焊墊230電性連接至重佈線路結構220的最頂部的重佈線導電層224。換句話說，焊墊230藉由重佈線路結構220電性連接至半導體裝置SE的導電通孔160a及貫穿絕緣體的導電通孔TIV。值得注意的是，球下金屬圖案230a的數目及連接墊230b的數目在本發明中不受限制。
參照圖13，在形成球下金屬圖案230a及連接墊230b之後，在球下金屬圖案230a上放置多個導電球240，且在連接墊230b上安裝多個被動元件250。在某些實施例中，可藉由植球製程（ball placement process）在球下金屬圖案230a上放置導電球240，且可藉由焊接製程（solder process）或回焊製程（reflow process）在連接墊230b上安裝被動元件250。在某些實施例中，導電球240的高度例如大於被動元件250的高度。
參照圖13及圖14，在焊墊230上安裝導電球240及被動元件250之後，令形成在絕緣封裝體210’的底表面上的介電層DI自剝離層DB分層，進而使得介電層DI從載板C分離。在某些實施例中，可藉由紫外線（UV）雷射來照射剝離層DB（例如，所述LTHC釋放層），進而使得介電層DI從載板C剝離。
如圖14中所示，接著對介電層DI進行圖案化以形成多個接觸開口O，且這些接觸開口O暴露出貫穿絕緣體的導電通孔TIV的底表面。接觸開口O的數目及位置對應於貫穿絕緣體的導電通孔TIV的數目。在某些實施例中，藉由雷射鑽孔製程或其他適合的圖案化製程來形成介電層DI的接觸開口O。
參照圖15，在介電層DI中形成接觸開口O之後，在貫穿絕緣體的導電通孔TIV的被接觸開口O暴露出的底表面上放置多個導電球260。並且，導電球260可例如被回焊而與貫穿絕緣體的導電通孔TIV的底表面接合。如圖15中所示，在形成導電球240及導電球260之後，具有雙側的端子設計（即，導電球240及260）的積體電路100的整合扇出型封裝體便已完成。
圖16是說明根據本發明某些實施例的疊層封裝（POP）結構的剖視圖。參照圖16，接著提供另一封裝體300。在某些實施例中，封裝體300是例如記憶體裝置或其他適合的半導體裝置。封裝體300藉由導電球260堆疊在圖15中所示的整合扇出型封裝體之上且電性連接至所述整合扇出型封裝體，從而製作出疊層封裝（POP）結構。
由於保護層150是在形成導電通孔160之前形成，因此導電通孔160與保護層150之間的黏著性良好，且在導電通孔160與保護層150之間的介面處不易發生層離（delamination）。
根據某些實施例，提供一種包括積體電路、保護層及導電通孔的半導體裝置。所述積體電路包括至少一個導電接墊。所述保護層覆蓋所述積體電路。所述保護層包括接觸開口，且所述導電接墊被所述保護層的接觸開口暴露出。所述導電通孔嵌置在所述保護層的接觸開口中，且所述導電通孔藉由所述接觸開口電性連接至所述導電接墊。
在所述的半導體裝置中，所述保護層包括堆疊在所述積體電路之上的多個圖案化介電層。
在所述的半導體裝置中，所述保護層包括：無機介電層，覆蓋所述積體電路；以及有機介電層，覆蓋所述無機介電層。
在所述的半導體裝置中，所述保護層包括：無機介電層，覆蓋所述積體電路；以及多個有機介電層，堆疊在所述無機介電層之上。
在所述的半導體裝置中，所述導電通孔包括：阻障襯層，配置於所述接觸開口中，且所述阻障襯層覆蓋所述導電接墊的被所述接觸開口暴露出的表面；以及柱部，嵌置在所述接觸開口中，其中所述阻障襯層位於所述柱部與所述保護層之間。
在所述的半導體裝置中，所述柱部不直接接觸所述保護層。
在所述的半導體裝置中，所述柱部與所述保護層藉由所述阻障襯層間隔開。
在所述的半導體裝置中，所述導電通孔的頂表面的水準高度高於所述保護層的頂表面的水準高度。
根據某些替代實施例，提供一種包括半導體裝置、絕緣封裝體及重佈線路結構的整合扇出型封裝體。所述半導體裝置包括積體電路、保護層及導電通孔。所述積體電路包括至少一個導電接墊。所述保護層覆蓋所述積體電路。所述保護層包括接觸開口，且所述導電接墊被所述保護層的所述接觸開口暴露出。所述導電通孔嵌置在所述保護層的所述接觸開口中，且所述導電通孔藉由所述接觸開口電性連接至所述導電接墊。所述絕緣封裝體封裝所述半導體裝置。所述重佈線路結構配置在所述半導體裝置及所述絕緣封裝體上，且所述重佈線路結構電性連接至所述半導體裝置的導電通孔。
在所述的整合扇出型封裝體中，所述保護層包括堆疊在所述積體電路之上的多個圖案化介電層。
在所述的整合扇出型封裝體中，所述保護層包括：無機介電層，覆蓋所述積體電路；以及有機介電層，覆蓋所述無機介電層。
在所述的整合扇出型封裝體中，所述保護層包括：無機介電層，覆蓋所述積體電路；以及多個有機介電層，堆疊在所述無機介電層之上。
在所述的整合扇出型封裝體中，所述導電通孔包括：阻障襯層，配置於所述接觸開口中，且所述阻障襯層覆蓋所述導電接墊的被所述接觸開口暴露出的表面；以及柱部，嵌置在所述接觸開口中，其中所述阻障襯層位於所述柱部與所述保護層之間。
在所述的整合扇出型封裝體中，所述柱部不直接接觸所述保護層。
在所述的整合扇出型封裝體中，所述柱部與所述保護層藉由所述阻障襯層間隔開。
在所述的整合扇出型封裝體中，所述導電通孔的頂表面與所述保護層的頂表面實質上共面。
根據某些替代實施例，提供一種包括以下步驟的半導體裝置的製作方法。提供包括至少一個導電接墊的積體電路。在所述積體電路上形成保護層，其中所述保護層包括接觸開口，且所述導電接墊被所述保護層的所述接觸開口暴露出。在形成所述保護層之後形成導電通孔，其中所述導電通孔嵌置在所述保護層的所述接觸開口中，且所述導電通孔藉由所述接觸開口電性連接至所述導電接墊。
在所述的半導體裝置的製作方法中，形成所述保護層的方法包括：形成堆疊在所述積體電路之上的多個圖案化介電層。
在所述的半導體裝置的製作方法中，形成所述導電通孔的方法包括：在所述保護層及被所述接觸開口暴露出的所述導電接墊上形成阻障層；在所述阻障層上形成柱部，所述阻障層被所述柱部局部地覆蓋，且所述柱部嵌置在所述接觸開口中；以及將所述阻障層圖案化，以在所述柱部與所述保護層之間形成阻障襯層。
在所述的半導體裝置的製作方法中，所述柱部與所述保護層藉由所述阻障襯層間隔開。
以上概述了數個實施例的特徵，使本領域具有通常知識者可更佳瞭解本揭露的態樣。本領域具有通常知識者應理解，其可輕易地使用本揭露作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本揭露的精神與範疇，且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
100、100a‧‧‧積體電路
110、110a‧‧‧半導體基板
120‧‧‧焊墊
130、130a‧‧‧鈍化層
132‧‧‧接觸開口
140‧‧‧導電圖案
140a‧‧‧導電接墊
150、150’‧‧‧保護層
150a、150a’、150b、150b’、150c、150c’‧‧‧圖案化介電層
152、152a、152a’、152b、152b’、152c、152c’‧‧‧接觸開口
160‧‧‧導通孔
210‧‧‧絕緣材料
210’‧‧‧絕緣封裝體
220‧‧‧重佈線路結構
222‧‧‧層間介電層
224‧‧‧重佈線導電層
230‧‧‧焊墊
230a‧‧‧球下金屬圖案
230b‧‧‧連接墊
240‧‧‧導電球
250‧‧‧被動元件
260‧‧‧導電球
300‧‧‧封裝體
B‧‧‧阻障層
BL‧‧‧阻障襯層
C‧‧‧載板
CA‧‧‧帽部
DB‧‧‧剝離層層
DI‧‧‧介電層
O‧‧‧接觸開口
OP‧‧‧開口
P‧‧‧柱部
PR‧‧‧圖案化光阻層
SE‧‧‧半導體裝置
TIV‧‧‧貫穿絕緣體的導通孔
W‧‧‧晶圓
圖1至圖7示意性地說明根據本發明某些實施例的製作半導體裝置的製造流程。 圖8至圖15示意性地說明根據本發明某些實施例的製作整合扇出型封裝體的製造流程。 圖16是說明根據本發明某些實施例的疊層封裝（package-on-package，POP）結構的剖視圖。
110‧‧‧半導體基板
120‧‧‧焊墊
130‧‧‧鈍化層
132、152‧‧‧接觸開口
140a‧‧‧導電接墊
150‧‧‧保護層
B‧‧‧阻障層
CA‧‧‧帽部
P‧‧‧柱部
W‧‧‧晶圓

Claims (1)

  1. 一種半導體裝置，其特徵在於，包括： 積體電路，包括至少一個導電接墊； 保護層，覆蓋所述積體電路，所述保護層包括接觸開口，且所述導電接墊被所述保護層的所述接觸開口暴露出；以及 導電通孔，嵌置在所述保護層的所述接觸開口中，且所述導電通孔藉由所述接觸開口電性連接至所述導電接墊。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10002852B1 (en) * 2016-12-15 2018-06-19 Dyi-chung Hu Package on package configuration
US10283473B1 (en) * 2017-11-03 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof
US10658287B2 (en) * 2018-05-30 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a tapered protruding pillar portion
CN110556299B (zh) * 2018-06-04 2021-11-16 中芯国际集成电路制造（天津）有限公司 一种半导体结构及其形成方法
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
US10923421B2 (en) * 2019-04-23 2021-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10833053B1 (en) * 2019-07-17 2020-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
TWI822833B (zh) * 2019-08-15 2023-11-21 優顯科技股份有限公司 電子探測板、光電探測模組、與電子探測方法
KR20210152721A (ko) * 2020-06-09 2021-12-16 삼성전자주식회사 반도체 패키지

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US20100007017A1 (en) * 2008-07-14 2010-01-14 Advanced Chip Engineering Technology Inc. Inter-connecting structure for semiconductor package and method for the same
US9177926B2 (en) * 2011-12-30 2015-11-03 Deca Technologies Inc Semiconductor device and method comprising thickened redistribution layers
KR20110124993A (ko) * 2010-05-12 2011-11-18 삼성전자주식회사 반도체 칩 및 이를 포함하는 반도체 패키지 및 반도체 칩의 제조 방법
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9520371B2 (en) * 2014-10-27 2016-12-13 Globalfoundries Singapore Pte. Ltd. Planar passivation for pads
US9818711B2 (en) * 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and methods thereof

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