CN109786274A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN109786274A
CN109786274A CN201810789446.5A CN201810789446A CN109786274A CN 109786274 A CN109786274 A CN 109786274A CN 201810789446 A CN201810789446 A CN 201810789446A CN 109786274 A CN109786274 A CN 109786274A
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China
Prior art keywords
seed layer
layer
laying
semiconductor devices
hole
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CN201810789446.5A
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CN109786274B (zh
Inventor
邹贤儒
吴志伟
林俊成
王卜
卢思维
施应庆
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

为了减少或消除通孔的分层，将集成扇出叠层封装结构与去湿结构一起使用。在实施例中，去湿结构是通过施加第一晶种层和第二晶种层形成的钛环，以帮助制造通孔。然后将第一晶种层图案化成环结构，该环结构也暴露第一晶种层的至少部分。本发明的实施例还涉及半导体器件及其制造方法。

Description

半导体器件及其制造方法
技术领域
本发明的实施例涉及半导体器件及其制造方法。
背景技术
由于各个电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成度的持续改进，半导体工业经历了快速增长。对于大部分而言，这种集成密度的改进来自于最小部件尺寸的连续减小(例如，朝向亚20nm节点缩小半导体工艺节点)，这允许更多的组件集成到给定区域中。随着近来对小型化、更高速度和更大带宽以及更低功耗和延迟的需求的增长，对于半导体管芯的更小且更具创造性的封装技术的需求也已增长。
随着半导体技术的进一步发展，堆叠和接合的半导体器件作为有效替代物出现从而进一步减小半导体器件的物理尺寸。在堆叠式半导体器件中，至少部分地在单独的衬底上制造有源电路(诸如逻辑、存储器、处理器电路等)，和然后将这些有源电路物理和电接合在一起以形成功能器件。这样的接合工艺利用复杂的技术，并且期望改进。
发明内容
本发明的实施例提供了一种制造半导体器件的方法，所述方法包括：在衬底上方沉积第一衬垫层；沉积与所述第一衬垫层物理接触的第一晶种层；将通孔镀在所述第一晶种层上；使用所述通孔作为掩模去除所述第一衬垫层和所述第一晶种层的部分；用密封剂密封所述通孔以及半导体管芯；以及在密封所述通孔之后，图案化所述第一衬垫层以暴露所述第一晶种层的内部而不暴露所述第一晶种层的外部。
本发明的另一实施例提供了一种制造半导体器件的方法，所述方法包括：将密封剂放置在聚合物层上方，所述密封剂密封半导体器件和多个通孔，所述多个通孔中的每个通孔均与所述半导体器件横向分隔开；图案化所述聚合物层以暴露所述多个通孔中的一个通孔的第一衬垫层；将所述第一衬垫层图案化成环结构，其中，使用所述聚合物层作为掩模来实施图案化所述第一衬垫层，并且其中，图案化所述第一衬垫层暴露第一晶种层的部分；以及将导电材料放置为穿过所述第一衬垫层与所述第一晶种层物理接触。
本发明的又一实施例提供了一种半导体器件，包括：密封剂，密封半导体器件；第一通孔，从所述密封剂的第一侧延伸至所述密封剂的第二侧，所述第一通孔包括：第一衬垫层；第一晶种层，与所述第一衬垫层物理接触，所述第一晶种层与所述第一衬垫层不同；以及导电材料，在所述第一晶种层的与所述第一衬垫层相对的侧上与所述第一晶种层物理接触，其中，所述第一衬垫层是环形。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据一些实施例的通孔的形成。
图2示出了根据一些实施例的半导体管芯。
图3示出了根据一些实施例的在通孔之间的半导体管芯的放置。
图4示出了根据一些实施例的参考通孔、通孔和半导体管芯的密封。
图5示出了根据一些实施例的再分布层的形成。
图6A至图6B示出了根据一些实施例的载体的去除。
图7示出了根据一些实施例的聚合物层的图案化。
图8A至图8B示出了根据一些实施例的第一晶种层的图案化。
图9示出了根据一些实施例的外部连接件的放置。
图10示出了根据一些实施例的第一封装件和第二封装件的接合。
图11示出了根据一些实施例的分割工艺。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
现在参照图1，其中，示出了第一载体衬底101和位于第一载体衬底101上方的粘合层103、聚合物层105、第一晶种层107(或第一衬垫层)和第二晶种层109(或第二衬垫层)。例如，第一载体衬底101包括诸如玻璃或氧化硅的硅基材料或诸如氧化铝的其它材料、这些材料的任何组合等。第一载体衬底101是平坦的以适合于诸如第一半导体器件201和第二半导体器件301(未在图1中示出，但是以下参照图2至图3示出和讨论)的半导体器件的附接。
粘合层103放置在第一载体衬底101上以帮助上面的结构(例如，聚合物层105)的粘合。在实施例中，粘合层103可以包括紫外胶，当其暴露于紫外光时，紫外胶失去其粘合性能。然而，也可以使用其它类型的粘合剂，诸如压敏粘合剂、辐射可固化粘合剂、环氧树脂、光热转换(LTHC)材料、这些的组合等。粘合层103可以以半液体或凝胶的形式放置在第一载体衬底101上，其在压力下容易变形。
例如，聚合物层105放置在粘合层103上方并且用于向第一半导体器件201和第二半导体器件301(一旦已附接第一半导体器件201和第二半导体器件301)提供保护。在实施例中，聚合物层105可以是聚苯并恶唑(PBO)，但是可以可选地利用诸如聚酰亚胺或聚酰亚胺的衍生物的任何适合的材料。可以使用例如旋涂工艺将聚合物层105放置为具有介于约0.5μm和约10μm之间(诸如5μm)的厚度，但是可以可选地利用任何合适的方法和厚度。
第一晶种层107形成在聚合物层105上方。在实施例中，第一晶种层107用作去湿结构，其可用于帮助减少或消除随后形成的第四外部连接件903(诸如焊料)之间的分层。因此，第一晶种层107可以由增加层的粘合而不引起其它不期望的晶种效应或去除问题的材料(诸如钛)形成，但是也可以利用任何其它合适的材料或材料的组合。第一晶种层107可以通过诸如物理汽相沉积、蒸发、化学汽相沉积、原子层沉积等的工艺形成，并且可以形成为具有介于约和约之间(诸如约)的厚度。然而，可以利用任何合适的方法或厚度。
第二晶种层109形成在第一晶种层107上方。在实施例中，第二晶种层109是有助于在随后工艺步骤期间形成更厚层的导电材料的薄层。第二晶种层109可以包括约厚的钛层以及随后的约厚的铜层。取决于所期望的材料，可以使用诸如物理汽相沉积、蒸发或PECVD工艺或金属箔层压工艺等的工艺生成第二晶种层109。第二晶种层109可以形成为具有介于约0.3μm和约1μm之间(诸如约0.5μm)的厚度。
图1也示出了位于第二晶种层109上方的光刻胶111的放置和图案化。在实施例中，可以使用例如旋涂技术在第二晶种层109上将光刻胶111放置为具有介于约50μm和约250μm之间(诸如约120μm)的高度。一旦放置在合适的位置，则然后可以通过将光刻胶111暴露于图案化的能量源(例如，图案化的光源)以引发化学反应，从而引发光刻胶111的暴露于图案化的光源的那些部分中的物理变化来图案化光刻胶111。然后将显影剂施加至曝光的光刻胶111以利用物理变化和取决于所期望的图案而选择性地去除光刻胶111的曝光部分或光刻胶111的未曝光部分。
在实施例中，在光刻胶111内形成的图案是用于通孔113的图案。以使得通孔113将位于随后附接的器件(诸如第一半导体器件201和第二半导体器件301)的不同侧上的布置来形成通孔113。然而，可以可选地利用通孔113的图案的任何合适的布置，诸如通孔113的图案定位为使得第一半导体器件201和第二半导体器件301放置在通孔113的相对侧上。
在实施例中，在光刻胶111内形成通孔113。在实施例中，通孔113包括诸如铜、钨、其它导电金属等的一种或多种导电材料，并且可以例如通过电镀、化学镀等形成。在实施例中，使用电镀工艺，其中，第二晶种层109和光刻胶111被淹没或浸没在电镀液中。第二晶种层109表面电连接至外部DC电源的负极侧，从而使得第二晶种层109在电镀工艺中用作阴极。诸如铜阳极的固体导电阳极也浸没在溶液中并且附接至电源的正极侧。来自阳极的原子溶解在溶液中，例如第二晶种层109的阴极从溶液中获取溶解的原子，从而对光刻胶111的开口内的第二晶种层109的暴露导电区域进行镀。
一旦已经使用光刻胶111和第二晶种层109形成通孔113，则可以使用合适的去除工艺去除光刻胶111(未在图1中示出，但在下面的图3中可见)。在实施例中，等离子灰化工艺可以用于去除光刻胶111，由此，光刻胶111的温度可以增加直至光刻胶111经历热分解并且可以被去除。然而，可以可选地利用任何其它合适的工艺，诸如湿剥离。光刻胶111的去除可以暴露出下面的第二晶种层109的部分。
一旦暴露，则可以实施第二晶种层109和第一晶种层107的暴露部分的去除(未在图1中示出，但在下面的图3中可见)。在实施例中，可以通过例如一种或多种湿或干蚀刻工艺去除第二晶种层109和第一晶种层107的暴露部分(例如，未由通孔113覆盖的那些部分)。例如，在干蚀刻工艺中，使用通孔113作为掩模，可以将反应剂导向第二晶种层109和第一晶种层107。在另一实施例中，蚀刻剂可以喷涂或以其它方式放置为与第二晶种层109和第一晶种层107接触以去除第二晶种层109和第一晶种层107的暴露部分。在已经蚀刻掉第二晶种层109和第一晶种层107的暴露部分之后，在通孔113之间暴露聚合物层105的部分。
在实施例中，通孔113、第一晶种层107和第二晶种层109将具有相同的第一宽度W1。例如，通孔113、第一晶种层107和第二晶种层109将具有约200μm的第一宽度W1。然而，可以利用任何合适的尺寸。
图2示出了将附接至通孔113(未在图2中示出，但是以下参照图3示出和描述)内的聚合物层105的第一半导体器件201。在实施例中，第一半导体器件201包括第一衬底203、第一有源器件(未单独示出)、第一金属化层205、第一接触焊盘207、第一钝化层211和第一外部连接件209。第一衬底203可以包括掺杂或未掺杂的块状硅或绝缘体上硅(SOI)衬底的有源层。通常，SOI衬底包括诸如硅、锗、锗硅、SOI、绝缘体上锗硅(SGOI)或它们的组合的半导体材料层。可以使用的其它衬底包括多层衬底、梯度衬底或混合取向衬底。
包括各种有源器件和无源器件(诸如电容器、电阻器、电感器等)的第一有源器件可以用于生成用于第一半导体器件201的设计的期望的结构和功能需求。可以在第一衬底203内或者上使用任何合适的方法形成第一有源器件。
第一金属化层205形成在第一衬底203和第一有源器件上方并且被设计为连接各个有源器件以形成功能电路。在实施例中，第一金属化层205由介电材料和导电材料的交替层形成并且可以通过任何适合的工艺(诸如沉积、镶嵌、双镶嵌等)的形成。在实施例中，可能存在通过至少一个层间介电层(ILD)与第一衬底203分隔开的四个金属化层，但是第一金属化层205的精确数目取决于第一半导体器件201的设计。
第一接触焊盘207可以形成在第一金属化层205上方并且与第一金属化层205电接触。第一接触焊盘207可以包括铝，但是可以可选地使用诸如铜的其它材料。可以使用诸如溅射的沉积工艺以形成材料层(未示出)并且然后可以通过合适的工艺(诸如光刻掩模和蚀刻)去除材料层的部分以形成第一接触焊盘207来形成第一接触焊盘207。然而，可以利用任何其它合适的工艺来形成第一接触焊盘207。第一接触焊盘可以形成为具有介于约0.5μm和约4μm之间(诸如约1.45μm)的厚度。
可以在第一衬底203上的第一金属层205和第一接触焊盘207上方形成第一钝化层211。第一钝化层211可以由一种或多种合适的介电材料制成，介电材料诸如氧化硅、氮化硅、诸如碳掺杂的氧化物的低k电介质、诸如多孔碳掺杂的二氧化硅的极低k电介质、这些的组合等。可以通过诸如化学汽相沉积(CVD)的工艺形成第一钝化层211，但是可以利用任何合适的工艺，并且第一钝化层211可以具有介于约0.5μm和约5μm之间(诸如约)的厚度。
可以形成第一外部连接件209以在第一接触焊盘207和例如再分布层(RDL)501(未在图2中示出，但是以下参照图5示出和描述)之间提供接触的导电区域。在实施例中，第一外部连接件209可以是导电柱并且可以通过首先在第一钝化层211上方形成介于约5μm和约20μm之间(诸如约10μm)的厚度的光刻胶(未示出)来形成。可以图案化光刻胶以暴露第一钝化层211的导电柱将延伸穿过的部分。一旦图案化，则然后光刻胶可以用作掩模以去除第一钝化层211的期望部分，从而暴露第一外部连接件209将与之接触的下面的第一接触焊盘207的那些部分。
第一外部连接件209可以形成在第一钝化层211和光刻胶的开口内。第一外部连接件209可以由诸如铜的导电材料形成，但是也可以使用其它导电材料，诸如镍、金、焊料、金属合金、这些的组合等。此外，可以使用诸如电镀的工艺来形成第一外部连接件209，通过电镀，电流流过第一接触焊盘207的期望形成第一外部连接件209的导电部分，并且第一接触焊盘207浸没在溶液中。溶液和电流将例如铜沉积在开口内以填充和/或过填充光刻胶和第一钝化层211的开口，从而形成第一外部连接件209。然后，可以使用例如灰化工艺、化学机械抛光(CMP)工艺、这些的组合等去除位于第一钝化层211的开口的外侧的过量的导电材料和光刻胶。
然而，本领域普通技术人员将意识到，上述形成第一外部连接件209的工艺仅仅是一种这样的描述，而不用于将实施例限于这种精确的工艺。而且，所描述的工艺仅旨在说明，如可以可选地利用用于形成第一外部连接件209的任何合适的工艺。所有合适的工艺均旨在完全包括在本发明的范围内。
可以将第一管芯附接膜217放置在第一衬底203的相对侧上以有助于将第一半导体器件201附接至聚合物层105。在实施例中，第一管芯附接膜217是环氧树脂、酚醛树脂、丙烯酸橡胶、硅胶填料或它们的组合，并且使用层压技术来施加。然而，可以可选地使用任何其它合适的可选材料和形成方法。
图3示出了在聚合物层105上放置第一半导体器件201以及放置第二半导体器件301。在实施例中，第二半导体器件301可以包括第二衬底303、第二有源器件(未单独示出)、第二金属化层305、第二接触焊盘307、第二钝化层311、第二外部连接件309和第二管芯附接膜317。在实施例中，第二衬底303、第二有源器件、第二金属化层305、第二接触焊盘307、第二钝化层311、第二外部连接件309和第二管芯附接膜317可以与参照图2描述的第一衬底203、第一有源器件、第一金属化层205、第一接触焊盘207、第一钝化层211、第一外部连接件209和第一管芯附接膜217类似，但是它们也可能不同。
在实施例中，可以将第一半导体器件201和第二半导体器件301放置在不同的通孔113之间的聚合物层105上。在实施例中，可以使用例如拾取和放置工艺放置第一半导体器件201和第二半导体器件301。然而，也可以利用将第一半导体器件201和第二半导体器件301放置在聚合物层105上的任何其它方法。
图4示出了通孔113、第一半导体器件201和第二半导体器件301的密封。可以在模制器件(未在图4中单独示出)中实施该密封，模制器件可以包括顶部模制部分和与顶部模制部分分隔开的底部模制部分。当顶部模制部分降低至邻近底部模制部分时，可以形成用于第一载体衬底101、通孔113、第一半导体器件201和第二半导体器件301的模腔。
在密封工艺期间，可以将顶部模制部分放置为邻近底部模制部分，从而将第一载体衬底101、通孔113、第一半导体器件201和第二半导体器件301封闭在模腔内。一旦封闭，顶部模制部分和底部模制部分可以形成气密密封以控制气体从模腔的流入和流出。一旦密封，则可以将密封剂401放置在模腔内。密封剂401可以是模塑料树脂，诸如聚酰亚胺、PPS、PEEK、PES、耐热晶体树脂，这些的组合等。可以在顶部模制部分和底部模制部分的对准之前，将密封剂401放置在模腔内，或者可以通过注入端口将密封剂401注入模腔。
一旦已经将密封剂401放置在模腔内，从而使得密封剂401密封第一载体衬底101、通孔113、第一半导体器件201和第二半导体器件301，则可以固化密封剂401以硬化密封剂401，从而用于最佳保护。虽然精确的固化工艺至少部分取决于选择用于密封剂401的特定材料，但是在将模塑料选择作为密封剂401的实施例中，可以通过诸如将密封剂401加热至介于约100℃和约130℃之间(诸如约125℃)的温度，持续约60秒至约3600秒(诸如约600秒)的工艺进行固化。此外，引发剂和/或催化剂可以包括在密封剂401内以更好地控制该固化工艺。
然而，本领域普通技术人员将意识到，上述固化工艺仅仅是示例性工艺，而不旨在限制当前的实施例。可以可选地使用诸如照射或甚至允许密封剂401在环境温度下固化的其它固化工艺。可以使用任何合适的固化工艺，并且所有这些工艺均旨在完全包括在本文所讨论的实施例的范围内。
图4也示出了密封剂401的减薄以暴露通孔113、第一半导体器件201和第二半导体器件301以用于进一步处理。例如，可以使用机械研磨或化学机械抛光(CMP)工艺来实施减薄，从而利用化学蚀刻剂和研磨剂以反应和研磨掉密封剂401、第一半导体器件201和第二半导体器件301，直至已经暴露通孔113、第一外部连接件209(位于第一半导体器件201上)和第二外部连接件309(位于第二半导体器件301上)。因此，第一半导体器件201、第二半导体器件301和通孔113可以具有平坦的表面，该平坦的表面也与密封剂401齐平。
然而，虽然上述CMP工艺呈现为一个示例性实施例，但是其不旨在限制该实施例。可以可选地使用任何其它合适的去除工艺以减薄密封剂401、第一半导体器件201和第二半导体器件301并且暴露通孔113。例如，可以利用一系列的化学蚀刻。该工艺和任何其它合适的工艺可以可选地用于减薄密封剂401、第一半导体器件201和第二半导体器件301，并且所有这些工艺均旨在完全包括在实施例的范围内。
图5示出了RDL 501的形成以使第一半导体器件201、第二半导体器件301、通孔113和第三外部连接件505互连。通过使用RDL 501来互连第一半导体器件201和第二半导体器件301，第一半导体器件201和第二半导体器件301可以具有大于1000的引脚数。
在实施例中，可以通过首先由诸如CVD或溅射的合适的形成工艺形成钛铜合金的晶种层(未示出)来形成RDL 501。然后可以形成光刻胶(也未示出)以覆盖晶种层，并且然后可以图案化该光刻胶以暴露晶种层的期望RDL 501定位在该位置的那些部分。
一旦已形成并且图案化光刻胶，则可以通过诸如镀的沉积工艺在晶种层上形成诸如铜的导电材料。导电材料可以形成为具有介于约1μm和约10μm之间(诸如约5μm)的厚度。然而，虽然讨论的材料和方法适用于形成导电材料，但是这些材料仅仅是示例性的。诸如AlCu或Au的任何其它合适的材料和诸如CVD或PVD的任何其它合适的形成工艺均可以用于形成RDL 501。
一旦已经形成导电材料，则可以通过诸如灰化的合适的去除工艺去除光刻胶。此外，在光刻胶的去除之后，例如，可以通过使用导电材料作为掩模的合适的蚀刻工艺去除晶种层的由光刻胶覆盖的那些部分。
图5也示出了在RDL 501上方形成第三钝化层503以向RDL 501和下面的其它结构提供保护和隔离。在实施例中，第三钝化层503可以是聚苯并恶唑(PBO)，但是可以利用诸如聚酰亚胺和聚酰亚胺的衍生物的任何适合的材料。可以使用例如旋涂工艺将第四钝化层503放置为具有介于约5μm和约25μm之间(诸如约7μm)的厚度，但是可以可选地使用任何合适的方法和厚度。
而且，虽然在图5中仅示出了单个RDL 501，但是这旨在用于清楚的目的，而不旨在限制实施例。而且，可以通过重复上述用于形成RDL 501的工艺来形成任何合适数量的导电层和钝化层(诸如三个RDL 501层)。可以利用任何合适数量的层。
图5进一步示出了第三外部连接件505的形成以制成与RDL 501的电接触。在实施例中，在已经形成第三钝化层503之后，可以通过去除第三钝化层503的部分以暴露下面的RDL501的至少一部分来制成穿过第三钝化层503的开口。开口允许RDL 501和第三外部连接件505之间的接触。可以使用合适的光刻掩模和蚀刻工艺来形成开口，但是可以使用用于暴露RDL 501的部分的任何合适的工艺。
在实施例中，第三外部连接件505可以穿过第三钝化层503而放置在RDL 501上并且可以是包括诸如焊料的共晶材料的球栅阵列(BGA)，但是可以可选地使用任何合适的材料。任选地，可以在第三外部连接件505和RDL 501之间利用凸块下金属。在第三外部连接件505是焊料凸块的实施例中，可以使用球落方法(诸如直接球落工艺)来形成第三外部连接件505。可选地，可以通过首先由诸如蒸发、电镀、印刷、焊料转移的任何合适的方法形成薄层，并且然后实施回流以将材料成形为期望的凸块形状来形成焊料凸块。一旦已经形成第三外部连接件505，则可以实施测试以确保该结构适合于进一步处理。
图6A示出了将第一载体衬底101从第一半导体器件201和第二半导体器件301脱粘。在实施例中，可以将第三外部连接件505并且因此，包括第一半导体器件201和第二半导体器件301的结构附接至环结构601。环结构601可以是在脱粘工艺期间和之后旨在为该结构提供支撑和稳定性的金属环。在实施例中，例如，使用紫外线胶带603将第三外部连接件505、第一半导体器件201和第二半导体器件301附接至环结构，但是可以可选地使用任何其它合适的粘合剂或附接件。
一旦将第三外部连接件505并且因此，包括第一半导体器件201和第二半导体器件301的结构附接至环结构601，则可以使用例如热工艺以改变粘合层103的粘合性能来将第一载体衬底101与包括第一半导体器件201和第二半导体器件301的结构脱粘。在特定实施例中，利用诸如紫外线(UV)激光、二氧化碳(CO2)激光或红外线(IR)激光的能量源来照射和加热粘合层103，直至粘合层103失去它的至少一些粘合性能。一旦实施，则第一载体衬底101和粘合层103可以物理分离并且从包括第三外部连接件505、第一半导体器件201和第二半导体器件301的结构去除。
图6B示出了用于将第一载体衬底101从第一半导体器件201和第二半导体器件301脱粘的另一实施例。在本实施例中，例如，可以使用第一胶607将第三外部连接件505附接至第二载体衬底605。在实施例中，第二载体衬底605与第一载体衬底101类似，但是其也可以是不同的。一旦附接，则可以照射粘合层103并且可以物理地去除粘合层103和第一载体衬底101。
返回至利用环结构601的实施例，图7示出了聚合物层105的图案化以形成第一开口703并且暴露通孔113(以及与每个通孔113相关的第二晶种层109)。在实施例中，例如，可以使用激光钻孔方法图案化聚合物层105，通过激光钻孔方法，将激光导向聚合物层105的期望被去除以暴露下面的第一晶种层107的那些部分。在激光钻孔工艺期间，钻孔能量可以在从0.1mJ至约60mJ的范围内，以及相对于聚合物层105的法线的钻孔角为约0度(垂直于聚合物层105)至约85度。
在实施例中，图案化可以形成为在第一通孔113上方形成第一开口703以具有小于通孔113的第一宽度W1的第二宽度W2。例如，在第一宽度W1为约200μm的实施例中，第一开口703可以形成为具有小于约200μm(诸如约150μm)的第二宽度W2。然而，可以利用任何合适的尺寸。
在另一实施例中，可以通过首先对聚合物层105施加光刻胶(未在图7中单独示出)并且然后将光刻胶暴露于图案化的能量源(例如，图案化的光源)以引发化学反应，从而引发光刻胶的暴露于图案化的光源的那些部分中的物理变化来图案化聚合物层105。然后对曝光的光刻胶施加显影剂以利用物理变化并且取决于所期望的图案而选择性地去除光刻胶的曝光部分或光刻胶的未曝光部分，并且例如，利用干蚀刻工艺去除下面的聚合物层105的曝光部分。然而，可以利用用于图案化聚合物层105的任何其它合适的方法。
图8A至图8B示出了穿过图案化的聚合物层105的第一晶种层107的图案化以暴露下面的第二晶种层109，以及聚合物层105的剩余部分的去除，其中，图8B示出了第一晶种层107和第二晶种层109的单个组合的俯视图。在实施例中，第一晶种层107的图案化和聚合物层105的去除可以使用两步后激光钻孔清洁(PLDC)工艺来实施，其中第一步骤用于图案化第一晶种层107。
例如，在实施例中，PLDC工艺的第一步骤可以包括诸如各向异性蚀刻工艺的第一蚀刻工艺，诸如利用等离子体的干蚀刻工艺。例如，在一个实施例中，第一蚀刻工艺利用对第一晶种层107有选择性的蚀刻剂并且将蚀刻剂导向第一晶种层107的暴露部分(由图案化的聚合物层105掩蔽)。因此，可以将第一开口703的图案转印至第一晶种层107中并且暴露第二晶种层109。
具体地，因为在聚合物层105的去除(以下进一步讨论)之前，第一开口703已经形成在聚合物层105内，因此在第一蚀刻工艺期间暴露第一晶种层107的部分。因此，第一蚀刻工艺将去除第一晶种层107的暴露部分，从而将第一开口703的图案转印至第一晶种层107中并且暴露下面的第二晶种层109。
一旦已经暴露第二晶种层109，则可以使用PLDC的第二步骤来去除聚合物层105的剩余部分。例如，第二步骤可以利用对聚合物层105的材料具有选择性的蚀刻剂的第二蚀刻工艺，诸如各向异性蚀刻工艺(利用等离子体的干蚀刻工艺)。利用对聚合物层105的材料具有选择性的蚀刻剂，第二蚀刻工艺可以去除聚合物层105的材料，其中，可以不去除或最少去除第一晶种层107和第二晶种层109的材料。然而，可以利用诸如湿蚀刻工艺的任何合适的去除工艺来去除聚合物层105。
参见图8B，可以将第一晶种层107图案化成环形，其中，中心区域被去除。在实施例中，环形可以具有介于约30μm和约250μm之间(诸如约200μm)的第一宽度W1的外径Do，以及介于约10μm和约230μm之间(诸如约150μm)的第二宽度W2的内径Di。然而，可以利用任何合适的尺寸。
此外，虽然第一晶种层107示出为被图案化成环形，但是该形状旨在说明，而不旨在限制。而且，可以利用提供额外的粘合的任何合适的形状。例如，第一晶种层107可以被图案化成矩形或任何其它合适的形状。所有这些形状均完全旨在包括在实施例的范围内。
通过打开聚合物层105(使用例如激光钻孔)来形成第一开口703，并且随后利用PLDC(使用例如多步等离子体清洁)，所得到的结构在打开的第二晶种层109(例如，铜)周围具有去湿环(例如，钛)。这种去湿环用作去湿结构，以在没有聚合物层105用作应力缓冲器的额外需求和成本的情况下帮助防止底部填充物和焊料之间的分层问题(以下进一步讨论)，分层可能导致金属接触件和通孔113(中介层通孔(TIV))之间的进一步分层。
可选地，在已经去除聚合物层105之后，可以放置背侧球焊盘(未在图8A中单独示出)以保护现在暴露的第二晶种层109。在实施例中，背侧球焊盘可以包括诸如膏上焊料或有机可焊性保护剂(OSP)的导电材料，但是可以可选地利用任何合适的材料。在实施例中，可以使用模板来施加背侧球焊盘，但是可以可选地利用任何合适的施加方法，并且然后回流以形成凸块形状。
同样可选地，可以在背侧球焊盘上方放置并且图案化背侧保护层(也未在图8A中示出)，以密封背侧球焊盘以及第一晶种层107和第二晶种层109之间的接头免受湿气侵入。在实施例中，背侧保护层可以是诸如PBO、阻焊剂(SR)、层压复合(LC)胶带、味之素构建膜(ABF)、非导电膏(NCP)、非导电膜(NCF)、图案化的底部填充物(PUF)、翘曲改进粘合剂(WIA)、液体模塑料V9、这些的组合等的保护材料。然而，也可以使用任何合适的材料。可以使用诸如丝网印刷、层压、旋涂等的工艺施加厚度介于约1μm至约100μm之间的背侧保护层。
图9示出了与第一晶种层107和第二晶种层109物理接触的第四外部连接件903的放置(在不存在背侧球焊盘的实施例中)。在实施例中，第四外部连接件903可以形成为提供通孔113与例如第一封装件1000和第二封装件1019(未在图9中示出但以下参照图10示出和讨论)之间的外部连接。第四外部连接件903可以是诸如微凸块或可控塌陷芯片连接(C4)凸块的接触凸块并且可以包括诸如锡的材料或诸如膏上焊料、银或铜的其它合适的材料。在第四外部连接件903是锡焊料凸块的实施例中，可以通过首先由诸如蒸发、电镀、印刷、焊料转移、球放置等的任何合适的方法来形成厚度例如为约100μm的锡层来形成第四外部连接件903。一旦已经在结构上形成锡层，则实施回流以将材料成形为期望的凸块形状。
图10示出了第四外部连接件903至第一封装件1000的接合。在实施例中，第一封装件1000可以包括第三衬底1003、第三半导体器件1005、第四半导体器件1007(接合至第三半导体器件1005)、第三接触焊盘1009(用于电连接至第四外部连接件903)以及第二密封剂1011。在实施例中，第三衬底1003可以是例如封装衬底，封装衬底包括内部互连件(例如，衬底通孔1015)以将第三半导体器件1005和第四半导体器件1007连接至第四外部连接件903。
可选地，第三衬底1003可以是用作中间衬底的中介层以将第三半导体器件1005和第四半导体器件1007连接至第四外部连接件903。在本实施例中，第三衬底1003可以是例如掺杂或未掺杂的硅衬底或绝缘体上硅(SOI)衬底的有源层。然而，第三衬底1003可以可选地为玻璃衬底、陶瓷衬底、聚合物衬底或可以提供合适的保护和/或互连功能的任何其它衬底。这些和任何其它合适的材料可以可选地用于第三衬底1003。
第三半导体器件1005可以是设计为用于预期目的的半导体器件，诸如为逻辑管芯、中央处理单元(CPU)管芯、存储器管芯(例如，DRAM管芯)、这些的组合等。在实施例中，第三半导体器件1005包括期望用于特定功能的集成电路器件，诸如晶体管、电容器、电感器、电阻器、第一金属化层(未示出)等。在实施例中，第三半导体器件1005被设计和制造为与第一半导体器件201一起或同时工作。
第四半导体器件1007可以与第三半导体器件1005类似。例如，第四半导体器件1007可以是设计为用于预期目的(例如，DRAM管芯)并且包括集成电路器件的半导体器件以用于期望功能。在实施例中，第四半导体器件1007被设计为与第一半导体器件201和/或第三半导体器件1005一起或同时工作。
第四半导体器件1007可以接合至第三半导体器件1005。在实施例中，诸如通过使用粘合剂仅将第四半导体器件1007与第三半导体器件1005物理接合。在本实施例中，第四半导体器件1007和第三半导体器件1005可以使用例如引线接合1017电连接至第三衬底1003，但是可以可选地利用任何合适的电接合。
可选地，第四半导体器件1007可以物理和电接合至第三半导体器件1005。在本实施例中，第四半导体器件1007可以包括与第三半导体器件1005上的第五外部连接件(未在图10中单独示出)连接的第四外部连接件(也未在图10中单独示出)以将第四半导体器件1007与第三半导体器件1005互连。
第三接触焊盘1009可以形成在第三衬底1003上以在第三半导体器件1005和例如第四外部连接件903之间形成电连接。在实施例中，第三接触焊盘1009可以形成在第三衬底1003内的电气布线(诸如衬底通孔1015)上方并且与电气布线电接触。第三接触焊盘1009可以包括铝，但是可以可选地使用诸如铜的其它材料。可以使用诸如溅射的沉积工艺以形成材料层(未示出)并且然后通过合适的工艺(诸如光刻掩模和蚀刻)去除材料层的部分以形成第三接触焊盘1009来形成第三接触焊盘1009。然而，可以利用任何其它合适的工艺来形成第三接触焊盘1009。第三接触焊盘1009可以形成为具有介于约0.5μm和约4μm之间(诸如约1.45μm)的厚度。
第二密封剂1011可以用于密封和保护第三半导体器件1005、第四半导体器件1007和第三衬底1003。在实施例中，第二密封剂1011可以是模塑料并且可以使用模制器件(未在图10中示出)来放置。例如，可以将第三衬底1003、第三半导体器件1005和第四半导体器件1007放置在模制器件的腔内，并且该腔可以气密地密封。可以在气密地密封腔之前将第二密封剂1011放置在腔内或者可以通过注入端口将第二密封剂1011注入至腔内。在实施例中，第二密封剂1011可以是模塑料树脂，诸如聚酰亚胺、PPS、PEEK、PES、耐热晶体树脂、这些的组合等。
一旦已被将第二密封剂1011放置在腔内，从而使得第二密封剂1011密封第三衬底1003、第三半导体器件1005和第四半导体器件1007周围的区域，则可以固化第二密封剂1011以硬化第二密封剂1011，从而用于最佳保护。虽然精确的固化工艺至少部分取决于选择用于第二密封剂1011的特定材料，在将模塑料选择作为第二密封剂1011的实施例中，可以通过诸如将第二密封剂1011加热至介于约100℃和约130℃之间(诸如约125℃)的温度持续约60秒至约3000秒(诸如约600秒)的工艺进行这种固化。此外，引发剂和/或催化剂可以包括在第二密封剂1011内以更好地控制该固化工艺。
然而，本领域普通技术人员将意识到，上述固化工艺仅仅是示例性工艺，而不旨在限制当前的实施例。可以使用诸如照射或甚至允许第二密封剂1011在环境温度下硬化的其它固化工艺。可以使用任何合适的固化工艺，并且所有这些工艺均旨在完全包括在本文所讨论的实施例的范围内。
一旦已经形成第四外部连接件903，则第四外部连接件903与第三接触焊盘1009对准并且放置为与第三接触焊盘1009物理接触，并且实施接合。例如，在第四外部连接件903是焊料凸块的实施例中，接合工艺可以包括回流工艺，从而将第四外部连接件903的温度升高至第四外部连接件903将液化并且流动的点，从而当第四外部连接件903重新固化时，将第一封装件1000接合至第四外部连接件903。
通过在第二半导体器件301上方放置第一封装件1000(其可以是例如DRAM封装件)，将第一封装件1000放置在设计为容纳第一封装件1000的第一容纳区域上方。在实施例中，第一容纳区域具有由放置在第一容纳区域上的第一封装件1000的期望尺寸确定的尺寸和形状。
图10额外示出了第二封装件1019至第四外部连接件903的接合。在实施例中，第二封装件1019可以与第一封装件1000类似，并且可以利用类似的工艺接合至第四外部连接件903。然而，第二封装件1019也可以与第一封装件1000不同。
图10也示出了第一封装件1000和第二封装件1019之间的底部填充材料1021的放置。在实施例中，底部填充材料1021是用于垫起和支撑第一封装件1000和第一封装件1019以免受操作和环境劣化(诸如操作期间热量生成所引起的应力)的保护材料。底部填充材料1021可以注入或者以其它方式形成在第一封装件1000和第二封装件1019之间的间隔中，并且例如可以包括分配在第一封装件1000和第二封装件1019之间并且然后固化以硬化的液体环氧树脂。
图11示出了第一封装件1000与第二封装件1019的分割。在实施例中，可以通过使用锯条(未单独示出)来割穿底部填充材料1021和密封剂401来实施分割。然而，本领域普通技术人员将意识到，使用锯条来分割仅仅是一个示例性实施例，而不旨在限制。可以利用任何用于实施分割的方法，诸如利用一个或多个蚀刻。这些方法和任何其它适当的方法均可以用于分割第一封装件1000与第二封装件1019。
通过利用第一晶种层107并且将其图案化成如上所述的去湿结构，可以减小底部填充材料1021和第四外部连接件903之间的分层的风险。因此，可以减小第四外部连接件903和通孔113之间的分层或裂缝的风险。这种改进将提高制造工艺的良率。
在实施例中，制造半导体器件的方法包括在衬底上方沉积第一衬垫层；沉积与第一衬垫层物理接触的第一晶种层；将通孔镀在第一晶种层上；使用通孔作为掩模去除第一衬垫层和第一晶种层的部分；用密封剂密封通孔以及半导体管芯；以及在密封通孔之后，图案化第一衬垫层以暴露第一晶种层的内部而不暴露第一晶种层的外部。在实施例中，第一衬垫层包括钛。在实施例中，第一晶种层包括铜。在实施例中，该方法还包括在密封通孔之后，在通孔上方形成聚合物层。在实施例中，该方法还包括去除聚合物层的部分以暴露第一衬垫层。在实施例中，去除聚合物层的部分包括将激光导向聚合物层。在实施例中，该方法还包括将导电材料放置为与第一衬垫层和第一晶种层直接物理接触。
在另一实施例中，制造半导体器件的方法包括：将密封剂放置在聚合物层上方，密封剂密封半导体器件和多个通孔，多个通孔中的每个通孔均与半导体器件横向分隔开；图案化聚合物层以暴露多个通孔中的一个通孔的第一衬垫层；将第一衬垫层图案化成环结构，其中，使用聚合物层作为掩模来实施图案化第一衬垫层，并且其中，图案化第一衬垫层暴露第一晶种层的部分；以及将导电材料放置为通过第一衬垫层与第一晶种层物理接触。在实施例中，第一衬垫层是钛。在实施例中，第一晶种层包括铜。在实施例中，图案化聚合物层包括激光钻孔。在实施例中，图案化第一衬垫层包括实施干蚀刻工艺。在实施例中，该方法还包括在图案化第一衬垫层之后去除聚合物层。在实施例中，环结构具有介于约150μm和约200μm之间的内径。
在另一实施例中，半导体器件包括密封半导体器件的密封剂；从密封剂的第一侧延伸至密封剂的第二侧的第一通孔，第一通孔包括：第一衬垫层；与第一衬垫层物理接触的第一晶种层，第一晶种层与第一衬垫层不同；以及与位于第一晶种层的与第一衬垫层相对的侧上的第一晶种层物理接触的导电材料，其中，第一衬垫层是环形。在实施例中，环形具有大于约150μm的内径。在实施例中，环形具有小于约200μm的外径。在实施例中，第一衬垫层包括去湿材料。在实施例中，去湿材料是钛。在实施例中，钛具有介于和之间的厚度。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种制造半导体器件的方法，所述方法包括：
在衬底上方沉积第一衬垫层；
沉积与所述第一衬垫层物理接触的第一晶种层；
将通孔镀在所述第一晶种层上；
使用所述通孔作为掩模去除所述第一衬垫层和所述第一晶种层的部分；
用密封剂密封所述通孔以及半导体管芯；以及
在密封所述通孔之后，图案化所述第一衬垫层以暴露所述第一晶种层的内部而不暴露所述第一晶种层的外部。
2.根据权利要求1所述的方法，其中，所述第一衬垫层包括钛。
3.根据权利要求2所述的方法，其中，所述第一晶种层包括铜。
4.根据权利要求1所述的方法，还包括：在密封所述通孔之后，在所述通孔上方形成聚合物层。
5.根据权利要求4所述的方法，还包括：去除所述聚合物层的部分以暴露所述第一衬垫层。
6.根据权利要求5所述的方法，其中，去除所述聚合物层的部分包括将激光导向所述聚合物层。
7.根据权利要求1所述的方法，还包括：将导电材料放置为与所述第一衬垫层和所述第一晶种层直接物理接触。
8.一种制造半导体器件的方法，所述方法包括：
将密封剂放置在聚合物层上方，所述密封剂密封半导体器件和多个通孔，所述多个通孔中的每个通孔均与所述半导体器件横向分隔开；
图案化所述聚合物层以暴露所述多个通孔中的一个通孔的第一衬垫层；
将所述第一衬垫层图案化成环结构，其中，使用所述聚合物层作为掩模来实施图案化所述第一衬垫层，并且其中，图案化所述第一衬垫层暴露第一晶种层的部分；以及
将导电材料放置为穿过所述第一衬垫层与所述第一晶种层物理接触。
9.根据权利要求8所述的方法，其中，所述第一衬垫层是钛。
10.一种半导体器件，包括：
密封剂，密封半导体器件；
第一通孔，从所述密封剂的第一侧延伸至所述密封剂的第二侧，所述第一通孔包括：
第一衬垫层；
第一晶种层，与所述第一衬垫层物理接触，所述第一晶种层与所述第一衬垫层不同；以及
导电材料，在所述第一晶种层的与所述第一衬垫层相对的侧上与所述第一晶种层物理接触，其中，所述第一衬垫层是环形。
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