CN107393865A - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
- Publication number
- CN107393865A CN107393865A CN201611119841.XA CN201611119841A CN107393865A CN 107393865 A CN107393865 A CN 107393865A CN 201611119841 A CN201611119841 A CN 201611119841A CN 107393865 A CN107393865 A CN 107393865A
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- semiconductor devices
- hole
- interconnection structure
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Classifications
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H01—ELECTRIC ELEMENTS
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract
本发明提供了一种半导体器件及其制造方法。特别地,半导体器件包括位于顶封装件和再分布层(RDL)之间并且连接顶封装件和再分布层(RDL)的第一组贯通孔、第一组贯通孔与模塑料物理接触并且与管芯分离。半导体器件还包括位于顶封装件和RDL之间并且连接顶封装件和RDL的第一互连结构,第一互连结构通过模塑料与管芯和第一组贯通孔分离。第一互连结构包括第二组贯通孔和至少一个集成无源器件。
Description
技术领域
本发明的实施例涉及半导体器件。
背景技术
由于各种电子组件(例如,晶体管、二极管、电阻器、电容器等)的集成密度的不断提高,半导体产业经历了快速增长。很大程度上,集成密度的这种改进源于最小部件尺寸的重复减小(例如,朝向亚20nm节点缩小半导体工艺节点),这允许将更多的组件集成到给定区域中。随着对小型化、更高速度和更大带宽以及更低功耗和延迟的需求的增长,对于半导体管芯的更小且更具创造性的封装技术的需求也已增长。
随着半导体技术的进一步发展,堆叠和接合的半导体器件已经作为有效替代物出现以进一步减小半导体器件的物理尺寸。在堆叠的半导体器件中,在单独衬底上至少部分地制造诸如逻辑、存储器、处理器电路等有源电路,并且然后将这些有源电路物理地接合且电接合在一起以形成功能器件。这样的接合工艺利用复杂的技术,并且期望改进。
发明内容
本发明的实施例提供了一种半导体器件,包括:再分布层(RDL);管芯,设置在所述再分布层上;第一组贯通孔,位于顶衬底和所述再分布层之间并且连接所述顶衬底和所述再分布层,所述第一组贯通孔与模塑料物理接触并且通过所述模塑料与所述管芯分离;以及第一互连结构,位于所述顶衬底和所述再分布层之间并且连接所述顶衬底和所述再分布层,所述第一互连结构通过所述模塑料与所述管芯和所述第一组贯通孔分离,所述第一互连结构包括:至少一个无源器件;以及第二组贯通孔,位于所述第一互连结构内。
本发明的另一实施例提供了一种半导体器件,包括:层,位于封装件和再分布层(RDL)之间,所述层包括:半导体管芯,其中,所述半导体管芯的第一侧连接至所述再分布层并且所述半导体管芯的第二侧附接至聚合物层;至少一个第一通孔,从所述层的第一侧延伸至所述层的第二侧;第一无源器件结构,所述第一无源器件结构包括:至少一个无源器件;以及至少一个第二通孔,设置在所述第一无源器件结构内;第二无源器件结构,所述第二无源器件结构包括:至少一个无源器件;以及至少一个第三通孔,设置在所述第二无源器件结构内;模塑料,围绕所述半导体管芯、所述至少一个第一通孔、所述第一无源器件结构和所述第二无源器件结构,其中,所述第一无源器件结构通过所述模塑料与所述至少一个第一通孔和所述第二无源器件结构分离,其中,所述至少一个第一通孔从所述模塑料的第一侧延伸至所述模塑料的第二侧;以及其中,所述至少一个第一通孔,所述至少一个第二通孔和所述至少一个第三通孔连接所述再分布层和所述封装件,其中,所述至少一个第二通孔和所述至少一个第三通孔是衬底贯通孔(TSV)。
本发明的又一实施例提供了一种制造半导体器件的方法,所述方法包括:在再分布层(RDL)上形成一组通孔;在所述再分布层上放置与所述一组通孔分离的管芯;以及在所述再分布层上放置第一互连结构,所述第一互连结构与所述管芯和所述一组通孔分离,所述第一互连结构包括:衬底;至少一个导电元件,从所述衬底的一侧延伸至所述衬底的第二侧;以及至少一个集成无源器件;将所述一组通孔、所述管芯和所述第一互连结构密封在所述密封剂中,其中,所述密封剂与所述一组通孔、所述管芯和所述第一互连结构物理接触;以及平坦化所述一组通孔、所述管芯、所述密封剂和所述第一互连结构。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳地理解本发明的各个方面。应该注意,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各种部件的尺寸可以被任意增大或减小。
图1示出根据一些实施例的集成无源器件的形成。
图2示出根据一些实施例的衬底贯通孔的形成。
图3示出根据一些实施例的金属化层和钝化层的形成。
图4示出根据一些实施例的外部连接件的形成。
图5示出根据一些实施例的削薄衬底。
图6示出根据一些实施例的再分布层的形成。
图7示出根据一些实施例的分割工艺。
图8示出根据一些实施例的贯通孔的形成。
图9示出根据一些实施例的第一半导体器件的实施例。
图10示出根据一些实施例的将第一半导体器件和第一互连结构放置在贯通孔之间。
图11示出根据一些实施例的第一半导体器件、第一互连结构和贯通孔的封装。
图12示出根据一些实施例的再分布层和外部连接件的形成。
图13示出根据一些实施例的载体晶圆的脱粘。
图14示出根据一些实施例的第一封装件和第二封装件的接合。
图15示出根据一些实施例的InFO-POP结构。
图16示出根据一些实施例的InFO-POP结构的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,在以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为了便于描述,在此可以使用诸如“在…下方”、“在…下面”、“下”、“在…之上”、“上”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),并且在此使用的空间相对描述符可以同样地作出相应的解释。
图1至图7示出第一互连结构711和第二互连结构713的实施例的形成。在一些实施例中,第一互连结构711和第二互连结构713可以是嵌入式双侧IPD(eDS-IPD)。现参照图1,示出第一衬底101、集成无源器件(IPD)103和第一金属化层105。第一衬底101可包括掺杂或未掺杂的块状硅、绝缘体上硅(SOI)衬底、二氧化硅(SiO2)或其它绝缘材料或另外的材料。IPD 103可包括诸如电容器、电阻器、电感器等各种无源器件。在图1至图7示出的实施例中,IPD 103示出为深沟槽电容器,但是在其他实施例中,IPD 103可包括如上所述的无源器件的一种或多种其他类型。
在第一衬底101内或第一衬底101上可以使用任何合适的方法形成IPD103。例如,可通过在第一衬底101内首先形成沟槽来形成深沟槽电容器。可通过任何合适的光刻掩模和蚀刻工艺来形成沟槽。例如,可在第一衬底101上方形成和图案化光刻胶,并且可以利用一种或多种蚀刻工艺(例如,干蚀刻工艺)以去除期望深沟槽电容器所在的第一衬底101的那些部分。可通过诸如沉积工艺或其他工艺在沟槽中形成第一导电电极材料来形成第一电容器电极。第一导电电极材料可以是诸如掺杂硅、多晶硅、铜、钨、铝或铜合金或其他导电材料的导电材料。可以在沟槽内的第一导电电极材料上方形成介电层。介电层可包括高K介电材料、氧化物、氮化物等或它们的组合或它们的多层,并且可使用诸如CVD工艺的任何合适的沉积工艺来形成介电层。可通过诸如沉积工艺或其他工艺在沟槽中的介电层上方形成第二导电电极材料以形成第二电容器电极。第二导电电极材料可以是诸如掺杂硅、多晶硅、铜、钨、铝或铜合金或其他导电材料的导电材料。本领域普通技术人员将意识到,上文中描述的用于形成深沟槽电容器的工艺仅仅是形成深沟槽电容器的一种方法,并且其他方法也完全旨在包括在实施例的范围内。
再次参照图1,第一金属化层105形成在第一衬底101上方并且设计为连接各个IPD103。在实施例中,第一金属化层105包括介电材料和导电材料的一层或多层并且可以通过任何合适的工艺(诸如合适的光刻掩模和蚀刻工艺、沉积、镶嵌、双镶嵌等)来形成第一金属化层。第一金属化层105中的导电材料可包括诸如铜的导电材料,但是可以使用诸如钨、铝或铜合金等的其他导电材料。
图2示出在第一衬底101中形成衬底贯通孔(TSV)201。例如,通过在第一金属化层105和第一衬底101中蚀刻开口并且然后在开口中沉积导电材料203来形成TSV 201。可使用合适的光刻掩模和蚀刻工艺在第一金属化层105和第一衬底101中形成开口。例如,可在第一金属化层105上方形成和图案化光刻胶,并且利用一种或多种蚀刻工艺(例如,湿蚀刻工艺或干蚀刻工艺)以去除TSV 201所期望的第一金属化层105和第一衬底101的那些部分。
一旦已经形成用于TSV 201的开口,可用例如阻挡层205和导电材料203填充用于TSV 201的开口。阻挡层205可以包括诸如氮化钛的导电材料,但是可以利用诸如氮化钽、钛、电介质等的其他材料。可以使用诸如PECVD的CVD工艺形成阻挡层205。然而,可以使用诸如溅射或金属有机化学汽相沉积(MOCVD)的其他可选工艺。可形成阻挡层205以与用于TSV201的开口的下面的形状一致。
导电材料203可以包括诸如铜、钨、其他导电金属等的一种或多种导电材料。例如,导电材料203的形成方法如下:沉积晶种层(未单独示出)并且使用电镀、化学镀等以在晶种层上沉积导电材料,填充且过填充用于TSV 201的开口。一旦已经填充用于TSV 201的开口,可通过诸如化学机械抛光(CMP)的研磨工艺去除用于TSV 201的开口的外部的多余的阻挡层205和多余的导电材料203,但是可以使用任何合适的去除工艺。在实施例中,TSV 201具有介于约5μm和约60μm之间(诸如约10μm)的宽度。本领域普通技术人员将意识到,上文中描述的用于形成TSV 201的工艺仅仅是形成TSV 201的一种方法,并且其他方法也完全旨在包括在实施例的范围内。
现参照图3,示出第一钝化层301、第二钝化层307、第三钝化层309、第一金属接触件305和连接端子311。可在TSV 201和IPD 103上方的第一金属化层105上形成第一钝化层301。第一钝化层301可以由诸如氧化硅、氮化硅、诸如碳掺杂的氧化物的低k电介质、诸如多孔碳掺杂的二氧化硅的极低k电介质、这些的组合等的一种或多种合适的介电材料制成。在一些实施例中,第一钝化层301可以是聚苯并恶唑(PBO),但是可以利用诸如聚酰亚胺或聚酰亚胺的衍生物的任何合适的材料。可以使用例如旋涂工艺将第一钝化层301放置为具有介于约5μm和约25μm之间(诸如约7μm)的厚度,但是可以使用任何合适的方法和厚度。在其他实施例中,可以通过诸如化学汽相沉积(CVD)的工艺形成第一钝化层301。
第一金属接触件305位于第一钝化层301中。第一金属接触件305通过第一金属化层105连接至TSV 201和IPD 103。第一金属接触件305可包括诸如铜的导电材料,但是可以使用诸如钨、铝或铜合金等的其他导电材料。可使用合适的光刻掩模和蚀刻工艺在第一钝化层301中形成开口。使用诸如沉积、镶嵌、双镶嵌或其他工艺的合适的工艺在第一钝化层301的开口中形成第一金属接触件305。在一些情况下,诸如第一金属接触件305、TSV 201、IPD 103的组件和本文描述的其他组件可以连接至其他组件,而不直接接触其他组件。例如,第一组件可以通过第三组件电连接或通信连接至第二组件,而不直接接触第二组件。
在其他实施例中,第一金属接触件305的形成方法如下:使用诸如溅射的沉积工艺以形成材料层(例如,铝或其他导电材料)并且然后可以通过合适的工艺(诸如光刻掩蔽和蚀刻)去除部分材料层以形成第一金属接触件305。然而,可以利用任何其他合适的工艺来形成第一金属接触件305。一旦形成第一金属接触件305,可在第一金属接触件305上方形成第一钝化层301。
在第一钝化层301和第一金属接触件305上方形成第二钝化层307以在后续的处理和环境中保护第一钝化层301和第一金属接触件305免受物理和环境的损坏。通过与第一钝化层301类似的工艺并且由类似的材料形成第二钝化层307,但是可由与第一钝化层301不同的材料形成第二钝化层307。在一些实施例中,例如,使用化学机械抛光(CMP)工艺平坦化第二钝化层307。
一旦在第一钝化层301和第一金属接触件305上方形成第二钝化层307,可形成穿过第二钝化层307的开口以暴露部分第一金属接触件305以用于进一步的连接。可以通过诸如合适的光刻掩模和蚀刻工艺的合适的掩模和去除工艺形成开口。然而,所讨论的公开的图案化工艺仅仅旨在作为代表性工艺,并且可以利用任何其他合适的图案化工艺以暴露部分第一金属接触件305。
一旦通过第二钝化层307暴露第一金属接触件305,可形成与穿过第二钝化层307的第一金属接触件305电接触的连接端子311。在一些实施例中,连接端子311包括诸如Al焊盘、AlCu焊盘或其他合适的材料的焊盘的一种或多种连接焊盘。在一些实施例中,连接端子311进一步包括凸块下金属件(UBM)。UBM可以包括诸如钛层、铜层和镍层的三层导电材料。然而,本领域的普通技术人员将意识到,存在诸如铬/铬铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置的材料和层的许多合适的布置,这些都适用于UBM的形成。UBM可使用的任何合适的材料或材料层完全旨在包括在当前发明的范围内。
可通过在第二钝化层307上方并且沿着穿过第二钝化层307的开口的内部形成连接端子311的每个子层来创建连接端子311。可使用诸如电镀的镀工艺实施每个子层的形成,但是可以依据所期望的材料使用诸如溅射、蒸发或PECVD工艺的其他形成工艺。
可在第一钝化层301、第二钝化层307和连接端子311上方形成第三钝化层309以在后续的处理和环境中保护第一钝化层301、第二钝化层307和连接端子311免受物理和环境的损坏。通过与第一钝化层301和第二钝化层307的类似的工艺并且由类似的材料形成第三钝化层309,但是可由与第一钝化层301和第二钝化层307不同的材料来形成第三钝化层309。
一旦在第一钝化层301和第二钝化层307和连接端子311上方形成第三钝化层309,可形成穿过第三钝化层309的开口以暴露部分连接端子311以用于进一步连接。通过诸如合适的光刻掩模和蚀刻工艺的合适的掩模和去除工艺形成开口。然而,所讨论的公开的图案化工艺仅仅旨在作为代表性工艺,并且可以利用任何其他合适的图案化工艺以暴露部分连接端子311。
现参照图4,示出保护涂层401、第一外部连接件403和焊球405。可以在第三钝化层309和连接端子311上形成保护涂层401。可以通过在第三钝化层309和连接端子311上涂覆诸如聚酰亚胺、聚苯并恶唑(PBO)或环氧树脂的绝缘材料来形成保护涂层401。可以通过诸如喷雾聚酰亚胺溶液、浸入聚酰亚胺溶液,旋涂或其他方法的任何合适的方法来形成保护涂层401。在其他实施例中,保护涂层401不是聚酰亚胺,而是诸如包括第一钝化层301、第二钝化层307和第三钝化层309的材料。
在实施例中,第一外部连接件403可以是导电柱并且通过首先在保护涂层401上方形成光刻胶(未示出)来形成。可以图案化光刻胶以暴露部分保护涂层401,第一外部连接件403将延伸穿过保护涂层401。一旦图案化,然后可以使用光刻胶作为掩模以去除保护涂层401的期望部分,形成开口,开口暴露将与第一外部连接件403接触的下面的连接端子311的那些部分。
可在保护涂层401和光刻胶两者的开口内形成第一外部连接403以提供至连接端子311的电连接。在实施例中,第一外部连接件403可以是例如,铜柱或铜杆。然而,实施例不限于这些,并且可以是焊料凸块、铜凸块或包括诸如铜、钨、其他导电金属等的一种或多种导电材料。可以制成其他合适的第一外部连接件403以提供电连接。所有这样的外部接触件旨在完全包括在本实施例的范围内。
可以通过例如沉积、电镀、化学镀等形成第一外部连接件403。一旦已经使用光刻胶形成第一外部连接件403,可使用合适的去除工艺去除光刻胶。在实施例中,使用等离子体灰化工艺去除光刻胶,由此,可以增大光刻胶的温度直到光刻胶经历热分解并且可以被去除。然而,可以可选地利用诸如湿剥离的任何其他合适的工艺。光刻胶的去除可暴露第一外部连接件403,从而使得第一外部连接件403突出于保护涂层401的表面。
在实施例中,可选的焊球405可以放置在第一外部连接件403上并且可以包括诸如焊料的共晶材料,但是可以可选地使用任何合适的材料。焊球405的形成方法如下:首先通过诸如蒸发、电镀、印刷、焊料转移的任何合适的方法形成锡层,并且然后实施回流以将材料成形为期望的凸块形状。在其他实施例中,可使用诸如直接球落工艺的球落方法来形成焊球405。
在这个阶段,可以实施电路探针测试以检查缺陷结构。在电路探针测试的实施例中,一个或多个探针(未示出)电连接至焊球405或第一外部连接件403并且将信号发送至第一外部连接件403和例如发送至IPD 103。如果不存在显著的缺陷,探针将接收来自第一外部连接件403的预定输出,并且可以识别缺陷结构和已知良好管芯(KGD)。可在进一步处理前识别缺陷结构和KGD以使整个过程更有效。例如,如下文参照图7至图15的描述,仅KGD可用于进一步处理。
现参照图5,示出载体衬底501和第一粘合层503。例如,载体衬底501包括诸如玻璃或氧化硅的硅基材料或诸如氧化铝的其他材料、这些材料的任何组合等。载体衬底501是平坦的以适合于诸如结合图1至图4描述和讨论的半导体器件的附接。
第一粘合层503放置在载体衬底501上以帮助粘合上面的结构(例如,保护涂层401、第一外部连接件403、焊球405)。在实施例中,第一粘合层503可以包括紫外胶,当其暴露于紫外光时,紫外胶失去其粘合性能。然而,也可以使用诸如压敏粘合剂、可辐射固化粘合剂、环氧树脂、这些的组合等其他类型的粘合剂。第一粘合层503可以以半液体或凝胶的形式放置到载体衬底501上,第一粘合层503在压力下容易变形。
图5也示出削薄第一衬底101以暴露用于进一步处理的TSV 201。可使用例如机械研磨或化学机械抛光(CMP)工艺实施削薄,通过利用化学蚀刻剂和研磨剂以反应和研磨掉第一衬底101,直到暴露TSV 201的导电材料203。以这种方式,TSV 201可以形成为具有介于约50μm和约200μm之间(诸如约100μm)的第一厚度。在实施例中,TSV 201具有介于约3:1和约10:1之间(诸如约5:1)的截面厚度:宽度高宽比。
虽然上文描述的CMP工艺表现为一个示例性实施例,但是其不旨在限制于该实施例。可以可选地使用任何其他合适的去除工艺以削薄第一衬底101。例如,可以利用一系列化学蚀刻。可以可选地利用该工艺和任何其他合适的工艺以削薄第一衬底101,并且所有这样的工艺旨在完全包括在实施例的范围内。可选地,削薄第一衬底101后,在第一衬底101内凹进TSV 201。在实施例中,可以利用对TSV 201的材料(例如,铜)具有选择性的蚀刻剂使用例如蚀刻工艺来凹进TSV 201。
现参照图6,示出第四钝化层601、第一再分布层(RDL)603、第五钝化层605和第二金属接触件607。可形成第一再分布层603和第二金属接触件607以互连TSV 201和外部半导体器件(下文参照图8至图15描述的实例)。在实施例中,使用与第一钝化层301、第二钝化层307和第三钝化层309类似的工艺和材料在第一衬底101上方形成第四钝化层601。可选地,可与第一钝化层301、第二钝化层307和第三钝化层309不同地形成第四钝化层601。在实施例中,削薄第四钝化层601以暴露TSV 201的导电材料203。例如,可以使用机械研磨或CMP工艺实施削薄。
在实施例中,可以通过首先使用诸如CVD或溅射的合适的形成工艺形成钛铜合金的晶种层(未示出)来形成第一再分布层603。然后可以形成光刻胶(也未示出)以覆盖晶种层,并且然后可以图案化光刻胶以暴露第一再分布层603期望定位的位置处的晶种层的那些部分。
一旦形成并图案化光刻胶,可以通过诸如镀的沉积工艺在晶种层上形成诸如铜的导电材料。然而,虽然讨论的材料和方法适用于形成导电材料,但是这些材料仅仅是示例性的。可以可选地使用诸如AlCu或Au的任何其他合适的材料和诸如CVD或PVD的任何其他合适的形成工艺来形成第一再分布层603。
一旦已经形成导电材料,可以通过诸如灰化的合适的去除工艺去除光刻胶。此外,去除光刻胶后,可以使用导电材料作为掩模通过例如合适的蚀刻工艺去除被光刻胶覆盖的晶种层的那些部分。
在实施例中,使用与第一钝化层301、第二钝化层307、第三钝化层309和第四钝化层601类似的工艺和材料在第一再分布层603上方形成第五钝化层605。可选地,可与第一钝化层301、第二钝化层307、第三钝化层309和第四钝化层601不同地形成第五钝化层605。在实施例中,例如,使用机械研磨或CMP工艺削薄第五钝化层605。
形成第一再分布层603后,可以通过去除部分第一再分布层603制造穿过第一再分布层603的开口以暴露下面的导电材料的至少一部分。可以使用合适的光刻掩模和蚀刻工艺来形成开口,但是可以可选地使用用于暴露部分第一再分布层603的任何合适的工艺。
可以在第一再分布层603上形成第二金属接触件607以形成至第一再分布层603的电连接。第二金属接触件607可以包括铝,但是可以可选地使用诸如铜的其他材料。第二金属接触件607的形成方法包括:使用诸如溅射的沉积工艺形成导电材料层并且然后可以通过合适的工艺(诸如光刻掩蔽和蚀刻)去除部分材料层以形成第二金属接触件607。然而,可以利用任何其他合适的工艺来形成第二金属接触件607。
现参照图7,示出框架701和第二粘合层703。第二粘合层703用于将第一再分布层603和第二金属接触件607附接至框架701以用于分割工艺。例如,框架701包括诸如玻璃或氧化硅的硅基材料或诸如氧化铝、金属、陶瓷、聚合物的其他材料,这些材料的任何组合等。在实施例中,第二粘合层703包括诸如环氧树脂、酚醛树脂、丙烯酸橡胶、硅胶填料或它们的组合的管芯附接膜(DAF),并且使用层压技术来施加。然而,可以可选地利用任何其他合适的可选材料和形成方法。
图7也示出第一互连结构711和第二互连结构713的分割705。在实施例中,可以通过使用锯片割穿第二粘合层703和上文中结合图1至图6描述的其它层(例如,第一衬底101、第一金属化层105等)来实施分割705,从而从另一互连结构分离了一个互连结构。
然而,本领域普通技术人员将意识到,利用锯片分割第一互连结构711和第二互连结构713仅仅是示例性实施例,并且不旨在限制本发明。可以可选地利用用于分割第一互连结构711和第二互连结构713的诸如一种或多种蚀刻的可选方法。可以可选地利用这些方法和任何其他合适的方法以分割第一互连结构711和第二互连结构713。
在一些实施例中,第一互连结构711和第二互连结构713可以合并入集成扇出叠层封装件(InFO-POP)中,下文中结合图8至图16讨论。现参照图8,示出载体衬底801和位于载体衬底801上方的第三粘合层803、聚合物层805和第一晶种层807。例如,载体衬底801包括诸如玻璃或氧化硅的硅基材料或诸如氧化铝的其他材料、这些材料的任何组合等。载体衬底801是平坦的以适合于诸如第一互连结构711、第二互连结构713以及第一半导体器件901和第二半导体器件1001(在图9中未示出,但是下文中结合图10至图15示出并讨论)的半导体器件的附接。
第三粘合层803放置在载体衬底801上以帮助上面的结构(例如,聚合物层805)的粘合。在实施例中,第三粘合层803可以包括紫外胶,当其暴露于紫外光时,紫外胶失去其粘合性能。然而,也可以使用诸如压敏粘合剂、可辐射固化粘合剂、环氧树脂、这些的组合等的其他类型的粘合剂。第三粘合层803可以以半液体或凝胶的形式放置到载体衬底801上,第三粘合层803在压力下容易变形。
聚合物层805放置在第三粘合层803上方并且一旦已附接第一半导体器件901和第二半导体器件1001,可利用聚合物层805以为例如第一半导体器件901和第二半导体器件1001提供保护。在实施例中,聚合物层805可以是聚苯并恶唑(PBO),但是可以可选地利用诸如聚酰亚胺或聚酰亚胺衍生物、阻焊剂(SR)或味之素构建膜(ABF)的任何合适的材料。可以使用例如旋涂工艺将聚合物层805放置成介于约2μm和约15μm之间(诸如5μm)的厚度,但是可以可选地利用任何合适的方法和厚度。
在聚合物层805上方形成第一晶种层807。在实施例中,第一晶种层807为半导体材料的薄层,其在后续处理步骤期间帮助形成较厚的层。第一晶种层807可以包括约厚的钛层和接着约厚的铜层。取决于所期望的材料,可使用诸如溅射、蒸发或PECVD工艺的工艺创建第一晶种层807。第一晶种层807可以形成为具有介于约0.3μm和约1μm之间(诸如约0.5μm)的厚度。
图8也示出了在第一晶种层807上方放置和图案化光刻胶809。在实施例中,可以使用例如旋涂技术在第一晶种层807上将光刻胶809放置成介于约50μm和约250μm之间(诸如约120μm)的高度。一旦放置在合适的位置,然后可通过将光刻胶809暴露于图案化的能量源(例如,图案化的光源)以引发化学反应,从而引发暴露于图案化的光源的光刻胶809的那些部分中的物理变化来图案化光刻胶809。然后依据所期望的图案,将显影剂施加于曝光的光刻胶809以利用物理变化并且选择性地去除光刻胶809的曝光部分或光刻胶809的未曝光部分。
在实施例中,在光刻胶809内形成的图案是用于通孔811的图案。以位于后续附接的器件(诸如第一半导体器件901和第二半导体器件1001)的不同侧上的这种布置来形成通孔811。然而,可以可选地利用通孔811的图案的任何合适的布置,诸如通孔811的图案定位为使得第一半导体器件901和第二半导体器件1001放置在通孔811的相对侧上。
在实施例中,在光刻胶809内形成通孔811。在实施例中,通孔811包括诸如铜、钨、其他导电金属等的一种或多种导电材料,并且可以通过例如电镀、化学镀等形成。在实施例中,使用电镀工艺,其中第一晶种层807和光刻胶809浸入或浸渍在电镀液中。第一晶种层807表面电连接至外部DC电源的负极侧,从而使得第一晶种层807在电镀工艺中用作阴极。诸如铜阳极的固体导电阳极也浸没在溶液中并且附接至电源的正极侧。来自阳极的原子溶解在溶液中,阴极(例如第一晶种层807)从溶液中获取溶解的原子,从而对光刻胶809的开口内的第一晶种层807的暴露导电区域进行镀工艺。
一旦已经使用光刻胶809和第一晶种层807形成通孔811,可使用合适的去除工艺(在图8中未示出,但在下文中的图10中可见)去除光刻胶809。在实施例中,可以使用等离子体灰化工艺去除光刻胶809,由此可以增加光刻胶809的温度,直到光刻胶809经历热分解并且可被去除。然而,可以可选地利用诸如湿剥离的任何其他合适的工艺。光刻胶809的去除可暴露下面的第一晶种层807的部分。
一旦暴露,可以实施第一晶种层807的暴露部分的去除(在图8中未示出,但在下文中的图10中可见)。在实施例中,可以通过例如湿蚀刻或干蚀刻工艺去除第一晶种层807的暴露部分(例如,未被通孔811覆盖的那些部分)。例如,在干蚀刻工艺中,使用通孔811作为掩模,可将反应剂导向第一晶种层807。在另一实施例中,蚀刻剂可以喷涂或以其它方式放置为与第一晶种层807接触以去除第一晶种层807的暴露部分。在已经蚀刻掉第一晶种层807的暴露部分后,在通孔811之间暴露部分聚合物层805。
图9示出将附接至通孔811内的聚合物层805(在图9中未示出,但是结合图10在下文中示出和描述)的第一半导体器件901。在实施例中,第一半导体器件901包括第三衬底903、第一有源器件(未单独示出)、第二金属化层905、第一接触焊盘907、第六钝化层911和第二外部连接件909。第三衬底903可以包括掺杂或未掺杂的块状硅、或绝缘体上硅(SOI)衬底的有源层。通常,SOI衬底包括诸如硅、锗、锗硅、SOI、绝缘体上锗硅(SGOI)或它们的组合的半导体材料层。可以使用包括多层衬底、梯度衬底或混合取向衬底的其他衬底。
第一有源器件包括诸如电容器、电阻器、电感器等各种有源器件和无源器件,其可用于产生为第一半导体器件901设计的期望的结构和功能需求。可使用任何合适的方法在第三衬底903内或第三衬底903上形成第一有源器件。
第二金属化层905形成在第三衬底903和第一有源器件上方并且设计为连接各个有源器件以形成功能电路。在实施例中,第二金属化层905由介电材料和导电材料的交替层形成并且可以通过任何适合的工艺(诸如沉积、镶嵌、双镶嵌等)形成。在实施例中,存在通过至少一个层间介电层(ILD)与第三衬底903分离的四个金属化层,但是第二金属化层905的精确数目取决于第一半导体器件901的设计。
第一接触焊盘907可以形成在第二金属化层905上方并且与第二金属化层905电接触。第一接触焊盘907可包括铝,但是可以可选地使用诸如铜的其他材料。第一接触焊盘907的形成方法如下:可以使用诸如溅射的沉积工艺形成材料层(未示出)并且然后可以通过合适的工艺(诸如光刻掩模和蚀刻)去除部分材料层以形成第一接触焊盘907。然而,可以利用任何其他合适的工艺形成第一接触焊盘907。第一接触焊盘907可以形成为具有介于约0.5μm和约4μm之间(诸如约1.45μm)的厚度。
在第三衬底903上且在第二金属层905和第一接触焊盘907上方形成第六钝化层911。可以由诸如氧化硅、氮化硅、诸如碳掺杂的氧化物的低k电介质、诸如多孔碳掺杂的二氧化硅的极低k电介质、这些的组合等的一种或多种合适的介电材料制成第六钝化层911。可以通过诸如化学汽相沉积(CVD)的工艺形成第六钝化层911,但是可以利用任何合适的工艺,并且第六钝化层911可以具有介于约0.5μm和约5μm之间(诸如约 )的厚度。
可以形成第二外部连接件909以在第一接触焊盘907和例如第二再分布层1201(在图9中未示出,但是结合图12在下文中示出和描述)之间提供用于接触的导电区。在实施例中,第二外部连接件909可以是导电柱并且可以通过首先在第六钝化层911上方形成介于约5μm至约20μm之间(诸如约10μm)的厚度的光刻胶(未示出)来形成。可以图案化光刻胶以暴露部分第一钝化层,导电柱将延伸穿过第一钝化层。一旦图案化,然后可使用光刻胶作为掩模以去除第六钝化层911的期望部分,从而暴露将与第二外部连接件909接触的下面的第一接触焊盘907的那些部分。
可以在第六钝化层911和光刻胶的开口内形成第二外部连接件909。第二外部连接件909可以由诸如铜的导电材料形成,但是也可以使用诸如镍、金或金属合金、这些的组合等的其他导电材料。此外,可以使用诸如电镀的工艺来形成第二外部连接件909,通过电镀,电流流过第一接触焊盘907的期望形成第一外部连接件909的导电部分,并且第一接触焊盘907浸渍在溶液中。溶液和电流将例如铜沉积在开口内以填充和/或过填充光刻胶和第六钝化层911的开口,从而形成第二外部连接件909。然后,可以使用例如灰化工艺、化学机械抛光(CMP)工艺、它们的组合等去除位于第六钝化层911的开口的外部的过量的导电材料和光刻胶。
然而,本领域普通技术人员任何将意识到,上述形成第二外部连接件909的工艺仅仅是一种这样的描述,而不旨在将实施例限于这种精确的工艺。相反,所描述的工艺旨在仅是说明性的,并且可以可选地利用形成第二外部连接件909的任何合适的工艺。所有合适的工艺旨在完全包括在本发明的范围内。
可以在与第二金属化层905相对的第三衬底903的一侧上形成管芯附接膜(DAF)913以帮助将第一半导体器件901附接至聚合物层805。在实施例中,管芯附接膜是环氧树脂、酚醛树脂、丙烯酸橡胶、硅胶填料或它们的组合,并且使用层压技术来施加。然而,可以可选地利用任何其他合适的可选材料及形成方法。
图10示出在聚合物层805上放置第一互连结构711、第二互连结构713、第一半导体器件901和第二半导体器件1001。在实施例中,第二半导体器件1001可以包括第四衬底1003、第二有源器件(未单独示出)、第三金属化层1005、第二接触焊盘1007、第七钝化层1011和第二管芯附接膜(DAF)1013和第三外部连接件1009。在实施例中,第四衬底1003、第二有源器件(未单独示出)、第三金属化层1005、第二接触焊盘1007、第七钝化层1011和第三外部连接件1009可以类似于第三衬底903、第一有源器件、第二金属化层905、第一接触焊盘907、第六钝化层911和第二外部连接件909,但是它们也可以不同。
在实施例中,可以使用例如拾取和放置工艺将第一互连结构711、第二互连结构713、第一半导体器件901和第二半导体器件1001放置在聚合物层805上。然而,可以使用放置第一互连结构711、第二互连结构713、第一半导体器件901和第二半导体器件1001的任何其他可选方法。
图11示出通孔811、第一半导体器件901和第二半导体器件1001的密封。可在模制器件(未在图11中单独示出)中实施密封,模制器件可以包括顶部模制部分和与顶部模制部分分离开的底部模制部分。当顶部模制部分降低到与底部模制部分相邻时,可形成用于载体衬底801、通孔713、第一互连结构711、第二互连结构713、第一半导体结构901和第二半导体器件1001的模制腔。
在密封工艺期间,顶部模制部分可以放置为与底部模制部分相邻,从而将载体衬底801、通孔811、第一半导体器件901和第二半导体器件1001封闭在模制腔内。一旦封闭,顶部模制部分和底部模制部分可形成气密密封以控制气体从模制腔的流入和流出。一旦密封,密封剂1101可以放置在模制腔内。密封剂1101可以是诸如聚酰亚胺、PPS、PEEK、PES、耐热晶体树脂、它们的组合等的模塑料树脂。可以在顶部模制部分和底部模制部分对准前,将密封剂1101放置于模制腔内,或者可以通过注入端口将密封剂注入模制腔。
可以将密封剂1101放置在模制腔内,从而使得密封剂1101密封载体801、通孔811、第一互连结构711、第二互连结构713、第一半导体结构901和第二半导体器件1001。例如,密封剂1101可以围绕通孔811,直接接触通孔811的导电材料和/或存在于通孔811的表面上的氧化的导电材料。一旦密封剂1101放置在模制腔内,可以固化密封剂1101以硬化密封剂1101用于最佳保护。虽然精确的固化工艺至少部分取决于选择用于密封剂1101的特定材料,在模塑料选择作为密封剂1101的实施例中,可以通过诸如将密封剂1101加热至约100℃至约130℃之间(诸如约125℃)的温度并且持续约60秒至约3000秒(诸如约600秒)的工艺进行这种固化。此外,引发剂和/或催化剂可以包括在密封剂1101内以更好地控制固化工艺。
然而,本领域普通技术人员将意识到,上述固化工艺仅仅是示例性工艺并且不旨在限制当前的实施例。可以可选地使用诸如照射或甚至允许密封剂1101在环境温度下硬化的其他固化工艺。可以使用任何合适的固化工艺,并且所有这样的工艺旨在完全包括在本文所讨论的实施例的范围内。
图11也示出削薄密封剂1101以暴露通孔811、第一互连结构711、第二互连结构713、第一半导体器件901和第二半导体器件1001以用于进一步处理。例如,可使用机械研磨或化学机械抛光(CMP)工艺来实施削薄,从而利用化学蚀刻剂和研磨剂以反应和研磨掉密封剂1101、第一半导体器件901和第二半导体器件1001,直到暴露通孔811、第二外部连接件909(位于第一半导体器件901上),第三外部连接件1009(位于第二半导体器件1001上)和(可选)焊球405或第一外部连接件403(位于第一互连结构711和第二互连结构713上)。因此,第一半导体器件901、第二半导体器件1001、第一互连结构711、第二互连结构713和通孔811可以具有与密封剂1101在同一平面上的平坦的表面。
然而,虽然上述的CMP工艺表现为一个示例性实施例,但是其不旨在限制于该实施例。可以可选地使用任何其他合适的去除工艺以削薄密封剂1101、第一半导体器件901和第二半导体器件1001。例如,可以利用一系列化学蚀刻。可以可选地利用该工艺和任何其他合适的工艺以削薄密封剂1101、第一半导体器件901和第二半导体器件1001,并且所有这样的工艺旨在完全包括在实施例的范围内。
图12示出形成互连第一半导体器件901、第二半导体器件1001、通孔811、第一互连结构711、第二互连结构713和第四外部连接件1221的第二再分布层(RDL)1201、第三再分布层1205和第四再分布层1209的截面图。图12也示出形成位于密封剂1101、第一半导体器件901、第二半导体器件1001、通孔811、第一互连结构711和第二互连结构713上方的第八钝化层1203以为其他下面的结构提供保护和隔离。在实施例中,第八钝化层1203可以是聚苯并恶唑(PBO),但是可以可选地利用诸如聚酰亚胺或聚酰亚胺的衍生物的任何合适的材料。可以使用例如旋涂工艺将第八钝化层1203放置为介于约5μm至约25μm之间(诸如约7μm)的厚度,但是可以可选地使用任何合适的方法和厚度。
形成第八钝化层1203后,可以通过去除部分第八钝化层1203,制造穿过第八钝化层1203的第一开口1204(为了简洁,仅在图12中示出其中的一个)以暴露下面的第二外部连接件909(位于第一半导体器件901上)、第三外部连接件1009(位于第二半导体器件1001)上和(可选)焊球或第一外部连接件403(位于第一互连结构711和第二互连结构713上)的至少一部分。第一开口1204允许第二再分布层1201和下面的结构之间接触。可使用合适的光刻掩模和蚀刻工艺来形成第一开口1204,但是也可以使用任何合适的工艺以暴露下面的结构。
在实施例中,可以通过首先使用诸如CVD或溅射的合适的形成工艺形成钛铜合金的晶种层(未示出)来形成第二再分布层1201。然后可以形成光刻胶(也未示出)以覆盖晶种层,并且然后可以图案化光刻胶以暴露位于第二再分布层1201期望定位的位置处的晶种层的那些部分。
一旦形成并图案化光刻胶,可以通过诸如镀的沉积工艺在晶种层上形成诸如铜的导电材料。导电材料可以形成为具有约1μm至约10μm之间(诸如约5μm)的厚度。然而,虽然讨论的材料和方法适用于形成导电材料,但是这些材料仅仅是示例性的。可以可选地使用诸如AlCu或Au的任何其他合适的材料和诸如CVD或PVD的任何其他合适的形成工艺来形成第二再分布层1201。
一旦形成导电材料,可以通过诸如灰化的合适的去除工艺去除光刻胶。此外,在去除光刻胶之后,可以使用导电材料作为掩模通过例如合适的蚀刻工艺去除被光刻胶覆盖的晶种层的那些部分。
图12也示出在第二再分布层1201上方形成第九钝化层1207以为第二再分布层1201和其他下面的结构提供保护和隔离。在实施例中,第九钝化层1207可以是聚苯并恶唑(PBO),但是可以可选地利用诸如聚酰亚胺或聚酰亚胺的衍生物的任何合适的材料。可以使用例如旋涂工艺将第九钝化层1207放置成介于约5μm至约25μm之间(诸如约7μm)的厚度,但是可以可选地使用任何合适的方法和厚度。
形成第九钝化层1207后,可以通过去除部分第九钝化层1207制造穿过第九钝化层1207的第二开口1206(为了简洁,仅在图12中示出其中的一个)以暴露下面的第二再分布层1201的至少一部分。第二开口1206允许第二再分布层1201和第三再分布层1205(下文中进一步描述)之间接触。可使用合适的光刻掩模和蚀刻工艺来形成第二开口1206,但是可以可选地使用任何合适的工艺以暴露部分第二再分布层1201。
形成第三再分布层1205以提供额外的布线和连接性并且与第二再分布层1201电连接。在实施例中,可以形成类似于第二再分布层1201的第三再分布层1205。例如,可以形成晶种层,可以在晶种层的顶部上放置和图案化光刻胶,并且可以将导电材料镀入穿过光刻胶的图案化的开口。一旦形成,可以去除光刻胶,可以蚀刻下面的晶种层,第十钝化层1211(其可以类似于第九钝化层1207)覆盖第三再分布层1205,并且可以图案化第十钝化层1211以形成第三开口1208(为了简洁,仅示出其中的一个)并且暴露下面的第三再分布层1205的导电部分。
可以形成第四再分布层1209以提供额外的布线以及第三再分布层1205和第四外部连接件1221之间的电连接。在实施例中,可以使用与第二再分布层1201类似的材料和工艺形成第四再分布层1209。例如,可以形成晶种层,可以在晶种层的顶部上放置光刻胶,并且以第四再分布层1209的期望的图案图案化光刻胶,将导电材料镀入在光刻胶的图案化开口,去除光刻胶并且蚀刻晶种层。
现转向图12和图13,形成第四再分布层1209后,可以在第四再分布层1209上方形成第十一钝化层1213以保护第四再分布层1209和其他下面的结构。在实施例中,第十一钝化层1213类似于第八钝化层1203,可由诸如PBO的聚合物形成,或由与第八钝化层1203类似的材料(例如,聚酰亚胺或聚酰亚胺衍生物)形成。第十一钝化层1213可以形成为具有介于约2μm和约15μm之间(诸如约5μm)的厚度。
形成第十一钝化层1213后,可以通过去除部分第十一钝化层1213制造穿过第十一钝化层1213的开口以暴露下面的第四再分布层1209的至少一部分。开口允许第四再分布层1209和第二UBM 1219之间的接触。可以使用合适的光刻掩模和蚀刻工艺来形成开口,但是可以可选地使用任何合适的工艺以暴露部分第四再分布层1209。
一旦通过第十一钝化层1213暴露第四再分布层1209,可形成与第十一钝化层1213电接触的第二UBM 1219。第二UBM 1219可以包括诸如钛层、铜层和镍层的三层导电材料。然而,本领域的普通技术人员将意识到,存在诸如铬/铬铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置的材料和层的许多合适的布置,这些都适用于形成第二UBM1219。可以用于第二UBM 1219的任何合适的材料或材料层旨在完全包括在当前发明的范围内。
可以通过在第十一钝化层1213上方且沿着穿过第十一钝化层1213的开口的内部形成各层来创建第二UBM 1219。可以使用诸如电镀的镀工艺实施各层的形成,但是可以依据所期望的材料可选地使用诸如溅射、蒸发或PECVD工艺的其他形成工艺。第二UBM 1219可以形成为具有介于约0.7μm和约10μm(诸如5μm)的厚度。一旦形成期望的层,然后可以通过合适的光刻掩模和蚀刻工艺去除部分层以去除期望的材料并且以期望的形状(诸如圆形、八边形、正方形或矩形形状)留下第二UBM 1219,但是可以可选地形成任何期望的形状。
第四外部连接件1221可用于提供电连接至第四再分布层1209的外部连接点并且可以是例如接触凸块,但是可以利用任何合适的连接。在第四外部连接件1221是接触凸块的实施例中,第四外部连接件1221可包括诸如锡的材料或诸如银、无铅的锡或铜的其他合适的材料。在第四外部连接件1221是锡焊料凸块的实施例中,可以通过首先使用诸如蒸发、电镀、印刷、焊料转移、球放置等的这样常用的方法来形成例如厚度为约100μm的锡层来形成第四外部连接件1221。一旦在结构上形成锡层,可以实施回流,以将材料成形为期望的凸块形状。
图13示出载体衬底801与第一互连结构711、第二互连结构713、第一半导体器件901和第二半导体器件1001的脱粘。在实施例中,第四外部连接件1221可以附接至环结构1301,并且因此包括第一互连结构711、第二互连结构713、第一半导体器件901和第二半导体器件1001的结构可以附接至环结构1301。环结构1301可以是在脱粘工艺期间和之后旨在为该结构提供支撑和稳定性的金属环。在实施例中,例如,使用紫外线胶带1303将第四外部连接件1221、第一互连结构711、第二互连结构713、第一半导体器件901和第二半导体器件1001附接至环结构1301,但是可以可选地使用任何其他合适的粘合剂或附接件。
一旦第四外部连接件1221附接至环结构1301,并且因此包括第一互连结构711、第二互连结构713、第一半导体器件901和第二半导体器件1001的结构附接至环结构1301,可以使用例如热工艺来改变第三粘合层803的粘合性能而使载体衬底801与包括第一互连结构711、第二互连结构713、第一半导体器件901和第二半导体器件1001的结构脱粘。在特定实施例中,利用诸如紫外线(UV)激光、二氧化碳(CO2)激光或红外线(IR)激光的能量源来照射和加热第三粘合层803,直到第三粘合层803失去它的至少一些粘合性能。一旦实施,载体衬底801和第三粘合层803可以物理分离并且从包括第四外部连接件1221、第一互连结构711、第二互连结构713、第一半导体器件901和第二半导体器件1001的结构去除。
图13额外地示出图案化聚合物层805以暴露通孔811(与相关的第一晶种层807)、第一互连结构711和第二互连结构713。在实施例中,例如,可使用激光钻孔方法图案化聚合物层805。在这样的方法中,首先在聚合物层805上方沉积诸如光热转换(LTHC)层或水溶性保护膜层(在图13中未单独示出)的保护层。一旦保护,将激光导向聚合物层805的期望被去除的那些部分以暴露下面的通孔811、第一互连结构711和第二互连结构713。在激光钻孔工艺期间,钻孔能量可以在从0.1mJ至约30mJ的范围内,并且相对于聚合物层805的法线的钻孔角度在约0度(垂直于聚合物层805)至约85度之间。在实施例中,可以实施图案化以在通孔811上方形成第四开口1305,第四开口1305具有介于约100μm和约300μm之间(诸如约200μm)的宽度。
在另一实施例中,通过首先对聚合物层805施加光刻胶(在图13中未单独示出)并且然后将光刻胶暴露于图案化的能量源(例如,图案化的光源)以引发化学反应,从而引发暴露于图案化的光源的光刻胶的那些部分中的物理变化来图案化聚合物层805。然后依据所期望的图案,将显影剂施加于曝光的光刻胶以利用物理变化并且选择性地去除光刻胶的曝光部分或光刻胶的未曝光部分。并且例如,通过干蚀刻工艺去除聚合物层805的下面的暴露部分。然而,可以利用任何其他合适的方法图案化聚合物层805。
图14示出在第四开口1305内放置背侧球焊盘1401以保护现在暴露的通孔811和第二金属接触件607。在实施例中,背侧球焊盘1401可以包括诸如膏上焊料或氧焊料保护(OSP)的导电材料,但是可以可选地利用任何合适的材料。在实施例中,可以使用模板来应用背侧球焊盘1401,但是可以可选地利用任何合适的施加方法,并且然后回流以形成凸块形状。
图14也示出位于背侧球焊盘1401上方的背侧保护层1403的放置和图案化,背侧保护层1403有效地密封背侧球焊盘1401和通孔811之间的接合点免受湿气的入侵。在实施例中,背侧保护层1403可以是诸如PBO、阻焊剂(SR)、层压复合(LC)胶带、味之素构建膜(ABF)、非导电膏(NCP)、非导电膜(NCF)、图案化的底部填充物(PUF)、翘曲改进粘合剂(WIA)、液体模塑料V9、这些的组合等的保护材料。然而,也可以使用任何适合的材料。可以使用诸如丝网印刷、层压、旋涂等的工艺施加介于约1μm至约200μm之间的厚度的背侧保护层1403。
图14也示出,一旦已经放置背侧保护层1403,可以图案化背侧保护层1403以暴露背侧球焊盘1401。在实施例中,例如,可以使用激光钻孔方法图案化背侧保护层1403,通过激光钻孔方法,将激光导向背侧保护层1403的期望被去除的那些部分以暴露背侧球焊盘1401。在激光钻孔工艺期间,钻孔能量可以在从0.1mJ至约30mJ的范围内,并且相对于背侧保护层1403的法线的钻孔角度在约0度(垂直于背侧保护层1403)至约85度之间。在实施例中,该暴露可以形成具有介于约30μm和约300μm之间(诸如约150μm)的直径的开口。
在另一实施例中,可以通过首先对背侧保护层1403施加光刻胶(未单独在图14中示出)并且然后将光刻胶暴露于图案化的能量源(例如,图案化的光源)以引发化学反应,从而引发暴露于图案化的光源的光刻胶的那些部分中的物理变化来图案化背侧保护层1403。然后依据所期望的图案,将显影剂施加于曝光的光刻胶以利用物理变化并且选择性地去除光刻胶的曝光部分或光刻胶的未曝光部分,并且例如,通过干蚀刻工艺去除下面的背侧保护层1403的暴露部分。然而,可以利用任何其他合适的方法图案化背侧保护层1403。
图14也示出背侧球焊盘1401至第一封装件1400的接合。在实施例中,第一封装件1400可包括第五衬底1405、第三半导体器件1407、第四半导体器件1409(接合至第三半导体器件1407)、第三接触焊盘1411、第二密封剂1413和第五外部连接件1415。在实施例中,第五衬底1405可以是例如封装衬底,封装衬底包括内部互连件(例如,衬底贯通孔1417)以将第三半导体器件1407和第四半导体器件1409连接至背侧球焊盘1401。
可选地,第五衬底1405可以是用作中间衬底以将第三半导体器件1407和第四半导体器件1409连接至背侧球焊盘1401的中介板。在这个实施例中,第五衬底1405可以是例如掺杂或未掺杂的硅衬底或者绝缘体上硅(SOI)衬底的有源层。然而,第五衬底1405可以可选地为玻璃衬底、陶瓷衬底、聚合物衬底、或可以提供合适的保护和/或互连功能的任何其他衬底。这些和任何其他合适的材料可以可选地用于第五衬底1405。
第三半导体器件1407可以是设计为诸如存储器管芯(例如,DRAM管芯)、逻辑管芯、中央处理单元(CPU)管芯、这些的组合等的用于预期目的的半导体器件。在实施例中,第三半导体器件1407中包括所期望用于特定功能的诸如晶体管、电容器、电感器、电阻器、第一金属化层(未示出)等的集成电路器件。在实施例中,第三半导体器件1407设计和制造为与第一半导体器件901一起或同时工作。
第四半导体器件1409可以类似于第三半导体器件1407。例如,第四半导体器件1409可以是设计为预期目的(例如,DRAM管芯)并且包括用于期望功能的集成电路器件的半导体器件。在实施例中,第四半导体器件1409设计为与第一半导体器件901和/或第三半导体器件1407一起或同时工作。
第四半导体器件1409可以接合至第三半导体器件1407。在实施例中,第四半导体器件1409与第三半导体器件1407仅物理接合,诸如通过使用粘合剂。在这个实施例中,第四半导体器件1409和第三半导体器件1407可以使用例如引线接合件1419电连接至第五衬底1405,但是可以可选地利用任何合适的电接合。
可选地,第四半导体器件1409可以物理地接合且电接合至第三半导体器件1407。在这个实施例中,第四半导体器件1409可以包括与第三半导体器件1407上的第七外部连接件(未在图14中单独示出)连接的第六外部连接件(也未在图14中单独示出)以将第四半导体器件1409与第三半导体器件1407互连。
可以在第五衬底1405上形成第三接触焊盘1411以在第三半导体器件1407和例如第五外部连接件1415之间形成电连接。在实施例中,第三接触焊盘1411可以形成在第五衬底1405上方并且与第五衬底1405内的电布线(诸如衬底贯通孔1417)电接触。第三接触焊盘1411可以包括铝,但是可以可选地使用诸如铜的其他材料。第三接触焊盘1411的形成方法如下:使用诸如溅射的沉积工艺以形成材料(未示出)层并且然后可以通过合适的工艺(诸如光刻掩模和蚀刻)去除部分材料层以形成第三接触焊盘1411。然而,可以利用任何其他合适的工艺以形成第三接触焊盘1411。第三接触焊盘1411可以形成为具有介于约0.5μm和约4μm之间(诸如约1.45μm)的厚度。
第二密封剂1413可以用于密封和保护第三半导体器件1407、第四半导体器件1409和第五衬底1405。在实施例中,第二密封剂1413可以是模塑料并且可以使用模制器件(未在图14中示出)来放置。例如,可以将第五衬底1405、第三半导体器件1407和第四半导体器件1409放置在模制器件的腔体内,并且腔体可以气密地密封。在气密地密封腔体之前将第二密封剂1413放置在腔体内或者通过注入端口将第二密封剂1011注入腔体内。在实施例中,第二密封剂1413可以是诸如聚酰亚胺、PPS、PEEK、PES、耐热晶体树脂、这些的组合等的模塑料树脂。
一旦第二密封剂1413放置在腔体内,从而使得第二密封剂1413密封第五衬底1405、第三半导体器件1407和第四半导体器件1409周围的区域,可以固化第二密封剂1413以硬化第二密封剂1413以用于最佳保护。虽然精确的固化工艺至少部分取决于选择用于第二密封剂1413的特定材料,在将模塑料选择作为第二密封剂1413的实施例中,可以通过诸如将第二密封剂1413加热至约100℃至约130℃之间的温度(诸如约125℃),并且持续约60秒至约3000秒(诸如约600秒)的工艺进行这种固化。此外,引发剂和/或催化剂可以包括在第二密封剂1413内以更好地控制固化工艺。
然而,本领域普通技术人员将意识到,上述固化工艺仅仅是示例性工艺并且不旨在限制当前的实施例。可以可选地使用诸如照射或甚至允许第二密封剂1413在环境温度下硬化的其他固化工艺。可以使用任何合适的固化工艺,并且所有这样的工艺预期完全包括在本文所讨论的实施例的范围内。
在实施例中,可以形成第五外部连接件1415以提供第五衬底1405和例如背侧球焊盘1401之间的外部连接。第五外部连接件1415可以是诸如微凸块或可控塌陷芯片连接(C4)凸块的接触凸块并且可以包括诸如锡的材料、或者诸如银或铜的其他合适的材料。在第五外部连接件1415为锡焊料凸块的实施例中,可以首先通过诸如蒸发、电镀、印刷、焊料转移、球放置等的任何合适的方法形成厚度为例如约100μm的锡层来形成第五外部连接件1415。一旦在结构上形成锡层,实施回流以将材料成形为期望的凸块形状。
一旦已经形成第五外部连接件1415,第五外部连接件1415与背侧球焊盘1401对准且放置为与背侧球焊盘1401物理接触,并且实施接合。例如,在第五外部连接件1415是焊料凸块的实施例中,接合工艺可以包括回流工艺,从而第五外部连接件1415的温度升高至第五外部连接件1415将液化并且流动的点,因此一旦第五外部连接件1415重新固化时,可将第一封装件1400接合至背侧球焊盘1401。
图14额外地示出将第二封装件1421接合至背侧球焊盘1401。在实施例中,第二封装件1421类似于第一封装件1400,并且可以利用类似的工艺接合至背侧球焊盘1401。然而,第二封装件1421也可以不同于第一封装件1400。如图14所示,第一封装件1400可以通过通孔811和第一互连结构711中的TSV 201电连接至第二再分布层1201。同样地,第二封装件1421可以通过通孔811和第二互连结构713中的TSV 201电连接至第二再分布层1201。
图15示出第四外部连接件1221从环结构1301的脱粘并且分割结构以形成集成扇出叠层封装(InFO-POP)结构1500。在实施例中,可以通过首先使用例如第二紫外线胶带将第一封装件1400和第二封装件1421接合至第二环结构来将第四外部连接件1221从环结构1301脱粘。一旦接合,可以利用紫外线辐射来照射紫外线胶带1303,一旦紫外线胶带1303失去其粘合性能,第四外部连接件1221可以与环结构1301物理地分离。
一旦脱粘,实施结构的分割以形成InFO-POP结构1500。在实施例中,可以通过使用锯片(未示出)来切穿通孔811之间的密封剂1101和聚合物层805来实施分割,从而将一部分与另一部分分离以形成具有第一半导体器件901的InFO-POP结构1500。然而,本领域普通技术人员将意识到,利用锯片分割InFO-POP结构1500仅仅是一个示例性实施例,并且不旨在限制本发明。可以可选地利用诸如利用一种或多种蚀刻以分离InFO-POP结构1500的分割InFO-POP结构1500的可选方法。可以可选地利用这些方法和任何其他合适的方法以分割InFO-POP结构1500。
图16示出通过图15所示的穿过A-A’的InFO-POP结构1500的实例的截面图。如图16所示,第一半导体器件901被通孔811、第一互连结构711、第三互连结构1601和第四互连结构1603围绕。图16示出包括三个互连结构的InFO-POP结构1500,但是在其他实施例中,InFO-POP结构1500包括其他数量的互连结构(例如,一个互连结构、两个互连结构、五个互连结构、或其他数量的互连结构)。在实施例中,第三互连结构1601和第四互连结构1603类似于第一互连结构711并且可以利用类似的工艺形成且合并入InFO-POP结构1500中。然而,第三互连结构1601和第四互连结构1603也可以不同于第一互连结构711。例如,第一互连结构711、第三互连结构1601和第四互连结构1603可以具有不同的尺寸、不同的形状、不同的布置、不同的数量、或不同的IPD类型、TSV 201的不同布置和数量或在其他方面上的不同。在实施例中,第一互连结构711、第三互连结构1601和第四互连结构1603邻近第一半导体器件901和InFO-POP结构1500的边缘之间的通孔811。在实施例中,通孔811形成围绕第一半导体器件901的通孔811的“环”,并且第一互连结构711、第三互连结构1601和第四互连结构1603可以设置在“环”中。在实施例中,第一互连结构711、第三互连结构1601和第四互连结构1603可用于替代InFO-POP结构1500中的通孔811。图16示出,在实施例中,第一互连结构711的TSV 201、第三互连结构1601和第四互连结构1603可以具有比InFO-POP结构1500的通孔811更小的宽度和/或更大的密度。
本文所公开的互连结构可以是嵌入式双侧IPD(eDS-IPD)。通过在同一结构中合并集成无源器件(IPD)和衬底贯通孔(TSV),互连结构(例如,eDS-IPD)可用作IPD器件和位于半导体器件(例如,第一半导体器件901)与封装件(例如,第一封装件1400)之间的互连路径。例如,互连结构可以同时用作IPD和位于半导体器件和DRAM之间的互连路径。互连结构(例如,第一互连结构711)可替代InFO-POP结构(例如,InFO-POP结构1500)中的通孔(例如,通孔811)以增强布线的灵活性并且节约损失面积。例如,定位具有通孔的互连结构可以减少用于并排放置的IPD和半导体器件的面积。由于较小的路径电感,互连结构也可以提供更好的电容性能。
在实施例中,半导体器件包括再分布层(RDL)和设置在RDL上的管芯。半导体器件还包括位于顶衬底和RDL之间并且连接顶衬底和RDL的第一组贯通孔,第一组贯通孔与模塑料物理地接触并且通过模塑料与管芯分离。半导体器件还包括位于顶衬底和RDL之间并且连接顶衬底和RDL的第一互连结构,第一互连结构通过模塑料与管芯和第一组贯通孔分离。第一互连结构包括至少一个无源器件和位于第一互连结构内的第二组贯通孔。
在上述半导体器件中,其中,所述至少一个无源器件是沟槽电容器。
在上述半导体器件中,其中,所述无源器件包括位于所述第二组贯通孔上方的导电柱。
在上述半导体器件中,其中,所述无源器件包括位于所述第二组贯通孔上方的导电柱,所述导电柱与所述模塑料物理接触。
在上述半导体器件中,其中,所述第一互连结构还包括金属化层,并且其中,所述至少一个无源器件通过所述金属化层连接至所述管芯。
在上述半导体器件中,还包括位于所述顶衬底和所述再分布层之间并且连接所述顶衬底和所述再分布层的第二互连结构,所述第二互连结构通过所述模塑料与所述管芯、所述第一互连结构和所述第一组贯通孔分离。
在上述半导体器件中,其中,所述第一组贯通孔围绕所述管芯,并且所述第一互连结构设置在所述第一组贯通孔内。
在上述半导体器件中,还包括顶封装件,设置在所述管芯和所述第一互连结构上方。
在其他实施例中,半导体器件包括位于封装件和再分布层(RDL)之间的层。该层包括连接至RDL的半导体管芯。半导体管芯的第一侧连接至RDL,并且半导体管芯的第二侧通过粘合层附接至聚合物层。该层还包括从该层的第一侧延伸至该层的第二侧的至少一个第一通孔、第一无源器件结构和第二无源器件结构。第一无源器件结构包括至少一个无源器件和设置在第一无源器件结构内的至少一个第二通孔。第二无源器件结构包括至少一个无源器件和设置在第二无源器件内的至少一个第三通孔。该半导体器件还包括围绕半导体管芯、至少一个第一通孔、第一无源器件结构和第二无源器件结构的模塑料,其中第一无源器件结构通过模塑料与至少一个第一通孔和第二无源器件结构分离,并且其中至少一个第一通孔从模塑料的第一侧延伸至模塑料的第二侧。至少一个第一通孔、至少一个第二通孔和至少一个第三通孔连接RDL和封装件,其中至少一个第二通孔和至少一个第三通孔是衬底贯通孔(TSV)。
在上述半导体器件中,还包括第三无源器件结构。
在上述半导体器件中,其中,所述至少一个第二通孔具有从3:1至10:1的高宽比。
在上述半导体器件中,其中,所述至少一个第一通孔具有比所述至少一个第二通孔更大的宽度。
在上述半导体器件中,其中,所述至少一个第二通孔通过再分布层连接至所述封装件。
在上述半导体器件中,其中,所述至少一个第二通孔通过金属化层连接至所述再分布层。
在上述半导体器件中,其中,所述半导体管芯通过所述再分布层连接至所述第一无源器件结构的所述至少一个无源器件。
在另一实施例中,提供了一种制造半导体器件的方法。该方法包括在再分布层(RDL)上形成一组通孔,在RDL上放置与一组通孔分离的管芯,并且在RDL上放置第一互连结构。第一互连结构与管芯和通孔分离,并且第一互连结构包括衬底、从衬底的一侧延伸到衬底的第二侧的至少一个导电元件和至少一个集成无源器件。该方法还包括将该组通孔、管芯和第一互连结构密封在密封剂中,其中,密封剂与该组通孔、管芯和第一互连结构物理地接触,并且平坦化该组通孔、管芯和第一互连结构。
在上述方法中,其中,在所述再分布层上放置所述第一互连结构包括拾取和放置工艺。
在上述方法中,还包括在所述一组通孔、所述管芯和所述第一互连结构上方放置顶封装件,其中,所述顶封装件连接至所述一组通孔和所述第一互连结构。
在上述方法中,还包括在所述再分布层上放置第二互连结构。
在上述方法中,其中,所述至少一个集成无源器件是沟槽电容器。
上面概述了若干实施例的特征,使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,在此他们可以做出多种变化、替换以及改变。
Claims (1)
1.一种半导体器件,包括:
再分布层(RDL);
管芯,设置在所述再分布层上;
第一组贯通孔,位于顶衬底和所述再分布层之间并且连接所述顶衬底和所述再分布层,所述第一组贯通孔与模塑料物理接触并且通过所述模塑料与所述管芯分离;以及
第一互连结构,位于所述顶衬底和所述再分布层之间并且连接所述顶衬底和所述再分布层,所述第一互连结构通过所述模塑料与所述管芯和所述第一组贯通孔分离,所述第一互连结构包括:
至少一个无源器件;以及
第二组贯通孔,位于所述第一互连结构内。
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US20180122781A1 (en) | 2018-05-03 |
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US10090284B2 (en) | 2018-10-02 |
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