JP5232185B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5232185B2 JP5232185B2 JP2010049348A JP2010049348A JP5232185B2 JP 5232185 B2 JP5232185 B2 JP 5232185B2 JP 2010049348 A JP2010049348 A JP 2010049348A JP 2010049348 A JP2010049348 A JP 2010049348A JP 5232185 B2 JP5232185 B2 JP 5232185B2
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Description
図1は、本発明の第1の実施形態に係る半導体装置の製造方法によって形成された半導体装置を下面側から見た平面図である。図1に示すように、本実施形態によって形成される半導体装置11は、装置11の下面に格子状に複数のBGA(Ball Grid Array)ボール12が形成された構成である。これらのBGAボール12は、装置11の外部電極となるものであり、BGAボール12を介して、図示しない実装基板上の配線と装置11内部に封止された半導体チップ13とが電気的に接続される。
次に、第2の実施形態に係る半導体装置の製造方法について説明する。第2の実施形態に係る半導体装置によって製造される半導体装置を下面側から見た平面図は図1と同様である。従って、この実施形態に係る半導体装置の製造方法によって製造される半導体装置の説明は、図1の一点鎖線A−A´に沿って示す断面図である図12を参照して説明する。なお、図12において、図2に示される半導体装置11と同一の箇所においては同一の符号を付すとともに、説明を省略する。
次に、第3の実施形態に係る半導体装置の製造方法について説明する。第3の実施形態に係る半導体装置によって製造される半導体装置の構造は図1、図2に示される構造と同一であるため説明を省略し、ここでは、第1の実施形態に係る半導体装置11の製造方法と異なる部分について説明する。
12・・・BGAボール
13・・・半導体チップ
14・・・ソルダーレジスト膜
15・・・配線パターン
16・・・ベース板
16A、33・・・めっき層
17、32、41・・・封止樹脂
18、51・・・支持フィルム
19・・・マーク認識用カメラ
20・・・ピックアップ装置
21・・・ダイシングライン
22・・・突き上げピン
34、42・・・溝
52・・・開口
Claims (2)
- それぞれに半導体チップが搭載された複数のベース板を、所定の間隔で支持体に貼り付ける工程と、
前記複数のベース板および複数の前記半導体チップを覆うように、前記支持体の下面に封止樹脂を形成した後、前記ベース板の周囲およびその下方の前記封止樹脂の一部を除去する工程と、
前記封止樹脂の下面に、それぞれの前記半導体チップに電気的に接続されるように配線パターンを形成する工程と、
前記配線パターンを含む前記封止樹脂の下面に、前記配線パターンの一部が露出するように配線保護膜を形成する工程と、
前記配線保護膜から露出した前記配線パターン接触するように外部電極を形成する工程と、
それぞれの前記ベース板の周囲およびその下方に形成された前記封止樹脂の少なくとも一部および前記配線保護膜を切断する工程と、
前記封止樹脂に覆われた前記半導体チップおよび前記ベース板を、前記支持体から剥がす工程と、
を具備することを特徴とする半導体装置の製造方法。 - 前記ベース板は、ステンレス、銅、若しくはセラミックからなることを特徴とする請求項1に記載の半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010049348A JP5232185B2 (ja) | 2010-03-05 | 2010-03-05 | 半導体装置の製造方法 |
TW100105095A TWI467669B (zh) | 2010-03-05 | 2011-02-16 | Semiconductor device manufacturing method and semiconductor device |
KR1020110018952A KR20110101068A (ko) | 2010-03-05 | 2011-03-03 | 반도체 장치의 제조 방법 및 반도체 장치 |
US13/039,663 US8673690B2 (en) | 2010-03-05 | 2011-03-03 | Method for manufacturing a semiconductor device and a semiconductor device |
CN201110052233.2A CN102194716B (zh) | 2010-03-05 | 2011-03-04 | 半导体装置的制造方法及半导体装置 |
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JP2010049348A JP5232185B2 (ja) | 2010-03-05 | 2010-03-05 | 半導体装置の製造方法 |
Publications (2)
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JP2011187551A JP2011187551A (ja) | 2011-09-22 |
JP5232185B2 true JP5232185B2 (ja) | 2013-07-10 |
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JP2010049348A Expired - Fee Related JP5232185B2 (ja) | 2010-03-05 | 2010-03-05 | 半導体装置の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8673690B2 (ja) |
JP (1) | JP5232185B2 (ja) |
KR (1) | KR20110101068A (ja) |
CN (1) | CN102194716B (ja) |
TW (1) | TWI467669B (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010219489A (ja) * | 2009-02-20 | 2010-09-30 | Toshiba Corp | 半導体装置およびその製造方法 |
US9117682B2 (en) * | 2011-10-11 | 2015-08-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of packaging semiconductor devices and structures thereof |
JP5810957B2 (ja) | 2012-02-17 | 2015-11-11 | 富士通株式会社 | 半導体装置の製造方法及び電子装置の製造方法 |
JP5810958B2 (ja) * | 2012-02-17 | 2015-11-11 | 富士通株式会社 | 半導体装置の製造方法及び電子装置の製造方法 |
US8907502B2 (en) * | 2012-06-29 | 2014-12-09 | Nitto Denko Corporation | Encapsulating layer-covered semiconductor element, producing method thereof, and semiconductor device |
DE102013210850B3 (de) * | 2013-06-11 | 2014-03-27 | Infineon Technologies Ag | Verfahren zur Herstellung eines Halbleitermoduls unter Verwendung eines Adhäsionsträgers |
JP6219155B2 (ja) * | 2013-12-13 | 2017-10-25 | 東芝メモリ株式会社 | 半導体装置の製造方法 |
US20160064299A1 (en) * | 2014-08-29 | 2016-03-03 | Nishant Lakhera | Structure and method to minimize warpage of packaged semiconductor devices |
JP6511695B2 (ja) * | 2015-01-20 | 2019-05-15 | ローム株式会社 | 半導体装置およびその製造方法 |
JP2017162876A (ja) * | 2016-03-07 | 2017-09-14 | 株式会社ジェイデバイス | 半導体パッケージの製造方法 |
JP6691835B2 (ja) * | 2016-06-17 | 2020-05-13 | 株式会社アムコー・テクノロジー・ジャパン | 半導体パッケージの製造方法 |
KR102492533B1 (ko) | 2017-09-21 | 2023-01-30 | 삼성전자주식회사 | 지지 기판, 이를 이용한 반도체 패키지의 제조방법 및 이를 이용한 전자 장치의 제조 방법 |
CN113329676A (zh) * | 2019-03-18 | 2021-08-31 | 奥林巴斯株式会社 | 保持框、内窥镜前端构造以及内窥镜 |
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JP3247384B2 (ja) * | 1994-03-18 | 2002-01-15 | 日立化成工業株式会社 | 半導体パッケージの製造法及び半導体パッケージ |
US6001671A (en) * | 1996-04-18 | 1999-12-14 | Tessera, Inc. | Methods for manufacturing a semiconductor package having a sacrificial layer |
KR100222299B1 (ko) * | 1996-12-16 | 1999-10-01 | 윤종용 | 웨이퍼 레벨 칩 스케일 패키지 및 그의 제조 방법 |
JP3526731B2 (ja) * | 1997-10-08 | 2004-05-17 | 沖電気工業株式会社 | 半導体装置およびその製造方法 |
JP2000077576A (ja) * | 1998-09-02 | 2000-03-14 | Texas Instr Japan Ltd | 半導体装置及びその製造方法 |
US6338980B1 (en) * | 1999-08-13 | 2002-01-15 | Citizen Watch Co., Ltd. | Method for manufacturing chip-scale package and manufacturing IC chip |
JP3813402B2 (ja) * | 2000-01-31 | 2006-08-23 | 新光電気工業株式会社 | 半導体装置の製造方法 |
US20040173894A1 (en) * | 2001-09-27 | 2004-09-09 | Amkor Technology, Inc. | Integrated circuit package including interconnection posts for multiple electrical connections |
JP3825370B2 (ja) * | 2002-05-24 | 2006-09-27 | 富士通株式会社 | 半導体装置の製造方法 |
JP2004056012A (ja) * | 2002-07-23 | 2004-02-19 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP3739375B2 (ja) * | 2003-11-28 | 2006-01-25 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
US7459781B2 (en) * | 2003-12-03 | 2008-12-02 | Wen-Kun Yang | Fan out type wafer level package structure and method of the same |
JP4746847B2 (ja) * | 2004-04-27 | 2011-08-10 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP2006222164A (ja) * | 2005-02-08 | 2006-08-24 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
SG149743A1 (en) | 2007-07-17 | 2009-02-27 | Advanced Chip Eng Tech Inc | Semiconductor packaging method by using large panel size |
TW201001632A (en) * | 2008-06-19 | 2010-01-01 | Chipmos Technologies Inc | Chip rearrangement package structure and the method thereof |
JP2010219489A (ja) | 2009-02-20 | 2010-09-30 | Toshiba Corp | 半導体装置およびその製造方法 |
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2010
- 2010-03-05 JP JP2010049348A patent/JP5232185B2/ja not_active Expired - Fee Related
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2011
- 2011-02-16 TW TW100105095A patent/TWI467669B/zh active
- 2011-03-03 KR KR1020110018952A patent/KR20110101068A/ko not_active Application Discontinuation
- 2011-03-03 US US13/039,663 patent/US8673690B2/en not_active Expired - Fee Related
- 2011-03-04 CN CN201110052233.2A patent/CN102194716B/zh active Active
Also Published As
Publication number | Publication date |
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JP2011187551A (ja) | 2011-09-22 |
CN102194716B (zh) | 2015-01-28 |
US8673690B2 (en) | 2014-03-18 |
TWI467669B (zh) | 2015-01-01 |
KR20110101068A (ko) | 2011-09-15 |
TW201140709A (en) | 2011-11-16 |
CN102194716A (zh) | 2011-09-21 |
US20110215461A1 (en) | 2011-09-08 |
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