JP6219155B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6219155B2 JP6219155B2 JP2013258704A JP2013258704A JP6219155B2 JP 6219155 B2 JP6219155 B2 JP 6219155B2 JP 2013258704 A JP2013258704 A JP 2013258704A JP 2013258704 A JP2013258704 A JP 2013258704A JP 6219155 B2 JP6219155 B2 JP 6219155B2
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Description
Claims (4)
- 配線基板に半導体チップを搭載する工程と、
前記半導体チップを封止するように、無機充填材を含有する封止樹脂層を形成する工程と、
ドライエッチングにより前記無機充填材の一部が露出するまで前記封止樹脂層の一部を除去する工程と、
前記ドライエッチング後に前記封止樹脂層を大気曝露することなく、少なくとも前記封止樹脂層を覆うようにシールド層を形成する工程と、を具備する半導体装置の製造方法。 - 前記ドライエッチングは、逆スパッタリングであり、
前記シールド層を形成する工程は、スパッタリングにより行う請求項1に記載の半導体装置の製造方法。 - 配線基板に半導体チップを搭載する工程と、
前記半導体チップを封止するように、無機充填材を含有する封止樹脂層を形成する工程と、
逆スパッタリングにより前記封止樹脂層の一部を表面から2.5nm以上7.5nm未満の深さまで除去する工程と、
前記逆スパッタリング後に前記封止樹脂層を大気曝露することなく、スパッタリングにより少なくとも前記封止樹脂層を覆うようにシールド層を形成する工程と、を具備する半導体装置の製造方法。 - 前記封止樹脂層の一部を除去する工程において、前記封止樹脂層の表面全体が灰化する前まで前記逆スパッタリングを行う請求項2または請求項3に記載の半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013258704A JP6219155B2 (ja) | 2013-12-13 | 2013-12-13 | 半導体装置の製造方法 |
TW103125175A TWI579934B (zh) | 2013-12-13 | 2014-07-22 | 半導體裝置之製造方法及半導體裝置 |
US14/475,326 US10312197B2 (en) | 2013-12-13 | 2014-09-02 | Method of manufacturing semiconductor device and semiconductor device |
CN201910213744.4A CN110010587B (zh) | 2013-12-13 | 2014-09-05 | 半导体装置的制造方法及半导体装置 |
CN201410452584.6A CN104716053A (zh) | 2013-12-13 | 2014-09-05 | 半导体装置的制造方法及半导体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013258704A JP6219155B2 (ja) | 2013-12-13 | 2013-12-13 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2015115559A JP2015115559A (ja) | 2015-06-22 |
JP6219155B2 true JP6219155B2 (ja) | 2017-10-25 |
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JP2013258704A Active JP6219155B2 (ja) | 2013-12-13 | 2013-12-13 | 半導体装置の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10312197B2 (ja) |
JP (1) | JP6219155B2 (ja) |
CN (2) | CN110010587B (ja) |
TW (1) | TWI579934B (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9601464B2 (en) | 2014-07-10 | 2017-03-21 | Apple Inc. | Thermally enhanced package-on-package structure |
CN107535081B (zh) * | 2015-05-11 | 2021-02-02 | 株式会社村田制作所 | 高频模块 |
JP6414637B2 (ja) * | 2015-06-04 | 2018-10-31 | 株式会社村田製作所 | 高周波モジュール |
US10109593B2 (en) | 2015-07-23 | 2018-10-23 | Apple Inc. | Self shielded system in package (SiP) modules |
JP6480823B2 (ja) * | 2015-07-23 | 2019-03-13 | 東芝メモリ株式会社 | 半導体装置の製造方法 |
JP6418605B2 (ja) * | 2015-07-31 | 2018-11-07 | 東芝メモリ株式会社 | 半導体装置および半導体装置の製造方法 |
JP6439053B2 (ja) * | 2015-08-26 | 2018-12-19 | 株式会社アルバック | 電子部品の製造方法および処理システム |
JP6397806B2 (ja) * | 2015-09-11 | 2018-09-26 | 東芝メモリ株式会社 | 半導体装置の製造方法および半導体装置 |
JP6617497B2 (ja) * | 2015-09-25 | 2019-12-11 | Tdk株式会社 | 半導体パッケージの製造方法 |
KR20170127324A (ko) * | 2016-05-11 | 2017-11-21 | (주)제이티 | 반도체소자 캐리어, 이의 제조방법 및 이를 포함하는 소자핸들러 |
US10825780B2 (en) * | 2016-11-29 | 2020-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with electromagnetic interference protection and method of manufacture |
JP6887326B2 (ja) * | 2017-06-28 | 2021-06-16 | 株式会社ディスコ | 半導体パッケージの形成方法 |
CN108770227B (zh) * | 2018-06-14 | 2021-07-13 | 环旭电子股份有限公司 | 一种基于二次塑封的SiP模组的制造方法及SiP模组 |
CN108601241B (zh) | 2018-06-14 | 2021-12-24 | 环旭电子股份有限公司 | 一种SiP模组及其制造方法 |
US11508668B2 (en) | 2020-12-03 | 2022-11-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method for manufacturing the same |
CN115881675B (zh) * | 2023-02-08 | 2024-04-02 | 荣耀终端有限公司 | 封装基板、其制备方法、封装结构及电子设备 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4343677A (en) * | 1981-03-23 | 1982-08-10 | Bell Telephone Laboratories, Incorporated | Method for patterning films using reactive ion etching thereof |
JPH03130373A (ja) * | 1989-10-13 | 1991-06-04 | Fujitsu Ltd | ガラスフィラー入り樹脂成形品の表面処理方法 |
JPH06236981A (ja) | 1993-02-10 | 1994-08-23 | Fujitsu Ltd | 固体撮像素子 |
JPH0745948A (ja) * | 1993-07-28 | 1995-02-14 | Ibiden Co Ltd | 多層配線板及びその製造方法 |
JP2845847B2 (ja) | 1996-11-12 | 1999-01-13 | 九州日本電気株式会社 | 半導体集積回路 |
TW569424B (en) * | 2000-03-17 | 2004-01-01 | Matsushita Electric Ind Co Ltd | Module with embedded electric elements and the manufacturing method thereof |
JP3901437B2 (ja) * | 2000-09-07 | 2007-04-04 | 株式会社リコー | 樹脂成形用断熱スタンパーおよびその製造方法 |
JP2003264373A (ja) * | 2002-03-08 | 2003-09-19 | Kanegafuchi Chem Ind Co Ltd | プリント配線板用積層体 |
JP2003273113A (ja) * | 2002-03-18 | 2003-09-26 | Seiko Epson Corp | 半導体装置および配線形成方法 |
JP3810359B2 (ja) | 2002-09-19 | 2006-08-16 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
TW200507218A (en) | 2003-03-31 | 2005-02-16 | North Corp | Layout circuit substrate, manufacturing method of layout circuit substrate, and circuit module |
JP2005109306A (ja) * | 2003-10-01 | 2005-04-21 | Matsushita Electric Ind Co Ltd | 電子部品パッケージおよびその製造方法 |
JP2007103632A (ja) | 2005-10-04 | 2007-04-19 | Nec Electronics Corp | 半導体集積回路の設計方法および半導体集積回路 |
JP4752586B2 (ja) | 2006-04-12 | 2011-08-17 | ソニー株式会社 | 半導体装置の製造方法 |
US20080083957A1 (en) | 2006-10-05 | 2008-04-10 | Wen-Chieh Wei | Micro-electromechanical system package |
KR100877551B1 (ko) * | 2008-05-30 | 2009-01-07 | 윤점채 | 전자파 차폐 기능을 갖는 반도체 패키지, 그 제조방법 및 지그 |
WO2010013470A1 (ja) * | 2008-07-31 | 2010-02-04 | 三洋電機株式会社 | 半導体モジュールおよび半導体モジュールを備える携帯機器 |
JP2011142204A (ja) | 2010-01-07 | 2011-07-21 | Renesas Electronics Corp | 半導体装置及び半導体装置の製造方法 |
JP5232185B2 (ja) * | 2010-03-05 | 2013-07-10 | 株式会社東芝 | 半導体装置の製造方法 |
US9362196B2 (en) * | 2010-07-15 | 2016-06-07 | Kabushiki Kaisha Toshiba | Semiconductor package and mobile device using the same |
JP2012151326A (ja) | 2011-01-20 | 2012-08-09 | Toshiba Corp | 半導体装置の製造方法、半導体装置及び電子部品のシールド方法 |
JP2012243895A (ja) * | 2011-05-18 | 2012-12-10 | Renesas Electronics Corp | 半導体装置およびその製造方法ならびに携帯電話機 |
US20130168231A1 (en) * | 2011-12-31 | 2013-07-04 | Intermolecular Inc. | Method For Sputter Deposition And RF Plasma Sputter Etch Combinatorial Processing |
JP6001893B2 (ja) | 2012-03-23 | 2016-10-05 | ローム株式会社 | セルベースic、セルベースicのレイアウトシステムおよびレイアウト方法 |
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