JP5726553B2 - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Description
最初に、実施形態に係る半導体装置の製造方法によって製造される半導体装置の概要について説明する。
図1は、第1実施形態に係る半導体装置の断面模式図である。
図2は、第1実施形態に係る半導体装置の平面模式図である。
図1には、図2のX−X’断面が示されている。
図3および図4は、第1実施形態に係る半導体装置の製造過程を説明するための断面模式図である。
図5および図6は、第2実施形態に係る半導体装置の製造過程を説明するための断面模式図である。
次に、図5(b)に示すように、複数の半導体素子20、配線層12およびワイヤ21等を封止樹脂層30によって封止する。これにより、基板10Aの上面側に封止樹脂層30が形成される。続いて、基板10Aの下面側を下地に接触させる。下地は、ダイシングシート100と、ダイシングシート100の上に設けられたシート部材101と、を含む。 シート部材101は、例えば、樹脂製の板状体である。シート部材101の主面には、必要に応じて粘着層を設けてもよい。
図7は、第3実施形態に係る半導体装置を説明する模式図であり、(a)は、断面模式図、(b)は平面模式図である。
図7(a)には、図8のX−X’断面が示されている。
図8および図9は、第3実施形態に係る半導体装置の製造過程を説明するための断面模式図である。
図10は、第4実施形態に係る半導体装置の製造過程で用いられる半導体装置の下地を説明するための模式図であり、(a)は、下地の表面模式図、(b)は、(a)のX−X’位置の断面模式図であり、(c)は、(a)のY−Y’位置の断面模式図である。
このようなシート部材102を含む下地をダイシング工程で用いれば、個片化された封止樹脂層30および回路基板10のそれぞれの間において、上から下に導電性シールド層40を侵入させても、個片化された封止樹脂層30および回路基板10のそれぞれの間に存在する空気は、層102a中の溝102x、102yを通じて効率よく排気される(図11(b)の矢印参照)。これにより、導電性シールド層40が個片化された回路基板10のそれぞれの間に円滑に侵入する。
図13は、第5実施形態に係る半導体装置の製造過程で用いられる半導体装置の下地を説明するための模式図であり、(a)は、下地の下面模式図、(b)は、(a)のX−X’位置の断面模式図であり、(c)は、(a)のY−Y’位置の断面模式図である。
図16は、第6実施形態に係る半導体装置の製造過程を説明するための断面模式図である。
次に、図16(b)に示すように、導電性シールド層40を個片化して半導体装置3を形成する。
10 回路基板
10A 基板
10w 側面
11 絶縁基材
12 配線層(第1配線層)
13 配線層(第2配線層)
14 ビア
15 配線層
16 ソルダレジスト層
17 外部接続端子
20 半導体素子
21 ワイヤ
22 マウント材
30 封止樹脂層
30s 隙間
40 導電性シールド層
40p 突出部
100、150 ダイシングシート
100s、101s 空間
100t、101t、102t、103t 溝
101、102、103、104、105 シート部材
102a、103a、104b、105b 層
102b、103b、104a、105a シート基材
103d、105d 凸部
102x、102y、104a、104y 溝
200 スキージ板
Claims (5)
- 絶縁基材と、前記絶縁基材の上面側に設けられた第1配線層を構成する複数の配線と、前記絶縁基材の下面側に設けられた第2配線層を構成する複数の配線と、前記絶縁基材の前記上面から前記下面にまで貫通する複数のビアと、を有する回路基板が前記回路基板の主面に対して平行な方向に複数連続して設けられた基板を準備する工程と、
前記複数の回路基板のそれぞれの上面側に半導体素子を搭載する工程と、
前記半導体素子および前記第1配線層を構成する複数の配線を封止する封止樹脂層を、前記基板の上面側に形成する工程と、
前記基板の下面側を、ダイシングシートと、前記ダイシングシートの上に設けられたシート部材と、を含む下地に接触させる工程と、
前記封止樹脂層および前記回路基板のそれぞれを個片化し、前記第1配線層を構成する複数の配線のいずれか、または前記複数のビアのいずれかを、前記回路基板の側面において露出させるとともに、個片化された前記回路基板のそれぞれの間の前記シート部材に溝を形成する工程と、
個片化されたそれぞれの前記封止樹脂層の上面を導電性シールド層により被覆するとともに、それぞれの前記封止樹脂層の側面、および、それぞれの前記回路基板の側面の少なくとも一部を前記導電性シールド層により被覆する工程と、
を備え、
前記封止樹脂層の前記側面および前記回路基板の前記側面の少なくとも一部を前記導電性シールド層により被覆する際には、
互いに隣接する前記封止樹脂層のあいだに形成された隙間の上から下に前記導電性シールド層を浸入させ、さらに、前記導電性シールド層が前記第1配線層または前記ビアに接するまで前記導電性シールド層を前記溝に向かって浸入させる半導体装置の製造方法。 - 前記シート部材は、シート基材と、前記シート基材の上または下に設けられた層と、を有し、前記層には、空気を通す隙間が設けられている請求項1記載の半導体装置の製造方法。
- 前記層に、前記溝を形成する請求項2記載の半導体装置の製造方法。
- 前記シート基材に前記溝を形成する請求項2記載の半導体装置の製造方法。
- 前記導電性シールド層を前記回路基板の下面の位置から下方に突出させる請求項1〜4のいずれか1つに記載の半導体装置の製造方法。
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