CN102194716A - 半导体装置的制造方法及半导体装置 - Google Patents
半导体装置的制造方法及半导体装置 Download PDFInfo
- Publication number
- CN102194716A CN102194716A CN2011100522332A CN201110052233A CN102194716A CN 102194716 A CN102194716 A CN 102194716A CN 2011100522332 A CN2011100522332 A CN 2011100522332A CN 201110052233 A CN201110052233 A CN 201110052233A CN 102194716 A CN102194716 A CN 102194716A
- Authority
- CN
- China
- Prior art keywords
- sealing resin
- semiconductor device
- substrate
- manufacture method
- wiring pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Dicing (AREA)
Abstract
Description
Claims (20)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010049348A JP5232185B2 (ja) | 2010-03-05 | 2010-03-05 | 半導体装置の製造方法 |
JP049348/2010 | 2010-03-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102194716A true CN102194716A (zh) | 2011-09-21 |
CN102194716B CN102194716B (zh) | 2015-01-28 |
Family
ID=44530609
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110052233.2A Active CN102194716B (zh) | 2010-03-05 | 2011-03-04 | 半导体装置的制造方法及半导体装置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8673690B2 (zh) |
JP (1) | JP5232185B2 (zh) |
KR (1) | KR20110101068A (zh) |
CN (1) | CN102194716B (zh) |
TW (1) | TWI467669B (zh) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103531514A (zh) * | 2012-06-29 | 2014-01-22 | 日东电工株式会社 | 覆有密封层的半导体元件、其制造方法及半导体装置 |
CN104241145A (zh) * | 2013-06-11 | 2014-12-24 | 英飞凌科技股份有限公司 | 用于在使用附着载体的情况下制造半导体模块的方法 |
CN109545730A (zh) * | 2017-09-21 | 2019-03-29 | 三星电子株式会社 | 支撑基板、电子器件制造方法、半导体封装件及制造方法 |
CN110010587A (zh) * | 2013-12-13 | 2019-07-12 | 东芝存储器株式会社 | 半导体装置的制造方法及半导体装置 |
CN113329676A (zh) * | 2019-03-18 | 2021-08-31 | 奥林巴斯株式会社 | 保持框、内窥镜前端构造以及内窥镜 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010219489A (ja) * | 2009-02-20 | 2010-09-30 | Toshiba Corp | 半導体装置およびその製造方法 |
US9117682B2 (en) | 2011-10-11 | 2015-08-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of packaging semiconductor devices and structures thereof |
JP5810957B2 (ja) | 2012-02-17 | 2015-11-11 | 富士通株式会社 | 半導体装置の製造方法及び電子装置の製造方法 |
JP5810958B2 (ja) * | 2012-02-17 | 2015-11-11 | 富士通株式会社 | 半導体装置の製造方法及び電子装置の製造方法 |
US20160064299A1 (en) * | 2014-08-29 | 2016-03-03 | Nishant Lakhera | Structure and method to minimize warpage of packaged semiconductor devices |
JP6511695B2 (ja) * | 2015-01-20 | 2019-05-15 | ローム株式会社 | 半導体装置およびその製造方法 |
JP2017162876A (ja) * | 2016-03-07 | 2017-09-14 | 株式会社ジェイデバイス | 半導体パッケージの製造方法 |
JP6691835B2 (ja) * | 2016-06-17 | 2020-05-13 | 株式会社アムコー・テクノロジー・ジャパン | 半導体パッケージの製造方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1144016A (zh) * | 1994-03-18 | 1997-02-26 | 日立化成工业株式会社 | 半导体组件的制造方法及半导体组件 |
US6338980B1 (en) * | 1999-08-13 | 2002-01-15 | Citizen Watch Co., Ltd. | Method for manufacturing chip-scale package and manufacturing IC chip |
JP2003347470A (ja) * | 2002-05-24 | 2003-12-05 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2004056012A (ja) * | 2002-07-23 | 2004-02-19 | Renesas Technology Corp | 半導体装置およびその製造方法 |
CN1624888A (zh) * | 2003-12-03 | 2005-06-08 | 育霈科技股份有限公司 | 扩散式晶圆型态封装的结构与其形成方法 |
CN1691318A (zh) * | 2004-04-27 | 2005-11-02 | 三洋电机株式会社 | 半导体装置及其制造方法 |
JP2006222164A (ja) * | 2005-02-08 | 2006-08-24 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6001671A (en) * | 1996-04-18 | 1999-12-14 | Tessera, Inc. | Methods for manufacturing a semiconductor package having a sacrificial layer |
KR100222299B1 (ko) * | 1996-12-16 | 1999-10-01 | 윤종용 | 웨이퍼 레벨 칩 스케일 패키지 및 그의 제조 방법 |
JP3526731B2 (ja) * | 1997-10-08 | 2004-05-17 | 沖電気工業株式会社 | 半導体装置およびその製造方法 |
JP2000077576A (ja) * | 1998-09-02 | 2000-03-14 | Texas Instr Japan Ltd | 半導体装置及びその製造方法 |
JP3813402B2 (ja) * | 2000-01-31 | 2006-08-23 | 新光電気工業株式会社 | 半導体装置の製造方法 |
US20040173894A1 (en) * | 2001-09-27 | 2004-09-09 | Amkor Technology, Inc. | Integrated circuit package including interconnection posts for multiple electrical connections |
JP3739375B2 (ja) * | 2003-11-28 | 2006-01-25 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
SG149743A1 (en) | 2007-07-17 | 2009-02-27 | Advanced Chip Eng Tech Inc | Semiconductor packaging method by using large panel size |
TW201001632A (en) * | 2008-06-19 | 2010-01-01 | Chipmos Technologies Inc | Chip rearrangement package structure and the method thereof |
JP2010219489A (ja) | 2009-02-20 | 2010-09-30 | Toshiba Corp | 半導体装置およびその製造方法 |
-
2010
- 2010-03-05 JP JP2010049348A patent/JP5232185B2/ja not_active Expired - Fee Related
-
2011
- 2011-02-16 TW TW100105095A patent/TWI467669B/zh active
- 2011-03-03 US US13/039,663 patent/US8673690B2/en not_active Expired - Fee Related
- 2011-03-03 KR KR1020110018952A patent/KR20110101068A/ko not_active Application Discontinuation
- 2011-03-04 CN CN201110052233.2A patent/CN102194716B/zh active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1144016A (zh) * | 1994-03-18 | 1997-02-26 | 日立化成工业株式会社 | 半导体组件的制造方法及半导体组件 |
US6338980B1 (en) * | 1999-08-13 | 2002-01-15 | Citizen Watch Co., Ltd. | Method for manufacturing chip-scale package and manufacturing IC chip |
JP2003347470A (ja) * | 2002-05-24 | 2003-12-05 | Fujitsu Ltd | 半導体装置の製造方法 |
JP2004056012A (ja) * | 2002-07-23 | 2004-02-19 | Renesas Technology Corp | 半導体装置およびその製造方法 |
CN1624888A (zh) * | 2003-12-03 | 2005-06-08 | 育霈科技股份有限公司 | 扩散式晶圆型态封装的结构与其形成方法 |
CN1691318A (zh) * | 2004-04-27 | 2005-11-02 | 三洋电机株式会社 | 半导体装置及其制造方法 |
JP2006222164A (ja) * | 2005-02-08 | 2006-08-24 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103531514A (zh) * | 2012-06-29 | 2014-01-22 | 日东电工株式会社 | 覆有密封层的半导体元件、其制造方法及半导体装置 |
CN104241145A (zh) * | 2013-06-11 | 2014-12-24 | 英飞凌科技股份有限公司 | 用于在使用附着载体的情况下制造半导体模块的方法 |
CN104241145B (zh) * | 2013-06-11 | 2017-12-08 | 英飞凌科技股份有限公司 | 用于在使用附着载体的情况下制造半导体模块的方法 |
CN110010587A (zh) * | 2013-12-13 | 2019-07-12 | 东芝存储器株式会社 | 半导体装置的制造方法及半导体装置 |
CN109545730A (zh) * | 2017-09-21 | 2019-03-29 | 三星电子株式会社 | 支撑基板、电子器件制造方法、半导体封装件及制造方法 |
US11908727B2 (en) | 2017-09-21 | 2024-02-20 | Samsung Electronics Co., Ltd. | Support substrates, methods of fabricating semiconductor packages using the same, and methods of fabricating electronic devices using the same |
CN113329676A (zh) * | 2019-03-18 | 2021-08-31 | 奥林巴斯株式会社 | 保持框、内窥镜前端构造以及内窥镜 |
CN113329676B (zh) * | 2019-03-18 | 2024-05-24 | 奥林巴斯株式会社 | 保持框、内窥镜前端构造以及内窥镜 |
Also Published As
Publication number | Publication date |
---|---|
TWI467669B (zh) | 2015-01-01 |
JP2011187551A (ja) | 2011-09-22 |
JP5232185B2 (ja) | 2013-07-10 |
CN102194716B (zh) | 2015-01-28 |
TW201140709A (en) | 2011-11-16 |
US20110215461A1 (en) | 2011-09-08 |
KR20110101068A (ko) | 2011-09-15 |
US8673690B2 (en) | 2014-03-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102194716A (zh) | 半导体装置的制造方法及半导体装置 | |
TWI634821B (zh) | 形成無核心基材之基材帶及方法 | |
US7622377B2 (en) | Microfeature workpiece substrates having through-substrate vias, and associated methods of formation | |
KR100608186B1 (ko) | 반도체 장치의 제조 방법 | |
CN100435332C (zh) | 具有高反差标志的金属层的半导体器件及制造方法 | |
CN101728363A (zh) | 晶片封装结构及其制作方法 | |
JP2008270810A (ja) | ヒートシンクおよびアースシールドの機能を向上させるための半導体デバイスパッケージ | |
US7825468B2 (en) | Semiconductor packages, stacked semiconductor packages, and methods of manufacturing the semiconductor packages and the stacked semiconductor packages | |
JP2001053110A (ja) | 半導体素子の実装方法及び実装装置 | |
US11043409B2 (en) | Method of forming contacts to an embedded semiconductor die and related semiconductor packages | |
CN101228625A (zh) | 具有镀金属连接部的半导体封装 | |
EP1906445A3 (en) | Manufacturing method of semiconductor device | |
TWI413210B (zh) | 電子裝置封裝及製造方法 | |
CN102034721A (zh) | 芯片封装方法 | |
CN106206486A (zh) | 电子器件封装 | |
CN101271853A (zh) | 制造电子器件、基板和半导体器件的方法 | |
JP2004186688A (ja) | 再配線素子を備える集積回路の形成方法及びそれに対応する集積回路 | |
CN104201156A (zh) | 基于基板的凸点倒装芯片csp封装件、基板及制造方法 | |
US9685376B2 (en) | Semiconductor device and method of manufacturing semiconductor device | |
US20100148339A1 (en) | Process for fabricating a semiconductor component support, support and semiconductor device | |
CN104347437A (zh) | 制造半导体器件的方法 | |
US8102046B2 (en) | Semiconductor device and method of manufacturing the same | |
US20230299027A1 (en) | Structure and method for semiconductor packaging | |
KR20180089886A (ko) | 반도체 칩의 제조 방법 | |
CN101373748B (zh) | 晶圆级封装结构及其制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20170728 Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Toshiba Corp. |
|
TR01 | Transfer of patent right | ||
CP01 | Change in the name or title of a patent holder |
Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Japanese businessman Panjaya Co.,Ltd. Address after: Tokyo, Japan Patentee after: Kaixia Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. |
|
CP01 | Change in the name or title of a patent holder | ||
TR01 | Transfer of patent right |
Effective date of registration: 20211231 Address after: Tokyo, Japan Patentee after: Japanese businessman Panjaya Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. |
|
TR01 | Transfer of patent right |