SG149743A1 - Semiconductor packaging method by using large panel size - Google Patents

Semiconductor packaging method by using large panel size

Info

Publication number
SG149743A1
SG149743A1 SG200718392-4A SG2007183924A SG149743A1 SG 149743 A1 SG149743 A1 SG 149743A1 SG 2007183924 A SG2007183924 A SG 2007183924A SG 149743 A1 SG149743 A1 SG 149743A1
Authority
SG
Singapore
Prior art keywords
dice
packaging method
semiconductor packaging
tool
large panel
Prior art date
Application number
SG200718392-4A
Inventor
Wen-Kun Yang
Chih-Wei Lin
Chun-Hui Yu
Original Assignee
Advanced Chip Eng Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from TW96126073A external-priority patent/TW200818350A/en
Application filed by Advanced Chip Eng Tech Inc filed Critical Advanced Chip Eng Tech Inc
Publication of SG149743A1 publication Critical patent/SG149743A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

Semiconductor Packaging Method by Using Large Panel Size The present invention discloses a semiconductor packaging method, comprises steps of back lapping a processed silicon wafer to a desired thickness. Then, the dice are separated from the processed and lapped wafer into a single die. Then, the dice are picked and placed on a tool, an active surface of the dice is attached on the tool. A molding is performed to mold the dice by molding material. The tool is then removed from the dice to form a small unit. The next step is to arrange a plurality of the small units on a carrier in a matrix from. Then, a build-up layer, a re-distribution layer are formed over the dice, followed by forming solder balls on the dice. Finally, the carrier is removed.
SG200718392-4A 2007-07-17 2007-12-06 Semiconductor packaging method by using large panel size SG149743A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW96126073A TW200818350A (en) 2006-10-05 2007-07-17 Semiconductor packaging method by using large panel size

Publications (1)

Publication Number Publication Date
SG149743A1 true SG149743A1 (en) 2009-02-27

Family

ID=40149282

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200718392-4A SG149743A1 (en) 2007-07-17 2007-12-06 Semiconductor packaging method by using large panel size

Country Status (4)

Country Link
JP (1) JP2009027127A (en)
KR (1) KR20090008105A (en)
DE (1) DE102008031373A1 (en)
SG (1) SG149743A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5232185B2 (en) 2010-03-05 2013-07-10 株式会社東芝 Manufacturing method of semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package

Also Published As

Publication number Publication date
KR20090008105A (en) 2009-01-21
DE102008031373A1 (en) 2009-01-22
JP2009027127A (en) 2009-02-05

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