JP2009027127A - Method for manufacturing semiconductor package by adopting large-scaled panel size - Google Patents

Method for manufacturing semiconductor package by adopting large-scaled panel size Download PDF

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JP2009027127A
JP2009027127A JP2008002871A JP2008002871A JP2009027127A JP 2009027127 A JP2009027127 A JP 2009027127A JP 2008002871 A JP2008002871 A JP 2008002871A JP 2008002871 A JP2008002871 A JP 2008002871A JP 2009027127 A JP2009027127 A JP 2009027127A
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die
tool
semiconductor package
layer
molding
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Wen-Kun Yang
ヤン ウェン−クン
Chih-Wei Lin
リン チー−ウェイ
Chun-Hui Yu
ユ チュン−フイ
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Advanced Chip Engineering Technology Inc
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Advanced Chip Engineering Technology Inc
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Priority claimed from TW96126073A external-priority patent/TW200818350A/en
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means for efficiently performing rewriting on a thin semiconductor chip. <P>SOLUTION: Individual piece-sized chips 406 are arrayed, in a state such that the active faces of those IC chips 406 are faced to a mending tool, the back faces and side faces of the chips 406 are sealed with resin, and the IC chips 406 are grounded to prescribed thickness so as to be made small, and attached to a substrate 520, and the mending tool is peeled. Afterwards, the substrate face of a plurality of units is attached to a pedestal, and rewiring 730, insulating layers 720 and solder balls 740 are formed on the active faces of the chips, and the pedestal is peeled so that individual semiconductors can be manufactured by dicing. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は半導体パッケージ製造、さらに特に大型パネルサイズとの採用によるユニットあたり最もパッケージコストの安い半導体パッケージ製造に関する。 The present invention relates to semiconductor package manufacturing, and more particularly to manufacturing a semiconductor package with the lowest package cost per unit by employing a large panel size.

従来の鉛フレームパッケージ技術はその端子密度が高すぎるため最新の半導体ダイにはもはや適切でない。従って、ＢＧＡ（ボール格子配列）という新たなパッケージ技術が最新半導体ダイ向けのパッケージ製造要件を満足させるために発達してきた。ＢＧＡパッケージには周辺端子が鉛フレームパッケージのものよりピッチが短いという利点があると同時に、ＢＧＡ端子は損傷や変形がしにくい傾向にある。さらに、信号伝達距離がより短いことにより、より効率性のよい要件に合致させるよう実効周波数が上がるというメリットが受けられる。多くのパッケージ技術はウェハー上にダイを各ダイに分割した後、それぞれダイをパッケージにしテストする。「ウェハーレベルパッケージ（ＷＬＰ）」と呼ばれる別のパッケージ技術は、ダイのそれぞれ個別のダイへの分割前にウェハー上のダイをパッケージにすることができる。ＷＬＰ技術にはより短いサイクル時間、低コスト、下部充填または成型不要といった利点がいくつかある。 Conventional lead frame packaging technology is no longer suitable for modern semiconductor dies due to its terminal density being too high. Therefore, a new packaging technology called BGA (Ball Grid Array) has been developed to satisfy the package manufacturing requirements for the latest semiconductor dies. The BGA package has the advantage that the peripheral terminals have a shorter pitch than that of the lead frame package, and at the same time, the BGA terminals tend not to be damaged or deformed. Further, the shorter signal transmission distance has the advantage of increasing the effective frequency to meet more efficient requirements. Many packaging technologies divide a die into dies on a wafer and then test each die in a package. Another packaging technology called "Wafer Level Package (WLP)" can package the dies on the wafer before dividing the dies into each individual die. WLP technology has several advantages, such as shorter cycle times, lower cost, and no bottom filling or molding.

図１は6,271,469により公開された従来の半導体パッケージ向け剥離成型方法を示す。本方法では、テープ１０４がミクロ電子ダイ１０２の活性面１０６に当接されて、ミクロ電子ダイ活性面１０６をあらゆる有害物から防護する。ミクロ電子ダイ活性面１０６にはそこに配置される少なくとも１つのコンタクト１０８がある。このコンタクト１０８はミクロ電子ダイ１０２内部で回路全体（図示されず）と電気接触状態にある。防護フィルム１０４にはウェハーダイス加工中に工業用に使用される防護フィルムに似たミクロ電子ダイ活性面１０６に貼りつく弱い接着性があっても良い。この接着タイプのフィルムはカプセル化工程に利用される母材でのミクロ電子ダイ１０２の設置に先立って貼られうる。防護フィルム１０４はカプセル化処理中の母材内面のミクロ電子ダイ活性面１０６上に保持されるＥＴＦＥ（エチレンテラフル−ロエチレン）またはテフロン（登録商標）、ＲＴＭフィルムといった非接着性のフィルムでも良い。 FIG. 1 shows a conventional peeling molding method for a semiconductor package disclosed by 6,271,469. In this method, the tape 104 is abutted against the active surface 106 of the microelectronic die 102 to protect the microelectronic die active surface 106 from any harmful substances. The microelectronic die active surface 106 has at least one contact 108 disposed thereon. This contact 108 is in electrical contact with the entire circuit (not shown) within the microelectronic die 102. The protective film 104 may have a weak adhesion that sticks to the microelectronic die active surface 106 similar to the protective film used for industrial use during wafer dicing. This adhesive type film can be applied prior to the installation of the microelectronic die 102 in the base material used in the encapsulation process. The protective film 104 may be a non-adhesive film such as ETFE (ethylene terafluoroethylene), Teflon (registered trademark), or RTM film held on the microelectronic die active surface 106 on the inner surface of the base material during encapsulation.

図２に戻ると、図１のテープは母材工具２００（剥離形）のパッケージ区域２０２上に置かれよう。図３に戻ると、その後に、ミクロ電子ダイ１０２は、図３に示されるように、ミクロ電子ダイ１０２の背面１１４および側面１１６を被覆するプラスチック、樹脂などといったカプセル材料１１２でカプセル化される。ミクロ電子ダイ１０２のカプセル化は射出、転写、ならびに圧縮成型だけに限られず任意の既知の処理で行われ得る。カプセル材料１１２により力学的剛性がもたらされ、ミクロ電子ダイ１０２が有害物から防護されるとともに、トレース積層層用表面区域が提供される。 Returning to FIG. 2, the tape of FIG. 1 will be placed on the package area 202 of the base material tool 200 (peeled). Returning to FIG. 3, the microelectronic die 102 is then encapsulated with an encapsulant 112 such as plastic, resin, etc. that covers the back surface 114 and side surfaces 116 of the microelectronic die 102, as shown in FIG. The encapsulation of the microelectronic die 102 is not limited to injection, transfer, and compression molding, and can be performed by any known process. The encapsulant material 112 provides mechanical rigidity, protects the microelectronic die 102 from harmful substances, and provides a surface area for the trace laminate layer.

しかしながら、該方法はひどく複雑であるだけでなく、成型工具２００にパッケージ区域２０２間に多くの間隔２０４がある。該間隔２０４により空間の多くが占有されすぎるので、多くのパッケージ用ダイが減少してしまう。さらに成型処理中のテープ上のダイの精度に問題がありそうでであって、ダイの移動やねじれを生ずるだけでなく、積層層と再分散処理に関して生産高にロスを生ずる場合がある。
6,271,469 However, the method is not only very complicated, but there are many spaces 204 between the package areas 202 in the molding tool 200. The spacing 204 occupies much of the space, reducing the number of packaging dies. Further, there may be a problem with the accuracy of the die on the tape during the molding process, which not only causes die movement or twisting, but may result in a loss in production with respect to the laminated layer and redispersion processing.
6,271,469

本発明は半導体パッケージ方法を公開するもので、加工済みシリコンウェハーの所望厚みまでの裏重ね段階が含まれるものである。次いで、ダイは加工と同時に重ね加工されたウェハーから分離されて単一のダイにされる。次に、ダイは取上げられるとともに工具上に置かれ、ダイの活性面が工具上に貼り付けられる。成型が行われ、成型材料によりダイが成型される。工具はその後、ダイから除去されて小型のユニットが形成される。次の段階は母材の形の台座上への複数の小型ユニットの配置である。そして、積層層、再分散層がダイ上に形成されて、ダイ上へのハンダボールの形成へと続く。最後に、台座が除去されると同時にダイが分離される。 The present invention discloses a semiconductor packaging method and includes a back-up step to a desired thickness of a processed silicon wafer. The dies are then separated from the overlaid wafer simultaneously with processing into a single die. The die is then picked up and placed on the tool, and the active surface of the die is affixed on the tool. Molding is performed, and a die is molded from the molding material. The tool is then removed from the die to form a small unit. The next step is the placement of multiple small units on a base in the form of a matrix. Then, a laminated layer and a redispersion layer are formed on the die, and the formation of solder balls on the die continues. Finally, the die is separated at the same time as the pedestal is removed.

ダイの貼り付け材料には水溶性接着剤、化学溶液溶解接着剤、リワーカブル接着剤、高融点ワックスが含まれ、取り外し式工具の材料はガラス、金属、シリコン、セラミックまたはＰＣＢであるとともに、台座材料にはガラスが含まれる。ある例では、積層層と再分散層がＬＣＤ表示パネル製造用設備内に形成される。あるいは、積層層と再分散層がＰＣＢタイプの設備内に形成される。 Die pasting materials include water-soluble adhesives, chemical solution-dissolving adhesives, reworkable adhesives, high melting point waxes, and removable tool materials are glass, metal, silicon, ceramic or PCB, and pedestal materials Includes glass. In one example, the laminated layer and the redispersion layer are formed in an LCD display panel manufacturing facility. Alternatively, the laminate layer and the redispersion layer are formed in a PCB type facility.

本発明は好ましい実施例と添付の図が利用されて説明される。すべての実施例は単に図解が目的で使用されるにすぎないことが認められなくてはならない。従って、本発明はこれらの好ましい実施例以外にも様々な実施例にも適用され得る。さらに、本発明はいずれの実施例にも制約されず、付録の請求項ならびにこれらの等価なものにのみ制約されるものである。 The present invention will be described with reference to the preferred embodiments and the accompanying figures. It should be appreciated that all examples are merely used for illustration purposes. Therefore, the present invention can be applied to various embodiments other than these preferred embodiments. Furthermore, the invention is not limited to any embodiment, but only to the appended claims and their equivalents.

本発明の実施のためには、ＬＣＤ向けといった大型パネルサイズのガラスが準備される。そして、裏重ね処理が行われ加工済みシリコンウェハーが所望厚みまで裏重ね加工が行われた後、加工済みウェハーと重ね加工済みウェハーとが複数の単一ダイにダイス加工される。図４を参照すると、ダイ再分散用工具４００が準備され、工具４００はダイの配置中の整列用の上面に整列パターン（図示されず）を有する。分離されたダイは取上げられると同時に、工具上で活性面４０２を裏にして工具４００上に置かれる。一時的にダイをくっつけるため工具表面に接着材料４０４が塗布されると同時に、解放条件のもとで解放可能となる。図３では、ダイ４０６には活性面にパッド４０８が含まれる。ダイの活性面４０２は裏返しになっていると同時に接着材料４０２に貼り付けられる。本方法は取上げ配置装置によってダイ間の間隔をできる限り小さくできる。 For the implementation of the present invention, a large panel size glass for LCD is prepared. Then, after the back-up process is performed and the processed silicon wafer is back-processed to a desired thickness, the processed wafer and the over-processed wafer are diced into a plurality of single dies. Referring to FIG. 4, a die redistribution tool 400 is provided, and the tool 400 has an alignment pattern (not shown) on the top surface for alignment during die placement. The separated dies are picked up and placed on the tool 400 with the active surface 402 facing back on the tool. The adhesive material 404 is applied to the tool surface to temporarily attach the die, and at the same time it can be released under release conditions. In FIG. 3, die 406 includes pads 408 on the active surface. The active surface 402 of the die is turned over and is affixed to the adhesive material 402 at the same time. In this method, the distance between the dies can be made as small as possible by the picking and placing device.

接着材料は水溶性接着剤、リワーカブル接着剤、高融点ワックス、化学溶液溶解接着剤等といった弾性材料であって良く、剛性のある工具用の材料はガラス、金属、合金、シリコン、セラミック、またはＰＣＢであってよかろう。次の段階はダイの成型であり、樹脂５１０といった成型材料が図５Ａに示されるように工具４００とダイ４０６上でプリントされるかあるいは成型される。次いで、工具４００は工具をユーザーが選定する接着剤に応じて溶液、水、高温環境の中で処理してダイから解放される。あるいは、図５Ｂに示されるように、樹脂５１０が所望の厚みまで部分的に除去されてから基板５２０がダイまたは成型材料５１０（コアペースト）に貼り付けられる。基板５２０はガラス、金属、合金、シリコン、セラミックまたはＰＣＢであってもよい。基板に貼る材料はコアーペーストと同様でありえる。ある実施例では、材料５２０はガラス、金属、合金、セラミックまたはＰＣＢであっても良い。 The adhesive material may be an elastic material such as a water-soluble adhesive, a reworkable adhesive, a high melting point wax, a chemical solution dissolving adhesive, etc., and the material for the rigid tool may be glass, metal, alloy, silicon, ceramic, or PCB That's fine. The next step is die molding, where a molding material such as resin 510 is printed or molded on tool 400 and die 406 as shown in FIG. 5A. The tool 400 is then released from the die by treating the tool in solution, water, or a high temperature environment depending on the adhesive selected by the user. Alternatively, as shown in FIG. 5B, after the resin 510 is partially removed to a desired thickness, the substrate 520 is attached to the die or molding material 510 (core paste). The substrate 520 may be glass, metal, alloy, silicon, ceramic or PCB. The material applied to the substrate can be the same as the core paste. In some embodiments, material 520 may be glass, metal, alloy, ceramic, or PCB.

図６を参照してもらうと、その上にダイ４０６が配置された成型材料５１０の上面が示される。これにはダイ４０６が母材の形で配置され、ダイ４０６間のピッチはユーザーによる所期の値に決定可能であるとともに、本発明は空間スペース節約とコスト削減かつダイの工具上への高精度配置の目的で実施可能であることが分かる。単一ユニット基板５００が図示の直立側面で示される。複数の単一ユニット６００が配置可能で母材の形のガラス台座６１０上の大型サイズパネルとなる。ダイを伴った小型の単一ユニット６００が母材の形での台座６１０に配置される。台座はガラスであるのが好ましい。こうして、バッチ処理が本発明によって行われ得る。従って、処理量はかなり向上すると同時にコストも削減される。ＬＣＤタイプ処理に関して、複数の小型ユニット６００がＬＣＤガラス６１０に配置可能で、引き続く処理のための大型サイズの基板が形成される。図において、ＬＣＤガラスはパネルの鋸断（単一化）前の処理中に台座として加工される。あるいは、単一ユニット６００が上述のような大型母材の形での形成を省いてに直接、加工が可能である。 Referring to FIG. 6, the top surface of the molding material 510 with the die 406 disposed thereon is shown. For this purpose, the dies 406 are arranged in the form of a base material, and the pitch between the dies 406 can be determined by the user's desired value, and the present invention saves space and costs and increases the cost of the dies on the tool. It can be seen that it can be implemented for the purpose of precision placement. A single unit substrate 500 is shown with the upright side shown. A plurality of single units 600 can be arranged to form a large-size panel on a glass base 610 in the form of a base material. A small single unit 600 with a die is placed on a pedestal 610 in the form of a matrix. The pedestal is preferably glass. Thus, batch processing can be performed according to the present invention. Therefore, the throughput is significantly improved and the cost is reduced. For LCD type processing, a plurality of small units 600 can be placed on the LCD glass 610 to form a large size substrate for subsequent processing. In the figure, the LCD glass is processed as a pedestal during processing prior to panel sawing. Alternatively, the single unit 600 can be processed directly without forming the large base material as described above.

次に、図７に示されるように、積層層処理とエレクトロプレイティング処理が行われて、積層層７２０と再分散層７３０が作り出される。この処理は本技術ではよく知られており、詳細説明は省略される。引き続き、ハンダボールの配置とハンダペーストプリント段階が行われ、ＩＲによるハンダの再注入が行われ、最終端子が製作される。ハンダボール７４０は再分散層上に形成されよう。この単一化処理は次にダイ分離に利用され、最終テスト後に個別のチップ８００が形成される。ガラス台座を採用する方法が取られる場合には、ガラス台座はダイ分離前に除去されなくてはならない。 Next, as shown in FIG. 7, a laminated layer process and an electroplating process are performed to create a laminated layer 720 and a redispersed layer 730. This process is well known in the art and will not be described in detail. Subsequently, solder ball placement and solder paste printing steps are performed, solder re-injection is performed by IR, and the final terminals are manufactured. Solder balls 740 will be formed on the redispersion layer. This singulation process is then used for die separation, and individual chips 800 are formed after the final test. If a method using a glass pedestal is taken, the glass pedestal must be removed prior to die separation.

ＬＣＤパネルとＰＣＢ/基板製造設備は半導体装置を採用せずに積層層、塗布、暴露、スパッタリングとエッチング処理に応用される。知られている通り、半導体設備はＬＣＤ設備にとって非常に高価である。本発明により製造コストがかなり削減可能である。本発明によりガラス台座方法の用途が示唆され、長方形タイプの基板はウェハー（円形）タイプ基板よりも多くのチップがその上に乗せることができる。従って、より多くのパッケージユニットが同時処理可能でバッチ処理が行われる。ＬＣＤ表示パネルタイプの整列精度はおよそ１ミクロンメーターであるとともに、ＰＣＢ/基板タイプはおよそ２ミクロンメーターである。本発明の精度はチップ上の積層層の要件を満足できる。 LCD panel and PCB / substrate manufacturing equipment is applied to laminated layers, coating, exposure, sputtering and etching processes without adopting semiconductor devices. As is known, semiconductor equipment is very expensive for LCD equipment. The present invention can significantly reduce manufacturing costs. The present invention suggests the use of the glass pedestal method, and a rectangular substrate can have more chips on it than a wafer (circular) substrate. Accordingly, more package units can be processed simultaneously and batch processing is performed. The alignment accuracy of the LCD display panel type is approximately 1 micrometer and the PCB / substrate type is approximately 2 micrometers. The accuracy of the present invention can satisfy the requirements of the laminated layer on the chip.

具体的な実施例が図解され、説明したが、技術の専門家にとっては付録の請求項によってのみ制約されると意図されるものから逸脱することなく様々な変更が可能であることは明らかであろう。 While specific embodiments have been illustrated and described, it will be apparent to those skilled in the art that various modifications can be made without departing from what is intended to be limited only by the appended claims. Let's go.

本発明の上述の目標とその他の特色および利点は図面と関連させて行われる以降の詳細説明を読めばさらに明らかとなろう。すなわち、 The foregoing goals and other features and advantages of the present invention will become more apparent upon reading the following detailed description taken in conjunction with the drawings. That is,

従来のパッケージ構造の全体模式図。The whole schematic diagram of the conventional package structure. 本発明によるダイの工具上への貼り付け段階を示す全体模式図。The whole schematic diagram which shows the sticking step on the tool of die | dye by this invention. Ａ、Ｂは本発明による成型段階を示す全体模式図。A and B are schematic diagrams showing the entire molding stage according to the present invention. 本発明による母材の形での小型ユニットの台座上への配置段階を示す全体模式図。The whole schematic diagram which shows the arrangement | positioning step on the base of the small unit in the form of the base material by this invention. 本発明による積層層、ハンダボールの形成段階を示す全体模式図。The whole schematic diagram which shows the formation step of the laminated layer by this invention, and a solder ball. 本発明によるダイの分離段階を示す全体模式図。The whole schematic diagram which shows the isolation | separation step of die | dye by this invention.

Claims (6)

ダイの取上げと工具上への設置、ダイの活性面の前記工具への取付、成型材料による前記ダイの成型、ユニット形成のための前記ダイからの前記工具の除去、母材の形での台座上への複数の前記ユニットの配置、積層層、前記台座上の前記ダイ上の再分散層の形成、前記ダイ上のハンダボールの形成、前記台座の除去ならびに前記ダイの分離が含まれる半導体パッケージ方法。 Picking up the die and placing it on the tool, attaching the active surface of the die to the tool, molding the die with molding material, removing the tool from the die to form a unit, pedestal in the form of a base material A semiconductor package comprising the placement of a plurality of the units above, a layer stack, formation of a redispersion layer on the die on the pedestal, formation of solder balls on the die, removal of the pedestal and separation of the die Method. さらに、前記ダイの前記工具上への取付前の段階のシリコンウェハーの所望厚さへの裏重ね加工、前記重ね加工ウェハーの単独ダイへのダイス切りが含まれる請求項１記載の半導体パッケージ方法。 The semiconductor package method according to claim 1, further comprising: back-side processing of a silicon wafer to a desired thickness before mounting the die on the tool, and dicing of the over-processed wafer into a single die. 前記成型段階に前記ダイとダイ背面間に樹脂充填が含まれ、さらに前記工具除去前の前記成型材料上への基板形成段階が含まれ、前記積層層と再分散層がＬＣＤ表示パネル製造用設備またはＰＣＢ/基板製造設備内部に形成される請求項１記載の半導体パッケージ方法。 The molding step includes resin filling between the die and the back surface of the die, and further includes a substrate forming step on the molding material before removing the tool, and the laminated layer and the redispersion layer are facilities for manufacturing an LCD display panel. 2. The semiconductor package method according to claim 1, wherein the semiconductor package method is formed inside a PCB / substrate manufacturing facility. ダイの取上げと工具上への設置、ダイ活性面の前記工具上への取付、成型材料による前記ダイの成型、ユニット形成のための前記工具の前記ダイからの除去、前記ユニット上の前記ダイ上の積層層、再分散層の形成、前記ダイ上のハンダボールの形成、ならびに前記ダイの分離が含まれる半導体パッケージ方法。 Die picking and placement on tool, mounting die active surface on the tool, molding the die with molding material, removing the tool from the die to form a unit, on the die on the unit A semiconductor package method comprising: forming a stacked layer, forming a redispersion layer, forming a solder ball on the die, and separating the die. さらに前記工具上への前記ダイ取付前の段階のシリコンウェハーの所望厚さへの裏重ね加工、前記重ね加工ウェハーの単独ダイへのダイス加工の段階が含まれる請求項４記載の半導体パッケージ方法。 The semiconductor package method according to claim 4, further comprising: a backside processing of the silicon wafer to a desired thickness before the die is mounted on the tool, and a step of dicing the overlapped wafer into a single die. さらに前記工具除去前の前記成型材料上への基板形成段階が含まれ、前記成型段階に前記ダイおよびダイ背面間の樹脂充填が含まれ、前記積層層と再分散層がＬＣＤ表示パネル製造設備またはＰＣＢ/基板製造設備内部に形成される請求項４記載の半導体パッケージ方法。 Furthermore, a substrate forming step on the molding material before removing the tool is included, and the molding step includes resin filling between the die and the back surface of the die, and the laminated layer and the re-dispersion layer are LCD display panel manufacturing equipment or 5. The semiconductor package method according to claim 4, wherein the semiconductor package method is formed inside a PCB / substrate manufacturing facility.
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