JP2005332999A - 回路装置およびその製造方法、板状体 - Google Patents
回路装置およびその製造方法、板状体 Download PDFInfo
- Publication number
- JP2005332999A JP2005332999A JP2004150362A JP2004150362A JP2005332999A JP 2005332999 A JP2005332999 A JP 2005332999A JP 2004150362 A JP2004150362 A JP 2004150362A JP 2004150362 A JP2004150362 A JP 2004150362A JP 2005332999 A JP2005332999 A JP 2005332999A
- Authority
- JP
- Japan
- Prior art keywords
- separation groove
- conductive
- conductive pattern
- back surface
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 239000011888 foil Substances 0.000 claims abstract description 102
- 229920005989 resin Polymers 0.000 claims abstract description 66
- 239000011347 resin Substances 0.000 claims abstract description 66
- 238000005530 etching Methods 0.000 claims abstract description 53
- 238000000034 method Methods 0.000 claims abstract description 46
- 238000007789 sealing Methods 0.000 claims abstract description 40
- 238000000926 separation method Methods 0.000 claims description 180
- 239000011248 coating agent Substances 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 7
- 239000011159 matrix material Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000002955 isolation Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 description 8
- 229910001111 Fine metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 239000004593 Epoxy Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000005219 brazing Methods 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 239000004734 Polyphenylene sulfide Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920000069 polyphenylene sulfide Polymers 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structure Of Printed Boards (AREA)
- Drying Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】 本発明の回路装置の製造方法では、導電箔40の表面に第1の分離溝41を設けて、形成予定の導電パターンを凸状に形成する。更に、第1の分離溝41が形成された領域に対応した導電箔40の裏面に第2の分離溝51を設ける。そして、回路素子12の固着およびその電気的接続が終了した後に、樹脂封止を行う。その後に、導電箔40の裏面のエッチングを行うことで、各導電パターン11の分離を行う。
【選択図】図6
Description
本形態では、本発明の回路装置の一例を説明する。図1を参照して、本形態の回路装置10Aの構成を説明する。図1(A)は回路装置10Aの平面図であり、図1(B)はその断面図である。
<第2の実施の形態>
図3から図9を参照して回路装置10の製造方法を説明する。
<第3の実施の形態>
本形態では、図10および図11を参照して、他の形態の回路装置の製造方法を説明する。本形態の回路装置の製造方法は、上述した第2の実施の形態と基本的には同様であり、相違点は、導電パターン11および第1の分離溝41を被覆する被覆樹脂61が形成される点にある。この相違点を中心に以下にて本形態の回路装置の製造方法を説明する。
11 導電パターン
12 回路素子
13 封止樹脂
14 金属細線
15 外部電極
16 レジスト
40 導電箔
41A〜41D 第1の分離溝
42 ブロック
43 スリット
44 ガイド孔
45 ユニット
51A〜51D 第2の分離溝
Claims (18)
- 導電箔を用意する工程と、
前記導電箔の表面に第1の分離溝を形成することで、凸状に突出する導電パターンを形成する工程と、
前記第1の分離溝に対応する箇所の前記導電箔の裏面に第2の分離溝を設ける工程と、
前記導電パターンに電気的に回路素子を接続する工程と、
前記第1の分離溝に充填されて前記回路素子を被覆するように封止樹脂を形成する工程と、
前記第1の分離溝に充填された前記封止樹脂が露出するまで前記導電箔の裏面を除去する工程とを具備することを特徴とする回路装置の製造方法。 - 表面に第1の分離溝により凸状に突出する導電パターンが形成され、前記第1の分離溝に対応する箇所の裏面に第2の分離溝が形成された導電箔を用意する工程と、
前記導電パターンに電気的に回路素子を接続する工程と、
前記第1の分離溝に充填されて前記回路素子を被覆するように封止樹脂を形成する工程と、
前記第1の分離溝に充填された前記封止樹脂が露出するまで前記導電箔の裏面を除去する工程とを具備することを特徴とする回路装置の製造方法。 - 前記第1の分離溝および前記第2の分離溝は、ウェットエッチングにより同時に形成されることを特徴とする請求項1または請求項2記載の回路装置の製造方法。
- 前記導電箔を厚み方向に貫通する貫通孔を設け、
前記第1の分離溝、前記第2の分離溝および前記貫通孔は、ウェットエッチングにより同時に形成されることを特徴とする請求項1または請求項2記載の回路装置の製造方法。 - 前記導電箔の裏面の除去は、前記第2の分離溝が露出するように前記導電箔の裏面を選択的に被覆するエッチングマスクを介したウェットエッチングにより行うことを特徴とする請求項1または請求項2記載の回路装置の製造方法。
- 前記導電箔の裏面を全面的にエッチングすることにより、前記第1の分離溝に充填された前記絶縁性樹脂を露出させることを特徴とする請求項1または請求項2記載の回路装置の製造方法。
- 複数個の前記導電パターンにより1つの回路装置を構成するユニットが構成され、
前記ユニットは、前記導電箔の表面に複数個が形成され、
前記ユニット同士の間に設けられる前記第1の分離溝に対応する領域の前記導電箔の裏面には、複数の前記第2の分離溝を設けることを特徴とする請求項1または請求項2記載の回路装置の製造方法。 - 前記第1の分離溝を含んだ前記導電箔の表面を被覆樹脂にて被覆し、
前記被覆樹脂から部分的に露出する前記導電パターンと前記回路素子とを電気的に接続することを特徴とする請求項1または請求項2記載の回路装置の製造方法。 - 少なくともアイランドおよび前記アイランドに近接して設けられたパッドを構成する複数の導電パターンと、前記アイランドに実装され、前記パッドと電気的に接続された回路素子と、前記導電パターンの裏面を露出させて前記回路素子および前記導電パターンを封止する絶縁樹脂とを具備する回路装置に於いて、
前記導電パターン同士を離間させる分離溝から前記絶縁樹脂が外部に突出し、
前記導電パターンの裏面と側面とが連続する角部は滑らかに形成されることを特徴とする回路装置。 - 前記導電パターンから成る配線部が設けられ、
前記配線部の表面には、前記回路素子と電気的に接続されるパッド部が形成され、
前記配線部の裏面には、前記パッド部とは平面的に異なる箇所に外部接続電極が形成されることを特徴とする請求項9記載の回路装置。 - 前記導電パターンから成る配線部により電気的に接続される複数個の前記回路素子が内蔵されることを特徴とする請求項9記載の回路装置。
- 前記導電パターンが露出する前記絶縁性樹脂の裏面はレジストにより被覆され、
前記レジストに設けた開口部から前記導電パターンの平坦面が露出することを特徴とする請求項9記載の回路装置。 - ハーフエッチングにより形成された第1の分離溝により凸状に突出した導電パターンが一主面に形成され、
前記第1の分離溝に対応する領域の他の主面に、第2の分離溝を具備することを特徴とする板状体。 - 複数の前記導電パターンにより1つの回路装置を構成するユニットが形成され、
前記一主面には前記ユニットがマトリックス状に配置されることを特徴とする請求項13記載の板状体。 - 複数個の前記ユニットから成るブロックが前記一主面に形成され、
前記ブロックの内部に前記第1の分離溝により凸状に形成される位置合わせマークが形成されることを特徴とする請求項14記載の板状体。 - 前記第2の分離溝は、前記第1の分離溝よりも浅いことを特徴とする請求項13記載の板状体。
- 前記第1の分離溝は、実質的に同じ幅で形成されることを特徴とする請求項13記載の板状体。
- パワー系の素子が固着される予定の前記導電パターンに隣接する前記第1の分離溝は、他の第1の分離溝よりも広く形成されることを特徴とする請求項13記載の板状体。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004150362A JP4353853B2 (ja) | 2004-05-20 | 2004-05-20 | 回路装置の製造方法および板状体 |
TW094113629A TWI267153B (en) | 2004-05-20 | 2005-04-28 | Circuit device and manufacturing method for the same, plate shaped body |
KR1020050039160A KR100680666B1 (ko) | 2004-05-20 | 2005-05-11 | 회로 장치 및 그 제조 방법과 판상체 |
CNB2005100688436A CN100463127C (zh) | 2004-05-20 | 2005-05-12 | 电路装置及其制造方法 |
US11/131,638 US7476972B2 (en) | 2004-05-20 | 2005-05-17 | Circuit device, manufacturing method thereof, and sheet-like board member |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004150362A JP4353853B2 (ja) | 2004-05-20 | 2004-05-20 | 回路装置の製造方法および板状体 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005332999A true JP2005332999A (ja) | 2005-12-02 |
JP4353853B2 JP4353853B2 (ja) | 2009-10-28 |
Family
ID=35375712
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004150362A Expired - Fee Related JP4353853B2 (ja) | 2004-05-20 | 2004-05-20 | 回路装置の製造方法および板状体 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7476972B2 (ja) |
JP (1) | JP4353853B2 (ja) |
KR (1) | KR100680666B1 (ja) |
CN (1) | CN100463127C (ja) |
TW (1) | TWI267153B (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009055015A (ja) * | 2007-07-31 | 2009-03-12 | Seiko Epson Corp | 基板及びその製造方法、並びに半導体装置及びその製造方法 |
JP2009224674A (ja) * | 2008-03-18 | 2009-10-01 | Denso Corp | 電子装置およびその製造方法 |
WO2020240882A1 (ja) * | 2019-05-31 | 2020-12-03 | アオイ電子株式会社 | 半導体装置および半導体装置の製造方法 |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8163604B2 (en) * | 2005-10-13 | 2012-04-24 | Stats Chippac Ltd. | Integrated circuit package system using etched leadframe |
US7537965B2 (en) * | 2006-06-21 | 2009-05-26 | Delphi Technologies, Inc. | Manufacturing method for a leadless multi-chip electronic module |
TWI324815B (en) * | 2006-12-28 | 2010-05-11 | Advanced Semiconductor Eng | Recyclable stamp device and recyclable stamp process for wafer bond |
US7777310B2 (en) * | 2007-02-02 | 2010-08-17 | Stats Chippac Ltd. | Integrated circuit package system with integral inner lead and paddle |
US8018064B2 (en) * | 2007-05-31 | 2011-09-13 | Infineon Technologies Ag | Arrangement including a semiconductor device and a connecting element |
DE102007031490B4 (de) * | 2007-07-06 | 2017-11-16 | Infineon Technologies Ag | Verfahren zur Herstellung eines Halbleitermoduls |
US8274176B2 (en) | 2007-07-13 | 2012-09-25 | Samsung Electronics Co., Ltd. | Power supply apparatus |
US8350407B2 (en) | 2007-07-13 | 2013-01-08 | Samsung Electronics Co., Ltd. | High voltage power supply apparatus |
KR100977209B1 (ko) * | 2008-10-30 | 2010-08-20 | 윌테크놀러지(주) | 공간 변환기, 공간 변환기를 포함하는 프로브 카드 및 공간변환기의 제조 방법 |
JP5126370B2 (ja) * | 2008-12-16 | 2013-01-23 | 株式会社村田製作所 | 回路モジュール |
JP5529494B2 (ja) * | 2009-10-26 | 2014-06-25 | 株式会社三井ハイテック | リードフレーム |
US20110108966A1 (en) * | 2009-11-11 | 2011-05-12 | Henry Descalzo Bathan | Integrated circuit packaging system with concave trenches and method of manufacture thereof |
TWI420630B (zh) * | 2010-09-14 | 2013-12-21 | Advanced Semiconductor Eng | 半導體封裝結構與半導體封裝製程 |
US8519519B2 (en) * | 2010-11-03 | 2013-08-27 | Freescale Semiconductor Inc. | Semiconductor device having die pads isolated from interconnect portion and method of assembling same |
US8501517B1 (en) | 2012-04-09 | 2013-08-06 | Freescale Semiconductor, Inc. | Method of assembling pressure sensor device |
KR101374145B1 (ko) * | 2012-04-19 | 2014-03-19 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
KR20140060390A (ko) | 2012-11-09 | 2014-05-20 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지의 랜드 및 그 제조 방법과 이를 이용한 반도체 패키지 및 그 제조 방법 |
US9911685B2 (en) * | 2012-11-09 | 2018-03-06 | Amkor Technology, Inc. | Land structure for semiconductor package and method therefor |
US9824958B2 (en) * | 2013-03-05 | 2017-11-21 | Infineon Technologies Austria Ag | Chip carrier structure, chip package and method of manufacturing the same |
KR101665242B1 (ko) | 2015-03-20 | 2016-10-11 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 이의 제조 방법 |
WO2017029745A1 (ja) * | 2015-08-20 | 2017-02-23 | 三菱電機株式会社 | 電力用半導体装置 |
US11887916B2 (en) | 2020-09-09 | 2024-01-30 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1122778A3 (en) * | 2000-01-31 | 2004-04-07 | Sanyo Electric Co., Ltd. | Circuit device and manufacturing method of circuit device |
JP3778773B2 (ja) * | 2000-05-09 | 2006-05-24 | 三洋電機株式会社 | 板状体および半導体装置の製造方法 |
JP2001250884A (ja) * | 2000-03-08 | 2001-09-14 | Sanyo Electric Co Ltd | 回路装置の製造方法 |
JP3883784B2 (ja) * | 2000-05-24 | 2007-02-21 | 三洋電機株式会社 | 板状体および半導体装置の製造方法 |
JP3561683B2 (ja) * | 2000-09-04 | 2004-09-02 | 三洋電機株式会社 | 回路装置の製造方法 |
JP3600131B2 (ja) | 2000-09-04 | 2004-12-08 | 三洋電機株式会社 | 回路装置の製造方法 |
JP3609737B2 (ja) * | 2001-03-22 | 2005-01-12 | 三洋電機株式会社 | 回路装置の製造方法 |
DE10341186A1 (de) * | 2003-09-06 | 2005-03-31 | Martin Michalk | Verfahren und Vorrichtung zum Kontaktieren von Halbleiterchips |
-
2004
- 2004-05-20 JP JP2004150362A patent/JP4353853B2/ja not_active Expired - Fee Related
-
2005
- 2005-04-28 TW TW094113629A patent/TWI267153B/zh not_active IP Right Cessation
- 2005-05-11 KR KR1020050039160A patent/KR100680666B1/ko not_active IP Right Cessation
- 2005-05-12 CN CNB2005100688436A patent/CN100463127C/zh not_active Expired - Fee Related
- 2005-05-17 US US11/131,638 patent/US7476972B2/en not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009055015A (ja) * | 2007-07-31 | 2009-03-12 | Seiko Epson Corp | 基板及びその製造方法、並びに半導体装置及びその製造方法 |
JP2009224674A (ja) * | 2008-03-18 | 2009-10-01 | Denso Corp | 電子装置およびその製造方法 |
WO2020240882A1 (ja) * | 2019-05-31 | 2020-12-03 | アオイ電子株式会社 | 半導体装置および半導体装置の製造方法 |
JP2020198355A (ja) * | 2019-05-31 | 2020-12-10 | アオイ電子株式会社 | 半導体装置および半導体装置の製造方法 |
TWI767145B (zh) * | 2019-05-31 | 2022-06-11 | 日商青井電子股份有限公司 | 半導體裝置及半導體裝置之製造方法 |
EP3979319A4 (en) * | 2019-05-31 | 2023-06-28 | Aoi Electronics Co. Ltd. | Semiconductor device and method for manufacture of semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
KR100680666B1 (ko) | 2007-02-09 |
CN100463127C (zh) | 2009-02-18 |
US7476972B2 (en) | 2009-01-13 |
KR20060046043A (ko) | 2006-05-17 |
TW200539367A (en) | 2005-12-01 |
JP4353853B2 (ja) | 2009-10-28 |
TWI267153B (en) | 2006-11-21 |
US20050260796A1 (en) | 2005-11-24 |
CN1700431A (zh) | 2005-11-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4353853B2 (ja) | 回路装置の製造方法および板状体 | |
JP4093818B2 (ja) | 半導体装置の製造方法 | |
US8673690B2 (en) | Method for manufacturing a semiconductor device and a semiconductor device | |
US7163846B2 (en) | Method for manufacturing circuit devices | |
US7420266B2 (en) | Circuit device and manufacturing method thereof | |
JP3897704B2 (ja) | リードフレーム | |
US7417309B2 (en) | Circuit device and portable device with symmetrical arrangement | |
KR100662686B1 (ko) | 회로 장치 및 그 제조 방법 | |
JP4073308B2 (ja) | 回路装置の製造方法 | |
JP2006156574A (ja) | 回路装置およびその製造方法 | |
JP4283240B2 (ja) | 半導体装置の製造方法 | |
JP4183500B2 (ja) | 回路装置およびその製造方法 | |
JP2007180445A (ja) | 回路装置およびその製造方法 | |
JP2007036015A (ja) | 回路装置およびその製造方法 | |
JP4168494B2 (ja) | 半導体装置の製造方法 | |
JP3863816B2 (ja) | 回路装置 | |
JP4454422B2 (ja) | リードフレーム | |
JP4488819B2 (ja) | リードフレーム | |
JP3913622B2 (ja) | 回路装置 | |
JP2006339233A (ja) | 回路装置およびその製造方法 | |
JP2001135747A (ja) | 半導体装置の製造方法 | |
JP2006128501A (ja) | 回路装置およびその製造方法 | |
JP2004071900A (ja) | 回路装置 | |
JP2006186019A (ja) | 回路装置およびその製造方法 | |
JP2007036071A (ja) | 回路装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070413 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090216 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090317 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090515 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090630 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090728 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120807 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130807 Year of fee payment: 4 |
|
LAPS | Cancellation because of no payment of annual fees |